!" "# $#%& Data Manual February 2004 Digital Audio Products SLES001C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated Contents Section Title Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5 1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6 2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 2.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 2.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 2.3.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 2.3.2 Analog Line Input to Line Output . . . . . . . . . . . . . . . . . . . . . . 2−2 2.3.3 Stereo Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 2.3.4 Analog Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 2.3.5 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 2.3.6 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 2.4 Digital-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4 2.4.1 Audio Interface (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . 2−4 2.4.2 Audio Interface (Slave-Mode) . . . . . . . . . . . . . . . . . . . . . . . . 2−5 2.4.3 Three-Wire Control Interface (SDI) . . . . . . . . . . . . . . . . . . . . 2−6 2.4.4 Two-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−6 3 How to Use the DAC23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 3.1 Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 3.1.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 3.1.2 2-Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 3.1.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 3.2 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 3.2.1 Line Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 3.2.2 Line Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 3.2.3 Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 3.3 Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 3.3.1 Digital Audio-Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . 3−5 3.3.2 Audio Sampling Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7 3.3.3 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10 A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A−1 iii List of Illustrations Figure 2−1 2−2 2−3 2−4 2−5 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 iv Title System-Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . Two-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . . SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-Wire Compatible Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Line Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Right Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Left Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital De-Emphasis Filter Response − 44.1 kHz Sampling . . . . . . . . . . . Digital De-Emphasis Filter Response − 48 kHz Sampling . . . . . . . . . . . . DAC Digital Filter Response 0: USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . DAC Digital Filter Ripple 0: USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Digital Filter Response 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . DAC Digital Filter Ripple 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . DAC Digital Filter Response 2: USB Mode and Normal Modes . . . . . . . . DAC Digital Filter Ripple 2: USB Mode and Normal Modes . . . . . . . . . . . DAC Digital Filter Response 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . DAC Digital Filter Ripple 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . Page 2−4 2−4 2−5 2−6 2−6 3−1 3−2 3−5 3−6 3−6 3−6 3−7 3−10 3−11 3−11 3−11 3−12 3−12 3−12 3−13 3−13 3−13 1 Introduction The TLV320DAC23 is a high performance stereo DAC with highly integrated analog functionality. The DACs within the TLV320DAC23 are comprised of multibit sigma-delta technology with integrated over-sampling digital interpolation filters. Supported data transfer word lengths are 16, 20, 24, and 32 bits with sample rates from 8 kHz to 96 kHz. The DAC sigma-delta modulator features a second order multibit architecture with up to 100 dBA SNR at audio sample rates up to 96 kHz. This enables high quality digital audio playback capability while consuming less than 19 mW during playback only. The TLV320DAC23 is the ideal choice for portable digital audio player applications such as MP3 digital audio players. Integrated analog features consist of stereo line inputs with an analog bypass path and a stereo headphone amplifier with analog volume control and mute. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The analog bypass path allows use of the stereo line inputs and the headphone amplifier with analog volume control while completely bypassing the DAC, thus enabling further design flexibility such as integrated FM tuners. While the TLV320DAC23 supports the industry standard over-sample rates of 256 fs and 384 fs, unique over-sample rates of 250 fs and 272 fs are provided which optimize interface considerations in designs using TI C54x DSPs and USB data interfaces. A single 12-MHz crystal can be used to supply clocking to the DSP, USB, and DAC. The TLV320DAC23 features an internal oscillator which, when connected to a 12-MHz external crystal, will provide a system clock to the DSP and other peripherals at either 12 MHz or 6 MHz using an internal clock buffer and selectable divider. Audio sample rates of 48 kHz and CD standard rates of 44.1 kHz are directly supported from a 12-MHz master clock with 250 fs and 272 fs over-sample rates. Low power consumption and flexible power management allow selective shutdown of DAC functions, thus extending battery life in portable applications. Couple this design solution with the industry’s smallest package, the TI proprietary MicroStar Junior using only 25 mm2 of board area, powerful portable stereo audio designs are easily realizable in a cost effective, space saving total analog solution. MicroStar Junior is a trademark of Texas Instruments. 1−1 1.1 Features • High-Performance Stereo DAC − − − − • Software control via TI McBSP-compatible multiprotocol serial port − − • 2-wire-compatible and SPI-compatible serial port protocols Glueless interface to TI McBSPs Audio data input/output via TI McBSP compatible programmable audio interface − − − − − − I2S-compatible interface Standard I2S, MSB, or LSB justified data transfers 16/20/24/32-bit word lengths Audio master/slave timing capability optimized for TI DSPs (250/272 fs) Industry-standard master/slave support also provided (256/384 fs) Glueless interface to TI McBSPs • Stereo line inputs • Stereo line outputs − Analog stereo mixer for DAC and analog bypass path • Analog volume control with mute • Highly efficient linear headphone amplifier − • • 18-mW power consumption during playback mode Standby power consumption <150 µW Power-down power consumption <15 µW Industry’s smallest package: 32-Pin TI proprietary MicroStar Junior − − − • 30 mW into 32 Ω from a 3.3-V analog supply voltage Flexible power management under total software control − − − 1−2 100-dB SNR multibit sigma-delta ADC (A-weighted at 48 kHz) 1.42 V – 3.6 V digital supply: compatible with TI C54x DSP core voltages 2.7 V – 3.6 V analog supply: compatible TI C54x DSP buffer voltages 8-kHz – 96-kHz sampling-frequency support 25 mm2 total board area 28-Pin TSSOP available (62 mm2 total board area) 28-Pin QFN available (25 mm2 total board area) Ideally suitable for portable solid-state audio players and recorders 1.2 Functional Block Diagram TLV320DAC23 AVDD 50 kΩ VDAC CS 1.0X Control Interface VMID 50 kΩ 1.0X AGND SDI SCLK MODE VMID Bypass RLINEIN LLINEIN HPVDD HPGND Headphone Driver DAC Select 6 to −73 dB, 1-dB Steps Σ−∆ DAC Σ RHPOUT Digital Filters DVDD BVDD DGND ROUT VDAC LOUT Σ−∆ DAC Σ LHPOUT Headphone Driver 6 to −73 dB, 1-dB Steps LRCIN XTI/MCLK CLKIN Divider (1x, 1/2x) OSC XTO CLKOUT Digital Audio Interface DIN BCLK CLKOUT (1x, 1/2x) 1−3 1.3 Terminal Assignments NC XTO DVDD DGND BVDD CLKOUT BCLK DIN NC GQE PACKAGE (TOP VIEW) 25 24 23 22 21 20 19 18 17 HPVDD 29 13 MODE LHPOUT 30 12 CS RHPOUT 31 11 LLINEIN HPGND 32 10 RLINEIN 2 3 4 5 6 7 8 9 NC 1 NC SDIN NC NC 14 VMID SCLK 28 AGND NC 15 AVDD XTI/MCLK 27 ROUT 16 LOUT 26 NC LRCIN PW PACKAGE (TOP VIEW) BVDD CLKOUT BCLK DIN LRCIN NC NC HPVDD LHPOUT RHPOUT HPGND LOUT ROUT AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC − No internal connection 1−4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DGND DVDD XTO XTI/MCLK SCLK SDIN MODE CS LLINEIN RLINEIN NC NC VMID AGND BCLK CLKOUT BVDD DGND DVDD XTO XTI/MCLK 28 27 26 25 24 23 22 RHD PACKAGE (TOP VIEW) 4 18 CS HPVDD 5 17 LLINEIN LHPOUT 6 16 RLINEIN RHPOUT 7 15 NC AGND 14 NC NC MODE 13 19 VMID 3 12 NC 11 SDIN AVDD 20 10 2 ROUT LRCIN 9 SCLK LOUT 21 8 1 HPGND DIN NC − No internal connection 1.4 Ordering Information PACKAGE TA 32-Pin MicroStar Junior GQE 28-Pin TSSOP PW 28-Pin QFN RHD −10°C to 70°C TLV320DAC23GQE TLV320DAC23PW TLV320DAC23RHD −40°C to 85°C TLV320DAC23IGQE TLV320DAC23IPW TLV320DAC23IRHD 1−5 1.5 Terminal Functions TERMINAL NUMBER NAME DESCRIPTION I/O GQE PW RHD AGND 5 15 12 − Analog supply return AVDD 4 14 11 − BCLK 23 3 28 I/O Analog supply input. Voltage level is 3.3 V nominal. I2S serial-bit clock. In audio master mode, the DAC23 generates this signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP. BVDD 21 1 26 − Buffer supply input. Voltage range is from 2.7 V to 3.6 V. CLKOUT 22 2 27 O Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of XTI. Frequency selection is controlled by bit X in control register XX. CS 12 21 18 I DIN 24 4 1 I Control port input latch/address select. For SPI control mode this input acts as the data latch control. For 2-wire control mode this input defines the seventh bit in the device address field. See Section 3.1 for details. I2S format serial data input to the sigma-delta stereo DAC DGND 20 28 25 − Digital supply return DVDD 19 27 24 − Digital supply input. Voltage range is 1.4 V to 3.6 V. HPGND 32 11 8 − Analog headphone amplifier supply return HPVDD 29 8 5 − Analog headphone amplifier supply input. Voltage level is 3.3 V nominal. LHPOUT 30 9 6 O Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1.0 VRMS. Gain of –73 dB to 6 dB is provided in 1-dB steps. LLINEIN 11 20 17 I Left stereo-line input channel LOUT 2 12 9 O LRCIN 26 5 2 I/O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS. I2S DAC-word clock signal. In audio master mode, the DAC23 generates this framing signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP. MODE 13 22 19 I Serial interface mode input. See Section 3.1 for details. 1, 7, 8, 9, 17, 25, 27, 28 6, 7, 17,18 3, 4, 14, 15 − Not Used—No internal connection RHPOUT 31 10 7 O Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1.0 VRMS. Gain of −73 dB to 6 dB is provided in 1-dB steps. RLINEIN 10 19 16 I Right stereo-line input channel ROUT 3 13 10 O Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS. SCLK 15 24 21 I Control port serial data clock. For both SPI and 2-wire control modes this is the serial clock input. See Section 3.1 for details. SDIN 14 23 20 I Control port serial data input. For both SPI and 2-wire control modes this is the serial data input and also is used to select the control protocol after reset. See Section 3.1 for details. VMID 6 16 13 I Midrail voltage decoupling input. 10-µF and 0.1-µF capacitors should be connected in parallel to this terminal for noise filtering. Voltage level is 1/2 AVDD nominal. XTI/MCLK 16 25 22 I Crystal or external clock input. Used for derivation of all internal clocks on the DAC23. XTO 18 26 23 O Crystal output. Connect to external crystal for applications where the DAC23 is the audio timing master. Not used in applications where external clock source is used. NC 1−6 2 Specifications 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3.63 V Analog supply return to digital supply return, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 0 .3 V Input voltage range, all input signals: Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: DVDD may not exceed BVDD + 0.3V; BVDD may not exceed AVDD + 0.3V or HPVDD + 0.3. 2.2 Recommended Operating Conditions MIN NOM MAX 2.7 3.3 3.6 V Digital buffer supply voltage, BVDD (see Note 2) 2.7 3.3 3.6 V Digital core supply voltage, DVDD (see Note 2) 1.42 1.5 3.6 Analog supply voltage, AVDD, HPVDD (see Note 2) Analog input voltage, (AVDD = 3.3 V) UNIT V 1 VRMS kΩ CLKOUT digital output load capacitance 20 pF All other digital output load capacitance 10 pF Stereo-line output load capacitance 50 pF Stereo line output load resistance Headphone amplifier output load resistance 10 XTI master clock Input DAC conversion rate Operating free-air temperature, TA Ω 0 −10 18.43 MHz 96 kHz 70 °C NOTE 2: Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND. 2−1 2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Master Mode, XTI = 12 MHz, (unless otherwise stated) 2.3.1 DAC 2.3.1.1 Load = 10 kΩ, 50 pF PARAMETER TEST CONDITIONS MIN TYP 90 100 0-dB full-scale output voltage Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5) Dynamic range, A-weighted (see Note 5) 1.0 AVDD = 3.3 V AVDD = 2.7 V AVDD = 3.3 V AVDD = 3.3 V Total harmonic distortion (THD) AVDD = 2.7 V Power supply rejection ratio fs = 44.1kHz fs = 96 kHz fs = 44.1 kHz 2.3.2 UNIT VRMS 98 dB 93 85 90 1 kHz, 0 dB –88 1 kHz, −3 dB −92 1 kHz, 0 dB −88 1 kHz, −3 dB −92 1 kHz, 100 mVpp DAC channel separation THD+N MAX AVDD=3.3 V, 1 kHz, 0dB dB –80 dB −80 dB 50 dB 100 dB −84 −79 TYP MAX dB Analog Line Input to Line Output 2.3.2.1 Load = 10 kΩ, 50 pF, no gain on input PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage Signal-to-noise ratio, (SNR) A-weighted, 0-dB gain (see Notes 3, 5) 1.0 AVDD = 3.3 V AVDD = 3.3 V Total harmonic distortion (THD) AVDD = 2.7 V 90 UNIT VRMS 95 dB 1 kHz, 0 dB –86 –80 1 kHz, −3 dB −92 −86 1 kHz, 0 dB −86 1 kHz, −3 dB −92 dB dB Power supply rejection ratio 1 kHz, 100 mVpp 50 dB Mute attenuation 1 kHz, 0 dB 80 dB 24 k Ω Input resistance 2−2 10 k 2.3.3 Stereo Headphone Output PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage TYP MAX 1.0 Maximum output power, PO RL = 32 Ω 30 RL = 16 Ω 40 Signal-to-noise ratio, A-weighted (see Note 4) AVDD = 3.3 V 90 Total harmonic distortion AVDD = 3.3 V, 1 kHz output, into 32Ω Power supply rejection ratio 1 kHz, 100 mVpp Programmable gain 1 kHz output mW 97 dB PO = 10 mW −60 PO = 20 mW −40 dB 50 dB −73 6 Programmable-gain step size Mute attenuation UNIT VRMS 1 kHz output dB 1 dB 80 dB NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. 4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in higher THD + N and lower SNR and dynamic range readings than shown in the electrical characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 5. Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over a 20-Hz to 20-kHz bandwidth. 2.3.4 Analog Reference Levels PARAMETER MIN TYP Reference voltage, VMID AVDD/2 − 50 mV Divider resistance, RVMID 40 2.3.5 V 60 kΩ Digital I/O VIL VIH Input low level VOL VOH Output low level MIN TYP MAX UNIT 0.3 × BVDD V 0.7 × BVDD Input high level V 0.1 × BVDD 0.9 × BVDD Output high level V V Supply Current PARAMETER ITOT UNIT AVDD/2 + 50 mV 50 PARAMETER 2.3.6 MAX Total supply current, no input signal (3.3 V supply) MIN TYP Line playback only (Clk power off, 50 Ω) 6 Line playback only (Clk power on, 50 Ω) 15 Analog bypass (line in to line out) 3 Power down Oscillator enabled 1.5 Oscillator disabled 0.01 MAX UNIT 8 mA 0.025 2−3 2.4 Digital-Interface Timing PARAMETER MIN High 18 Low 18 tw(1) tw(2) System-clock pulse duration, MCLK/XTI tc(1) System-clock period, MCLK/XTI MAX Propagation delay, CLKOUT UNIT ns 54 Duty cycle, MCLK/XTI tpd(1) TYP ns 40/60% 60/40% 0 10 ns tc(1) tw(1) tw(2) MCLK/XTI tpd(1) CLKOUT CLKOUT (Div 2) Figure 2−1. System-Clock Timing Requirements 2.4.1 Audio Interface (Master Mode) PARAMETER MIN 0 TYP MAX Propagation delay, LRCIN Setup time, DIN 10 ns th(1) Hold time, DIN 10 ns BCLK tpd(2) LRCIN DIN tsu(1) th(1) Figure 2−2. Master-Mode Timing Requirements 2−4 10 UNIT tpd(2) tsu(1) ns 2.4.2 Audio Interface (Slave-Mode) PARAMETER tw(3) tw(4) Pulse duration, BCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(2) tsu(2) Clock period, BCLK 50 ns Setup time, DIN 10 ns th(2) tsu(3) Hold time, DIN 10 ns Setup time, LRCIN 10 ns th(3) Hold time, LRCIN 10 ns tc(2) tw(4) tw(3) BCLK LRCIN tsu(2) th(3) tsu(3) DIN th(2) Figure 2−3. Slave-Mode Timing Requirements 2−5 2.4.3 Three-Wire Control Interface (SDI) PARAMETER tw(5) tw(6) Clock pulse duration, SCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(3) tsu(4) Clock period, SCLK 80 ns Clock rising edge to CS rising edge, SCLK 60 ns tsu(5) th(4) Setup time, SDIN to SCLK 20 ns 20 ns tw(7) tw(8) Hold time, SCLK to SDIN Pulse duration, CS High 20 Low 20 ns tw(8) CS tc(3) tw(5) tw(6) tsu(4) SCLK tsu(5) th(4) LSB DIN Figure 2−4. Three-Wire Control Interface Timing Requirements 2.4.4 Two-Wire Control Interface PARAMETER tw(9) Clock pulse duration, SCLK tw(10) MIN High 1.3 Low 600 0 TYP MAX UNIT µs ns f(sf) Clock frequency, SCLK th(5) tsu(6) Hold time (start condition) 600 Setup time (start condition) 600 th(6) tsu(7) Data hold time tr tf Rise time, SDIN, SCLK 300 ns Fall time, SDIN, SCLK 300 ns tsu(8) Setup time (stop condition) tw(9) tw(10) SCLK th(6) tsu(7) tsu(8) DIN Figure 2−5. Two-Wire Control Interface Timing Requirements 2−6 ns 100 600 kHz ns 900 Data setup time th(5) 400 ns ns ns 3 How to Use the DAC23 3.1 Control Interfaces The TLV320DAC23 has many programmable features. The control interface is used to program the registers of the device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level. 3.1.1 MODE INTERFACE 0 2-wire 1 SPI SPI In SPI mode, SDI carries the serial data, SCLK is the serial clock and CS latches the data word into the TLV320DAC23. The interface is compatible with microcontrollers and DSPs with an SPI interface. A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising edge on CS after the sixteenth rising clock edge latches the data word into the DAC (see Figure 3-1). The control word is divided into two parts. The first part is the address block, the second part is the data block: B[15:9] B[8:0] Control address bits Control data bits CS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SCLK SDI B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 MSB B4 B3 B2 B1 B0 LSB Figure 3−1. SPI Timing 3.1.2 2-Wire In 2-wire mode, the data transfer uses SDI for the serial data and SCLK for the serial clock. The start condition is a falling edge on SDIN while SCLK is high. The seven bits following the start condition determine the device on the 2-wire bus that receives the data. R/W determines the direction of the data transfer. The TLV320DAC23 is a write only device and responds only if R/W is 0. The device operates only as a slave device whose address is selected by setting the state of the CS pin as follows. CS STATE (Default = 0) ADDRESS 0 0011010 1 0011011 The device that recognizes the address responds by pulling SDI low during the ninth clock cycle, acknowledging the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a rising edge on SDI when SCLK is high (see Figure 3-2). 3−1 The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block: B[15:9] B[8:0] Control address bits Control data bits Start Stop 1 SCLK 7 ADDR SDI 8 9 1 8 9 1 8 R/W ACK B15 − B8 ACK B7 − B0 9 ACK Figure 3−2. 2-Wire Compatible Timing 3.1.3 Register Map The TLV320DAC23 has the following set of registers, which are used to program the modes of operation. ADDRESS REGISTER 0000000 Left line input channel control 0000001 Right line input channel control 0000010 Left channel headphone volume control 0000011 Right channel headphone volume control 0000100 Analog audio path control 0000101 Digital audio path control 0000110 Power down control 0000111 Digital audio interface format 0001000 Sample rate control 0001001 Digital interface activation 0001111 Reset register Left Line Input Channel Control (Address: 0000000) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function LRS LIM X X X X X X X Default 0 1 0 0 0 0 0 0 0 LRS Left/right line simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Left line input mute 0 = Normal 1 = Muted Reserved LIM X Right Line Input Channel Control (Address: 0000001) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RLS RIM X X X X X X X Default 0 1 0 0 0 0 0 0 0 RLS RIM X 3−2 Right/left line simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Right line input mute 0 = Normal 1 = Muted Reserved Left Channel Headphone Volume Control (Address: 0000010) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 Default 0 1 1 1 1 1 0 0 1 LRS Left/right headphone channel simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Left-channel zero-cross detect Zero-cross detect 0 = Off 1 = On Left Headphone volume control (1111001 = 0 dB default) 1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute), any thing below 0110000 does nothing − you are still muted LZC LHV[6:0] Right Channel Headphone Volume Control (Address: 0000011) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RLS RZC RHV6 RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 Default 0 1 1 1 1 1 0 0 1 RLS Right/left headphone channel simultaneous volume/mute Update Simultaneous update 0 = Disabled 1 = Enabled Right-channel zero-cross detect Zero-cross detect 0 = Off 1 = On Right headphone volume control (1111001 = 0 dB default) 1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute), any thing below 0110000 does nothing − you are still muted RZC RHV[6:0] Analog Audio Path Control (Address: 0000100) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X DAC BYP X X X Default 0 0 0 0 0 1 0 1 0 DAC BYP X DAC select Bypass Reserved 0 = DAC off 0 = Disabled 1 = DAC selected 1 = Enabled Digital Audio Path Control (Address: 0000101) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X DACM DEEMP1 DEEMP0 X Default 0 0 0 0 0 1 0 0 0 DACM DEEMP[1:0] X DAC soft mute De-emphasis control Reserved 0 = Disabled 00 = Disabled 1 = Enabled 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz Power Down Control (Address: 0000110) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X OFF CLK OSC OUT DAC X X LINE Default 0 0 0 1 1 1 1 1 1 OFF CLK OSC OUT DAC LINE X Power Clock Oscillator Outputs DAC Line input Reserved 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 1 = Off 1 = Off 1 = Off 1 = Off 1 = Off 1 = Off 3−3 Digital Audio Interface Format (Address: 0000111) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0 Default 0 0 0 0 0 0 0 0 1 MS LRSWAP LRP Master/slave mode DAC left/right swap DAC left/right phase IWL[1:0] FOR[1:0] Input bit length Data format X Reserved 0 = Slave 1 = Master 0 = Disabled 1 = Enabled 0 = Right channel on, LRCIN high 1 = Right channel on, LRCIN low 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit 11 = DSP format, frame sync followed by two data words 10 = I2S format, MSB first, left – 1 aligned 01 = MSB first, left aligned 00 = MSB first, right aligned NOTES: 1. In Master mode, the TLV320AIC23 supplies the BCLK and LRCIN. In Slave mode, BCLK and LRCIN are supplied to the TLV320AIC23. 2. In normal mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate, BCLK = MCLK. 3. In USB mode, bit BCLK = MCLK Sample Rate Control (Address: 0001000) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal Default 0 0 0 0 0 0 0 0 0 CLKOUT CLKIN SR[3:0] BOSR Clock output divider 0 = MCLK 1 = MCLK/2 Clock input divider 0 = MCLK 1 = MCLK/2 Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2) Base oversampling rate USB mode: 0 = 250 fs 1 = 272 fs Normal mode: 0 = 256 fs 1 = 384 fs Clock mode select: 0 =Normal 1 = USB Reserved USB/Normal X Digital Interface Activation (Address: 0001001) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X X X ACT Default 0 0 0 0 0 0 0 0 0 ACT X Activate interface Reserved 0 = Inactive 1 = Active Reset Register (Address: 0001111) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RES RES RES RES RES RES RES RES RES Default 0 0 0 0 0 0 0 0 0 RES Write to this register triggers reset 3.2 Analog Interface 3.2.1 Line Inputs The TLV320DAC23 has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs have independently programmable mutes. Active and passive filters for the two channels prevent high frequencies from folding back into the audio band. 3−4 The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode, the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise might be heard when reactivating the inputs. For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit shown in Figure 3-3. Where: R1 = 5 kΩ R2 = 5 kΩ C1 = 47 pF C2 = 470 nF R1 C2 CDIN + LINEIN R 2 C1 AGND Figure 3−3. Analog Line Input Circuit R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of the DAC23 inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal. 3.2.2 Line Outputs The TLV320DAC23 has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of driving line loads with 10-kΩ and 50-pF impedances. The DAC full-scale output voltage is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with the analog supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes out-of-band components. No further external filtering is required in most applications. The DAC outputs and the line inputs are summed into the line outputs. The line outputs are muted by either muting the DAC (analog) or soft muting (digital) and disabling the bypass path (see Section 3.1.3). 3.2.3 Headphone Output The TLV320DAC23 has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive 16-Ω or 32-Ω headphones. The headphone output includes a high-quality volume control and mute function. The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to the volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone output is muted or the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks. A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is enabled, the volume-control values are updated only when the input signal to the gain stage is close to the analog ground level. This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so if only dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated. The gain is independently programmable on the left and right channels. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3). 3.3 Digital Audio Interface 3.3.1 Digital Audio-Interface Modes The TLV320DAC23 supports four audio-interface modes. • • • • Right justified Left justified I2S mode DSP mode 3−5 The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified mode, which does not support 32 bits). The digital audio interface consists of clock signal BCLK, data signals DIN and and the synchronization signal LRCIN. BCLK is an output in master mode and an input in slave mode. 3.3.1.1 Right-Justified Mode In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN (see Figure 3-4). 1/fs LRCIN BCLK Left Channel DIN 0 n n−1 Right Channel 1 MSB 0 n n−1 1 0 LSB Figure 3−4. Right Justified Mode Timing 3.3.1.2 Left-Justified Mode In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN (see Figure 3-5) 1/fs LRCIN BCLK Left Channel DIN n n−1 1 MSB Right Channel 0 n n−1 1 0 n LSB Figure 3−5. Left Justified Mode Timing 3.3.1.3 I2S Mode In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN (see Figure 3-6). 1/fs LRCIN BCLK 1BCLK DIN Left Channel n MSB n−1 1 0 Right Channel n n−1 LSB Figure 3−6. I2S Mode Timing 3−6 1 0 3.3.1.4 DSP Mode The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN must be connected to the Frame Sync signal of the McBSP. A falling edge on LRCIN starts the data transfer. The left-channel data consists of the first data word, which is immediately followed by the right channel data word (see Figure 3-7). LRCIN BCLK Left Channel DIN n n−1 1 MSB Right Channel 0 n n−1 1 LSB MSB 0 LSB Figure 3−7. DSP Mode Timing 3.3.2 Audio Sampling Rates The TLV320DAC23 can operate in master or slave clock mode. In the master mode, the TLV320DAC23 clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB specification. The TLV320DAC23 can be used directly in a USB system. In the slave mode, the TLV320DAC23 clock and sample rates are controlled by using an appropriate MCLK or crystal frequency and the sample rate control register settings. The settings in the sample rate control register control the clock mode and sampling rates. Sample Rate Control (Address: 0001000) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal Default 0 0 0 0 0 0 0 0 0 CLKOUT CLKIN SR[3:0] BOSR USB/Normal X Clock output divider 0 = MCLK 1 = MCLK/2 Clock input divider 0 = MCLK 1 = MCLK/2 Sample rate control (see Sections 3.3.2.1 and 3.3.2.2) Base oversampling rate USB mode: 0 = 250 fs 1 = 272 fs Normal mode: 0 = 256 fs 1 = 384 fs Clock mode select: 0 =Normal 1 =USB Reserved The clock circuit of the DAC23 has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate generator of the DAC. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN to 1, the entire DAC is clocked with half the frequency, effectively dividing the resulting sampling rates by two. 3−7 3.3.2.1 USB-Mode Sampling Rates In the USB mode, the following DAC sampling rates are available: (MCLK = 12 MHz) SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 96 3 0 1 1 1 0 0 88.235 2 1 1 1 1 1 0 48 0 0 0 0 0 0 0 44.118 1 1 0 0 0 1 0 32 0 0 1 1 0 0 0 8.021 1 1 0 1 1 1 0 8 0 0 0 1 1 0 0 48 3 0 1 1 1 0 1 44.118 2 1 1 1 1 1 1 24 0 0 0 0 0 0 1 22.059 1 1 0 0 0 1 1 16 0 0 1 1 0 0 1 4.0105 1 1 0 1 1 1 1 4 0 0 0 1 1 0 1 (MCLK = 6 MHz) SAMPLING RATE 3−8 SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 48 3 0 1 1 1 0 0 44.118 2 1 1 1 1 1 0 24 0 0 0 0 0 0 0 22.059 1 1 0 0 0 1 0 16 0 0 1 1 0 0 0 4.0105 1 1 0 1 1 1 0 4 0 0 0 1 1 0 0 24 3 0 1 1 1 0 1 22.059 2 1 1 1 1 1 1 12 0 0 0 0 0 0 1 11.029 1 1 0 0 0 1 1 8 0 0 1 1 0 0 1 2.005 1 1 0 1 1 1 1 2 0 0 0 1 1 0 1 3.3.2.2 Normal-Mode Sampling Rates In Normal mode, the following DAC sampling rates, depending on the MCLK frequency, are available: MCLK = 12.288 MHz SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 96 2 0 1 1 1 0 0 48 1 0 0 0 0 0 0 32 1 0 1 1 0 0 0 8 1 0 0 1 1 0 0 48 2 0 1 1 1 0 1 24 1 0 0 0 0 0 1 16 1 0 1 1 0 0 1 4 1 0 0 1 1 0 1 MCLK = 11.2896 MHz SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 88.2 2 1 1 1 1 0 0 44.1 1 1 0 0 0 0 0 8.021 1 1 0 1 1 0 0 44.1 2 1 1 1 1 0 1 22.05 1 1 0 0 0 0 1 4.0105 1 1 0 1 0 0 1 MCLK = 18.432 MHz SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 96 2 0 1 1 1 1 0 48 1 0 0 0 0 1 0 32 1 0 1 1 0 1 0 8 1 0 0 1 1 1 0 48 2 0 1 1 1 1 1 24 1 0 0 0 0 1 1 16 1 0 1 1 0 1 1 4 1 0 0 1 1 1 1 MCLK = 16.9344 MHz SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS kHz FILTER TYPE SR3 SR2 SR1 SR0 BOSR CLKIN 88.2 2 1 1 1 1 1 0 44.1 1 1 0 0 0 1 0 8.021 1 1 0 1 1 1 0 44.1 2 1 1 1 1 1 1 22.05 1 1 0 0 0 1 1 4.0105 1 1 0 1 1 1 1 3−9 3.3.3 Digital Filter Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Filter Characteristics (48-kHz Sampling Rate) Passband ±0.03 dB Stopband −6 dB 0.416 fs Hz 0.5 fs Hz ±0.03 Passband ripple Stopband attenuation f > 0.584 fs −50 dB dB DAC Filter Characteristics (44.1-kHz Sampling Rate) Passband ±0.03 dB Stopband −6 dB 0.4535 fs Hz 0.5 fs Stopband attenuation f > 0.5465 fs −50 0 Filter Response − dB −2 −4 −6 −8 −10 0 0.1 0.2 0.3 0.4 0.5 Normalized Audio Sampling Frequency − Hz Figure 3−8. Digital De-Emphasis Filter Response − 44.1 kHz Sampling 3−10 Hz ±0.03 Passband ripple dB dB 0 Filter Response − dB −2 −4 −6 −8 −10 0 0.10 0.20 0.30 0.40 0.50 Normalized Audio Sampling Frequency − Hz Figure 3−9. Digital De-Emphasis Filter Response − 48 kHz Sampling Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 Normalized Audio Sampling Frequency − Hz 2.5 3 Figure 3−10. DAC Digital Filter Response 0: USB Mode Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency − Hz Figure 3−11. DAC Digital Filter Ripple 0: USB Mode 3−11 Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency − Hz Figure 3−12. DAC Digital Filter Response 1: USB Mode Only Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency − Hz Figure 3−13. DAC Digital Filter Ripple 1: USB Mode Only Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 Normalized Audio Sampling Frequency − Hz Figure 3−14. DAC Digital Filter Response 2: USB Mode and Normal Modes 3−12 3 Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency − Hz Figure 3−15. DAC Digital Filter Ripple 2: USB Mode and Normal Modes Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency − Hz Figure 3−16. DAC Digital Filter Response 3: USB Mode Only Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency − Hz Figure 3−17. DAC Digital Filter Ripple 3: USB Mode Only 3−13 3−14 Appendix A Mechanical Data GQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,10 SQ 4,90 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 NOTES: A. B. C. D. ∅ 0,05 M 0,21 0,11 0,08 4200461/C 10/00 All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA configuration Falls within JEDEC MO-225 MicroStar Junior is a trademark of Texas Instruments. A−1 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°−ā 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. A−2 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 RHD (S−PQFP−N28) PLASTIC QUAD FLATPACK 5,00 A B ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ 5,00 28 1 PIN 1 INDEX AREA 1,00 0,80 0,20 REF C SEATING PLANE 0,08 C 0,05 MAX 3,25 SQ 3,00 PIN 1 IDENTIFIER 1 0,65 28 0,45 0,435 28 0,18 0,435 4 3,00 0,18 0,50 EXPOSED THERMAL DIE PAD D 28 0,30 0,18 0,10 M C A B 4204400/A 05/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. QFN (Quad Flatpack No−Lead) Package configuration. A−3 D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected ground leads. E. Package complies to JEDEC MO-220. A−4 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Lead/Ball Finish MSL Peak Temp (3) TLV320DAC23GQE ACTIVE BGA MI CROSTA R JUNI OR GQE 80 360 TBD SNPB Level-2A-235C-4 WKS TLV320DAC23GQER ACTIVE BGA MI CROSTA R JUNI OR GQE 80 2500 TBD SNPB Level-2A-235C-4 WKS TLV320DAC23IGQE ACTIVE BGA MI CROSTA R JUNI OR GQE 80 360 TBD SNPB Level-2A-235C-4 WKS TLV320DAC23IGQER ACTIVE BGA MI CROSTA R JUNI OR GQE 80 2500 TBD SNPB Level-2A-235C-4 WKS TLV320DAC23IPW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23IPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23IPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23IRHD ACTIVE QFN RHD 28 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC23IRHDG4 ACTIVE QFN RHD 28 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC23IRHDR ACTIVE QFN RHD 28 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC23IRHDRG4 ACTIVE QFN RHD 28 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC23PW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23PWG4 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23PWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23PWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV320DAC23RHD ACTIVE QFN RHD 28 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC23RHDG4 ACTIVE QFN RHD 28 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC23RHDR ACTIVE QFN RHD 28 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC23RHDRG4 ACTIVE QFN RHD 28 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Package Type Package Drawing Pins Package Eco Plan (2) Qty (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320DAC23GQER GQE 80 SITE 60 330 12 5.3 5.3 1.5 8 12 Q1 TLV320DAC23IGQER GQE 80 SITE 60 330 12 5.3 5.3 1.5 8 12 Q1 TLV320DAC23IPWR PW 28 SITE 60 330 16 6.9 10.2 1.8 12 16 Q1 TLV320DAC23IRHDR RHD 28 SITE 60 330 12 5.3 5.3 1.5 8 12 Q2 TLV320DAC23PWR PW 28 SITE 60 330 16 6.9 10.2 1.8 12 16 Q1 TLV320DAC23RHDR RHD 28 SITE 60 330 12 5.3 5.3 1.5 8 12 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TLV320DAC23GQER GQE 80 SITE 60 342.9 336.6 20.64 TLV320DAC23IGQER GQE 80 SITE 60 342.9 336.6 20.64 TLV320DAC23IPWR PW 28 SITE 60 346.0 346.0 33.0 TLV320DAC23IRHDR RHD 28 SITE 60 342.9 336.6 20.64 TLV320DAC23PWR PW 28 SITE 60 346.0 346.0 33.0 TLV320DAC23RHDR RHD 28 SITE 60 342.9 336.6 20.64 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265