TI TLC320AD81C

TLC320AD81C
Stereo Audio Digital Equalizer DAC
Data Manual
1999
Mixed Signal Linear Products
Printed in U.S.A.
03/99
SLAS203
TLC320AD81C
Stereo Audio Digital Equalizer DAC
SLAS203
March 1999
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–1
1–2
1–2
1–3
1–3
1–4
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 I2S Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Left-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Right-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1 I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Filter Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1 Biquad Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Volume Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.1 Soft Volume Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.2 Software Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.3 Hardware Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.4 Mixer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.5 Treble Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.6 Bass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.7 De-Emphasis (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1
2–1
2–1
2–1
2–1
2–2
2–2
2–2
2–2
2–2
2–3
2–3
2–3
2–3
2–4
2–4
2–4
2–4
2–5
2–5
2–6
2–7
2–7
2–7
2–8
2–8
2–8
2–8
2–8
2–8
2–8
2–8
2–9
2–9
iii
2.11.2 Device Power On Plus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.11.3 Fast Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Absolute Maximum Ratings Over Operating Free-air Temperature Range . . . . .
3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Static Digital Specifications, TA = 0°C to 70°C, all VDD = 3.3 V + 0.3 V . . . . . . . .
3.4 DAC Performance Characteristics, TA = 25°C, AVDD_DAC = 5 V,
All Other VDD = 3.3 V, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Audio Serial Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 I2C Serial Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1
3–1
3–1
3–1
3–2
3–3
3–3
4
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
5
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
6
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1 Audio Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Appendix A Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Appendix B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
iv
List of Illustrations
Figure
Title
Page
2–1
2–2
2–3
2–4
2–5
2–6
I2S Compatible Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Left-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Right-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical I2C Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Biquad Cascade Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1
4–2
I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
2–2
2–3
2–4
2–5
2–7
2–9
6–1 Example USB Audio System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6–2 Example SPDIF Audio System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
List of Tables
Table
Title
Page
2–1 I2C Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
v
vi
1 Introduction
The TLC320AD81C performs standard audio signal processing for bass, treble, and volume, as well as
parametric equalization on a digital audio stream resulting in superior quality audio normally not available
in a low-cost solution. The TLC320AD81C contains a digital audio processor, a slave I2C interface port, and
a sigma-delta digital-to-analog converter (DAC). The audio control functions (volume, treble, and bass,) and
parametric EQ coefficients are downloaded through the I2C port to the TLC320AD81C.
The volume, treble, and bass controls may be dynamically adjusted by the user. They are updated within
the device without degradation of the output signal.
The parametric EQ consists of multiple cascaded independent biquad filters per channel. Each biquad has
five 24-bit coefficients that can be downloaded across the I2C port. The parametric EQ should not be
updated while digital audio data is being processed, because the update will possibly cause audible
artifacts.
The digital audio processor and on-chip logic use an internal system clock that is generated by the PLL from
the system clock provided to the device at the master clock input.
The TLC320AD81C supports three audio serial interface formats (I2S, left justified, and right justified) with
data word lengths of 16, 18, and 20 bits (16-bit, 32 fs mode is only supported by left justified). The sampling
frequency may be set to 44.1 kHz or 48 kHz. An I2C slave port is used to download filter coefficients and
control information to the TLC320AD81C.
Additionally, two address-select pins allow multiple TLC320AD81Cs to be cascaded on the I2C bus to
support left, right, and sub (3-channel) systems or left, right, center, rear left, rear right, and sub (6-channel)
systems.
The sigma-delta DAC has 64x oversampling. Typically, the DAC also has a 98-dB signal-to-noise ratio
(SNR) and a 94-dB dynamic range at 5 V. Hardware control for de-emphasis is supported for CD
applications at 44.1 kHz. Hardware control for soft mute is also provided.
1–1
1.1
Features
•
Stereo Sigma-Delta D/A Converter
•
98-dB Signal-to-Noise Ratio (SNR) Typical
•
94-dB Dynamic Range Typical
•
Optional 5-V Analog Power Supply for DAC Output (1 Vrms)
•
De-Emphasis Supported at 44.1 kHz for CD Applications
•
Programmable Audio Serial Port
•
Dual Input Data Channels (SDIN1 and SDIN2)
•
Single Digital Output Data Channel (SDOUT)
•
Programmable Digital Mixer
•
Programmable Multi-Band Digital Parametric EQ
•
Programmable Digital Bass and Treble Control (dynamically updateable)
•
Programmable Digital Volume Control (dynamically updateable)
•
Serial I2C Slave Port Allows Downloading of Control Data to the Device
•
Two I2C Address Pins Allow Cascading of Multiple Devices on the I2C Bus
•
Supports 2 speaker, 3 speaker†, and 6 (5.1) speaker† systems
•
Soft Mute (hardware pin control and software control)
•
Single 3.3-V Power Supply Operation
•
38-Pin TSSOP Package
•
External Analog-to-Digital Converter Supported
† Requires multiple TLC320AD81C devices
Functional Block Diagram
DM
TREB
TLC320AD81C
RESET
MCLK
CS2
I2C Slave
PLL
SDOUT
SDIN2
SDIN1
SCLK
LRCLK
Audio Serial Interface
SCL
Σ
1–2
∆Σ
Modulator
Digital
Filters
Multi Band EQ
SDA
BASS
PLL-FLT
VOL
CAP VREF
SMUTE
CS1
1.2
DAC
OUT_L
OUT_R
1.3
Terminal Assignments
SDOUT
MCLK
LRCLK
SCLK
AVSS_PLL
AVDD_PLL
PLL-FLT
RESERVED
RESERVED
RESET
NC
NC
NC
CAP_VREF
NC
OUT_R
NC
AVSS_DAC
DVSS_DAC
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
SDIN2
SDIN1
SCL
SDA
DVDD
DVSS
CS2
CS1
RESERVED
DM
NC
NC
NC
SMUTE
NC
NC
OUT_L
AVDD_DAC
DVDD_DAC
NC – No internal connection
1.4
Ordering Information
PACKAGE
TA
SMALL OUTLINE
(DBT)
0°C to 70°C
TLC320AD81CDBT
1–3
1.5
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVDD_DAC
AVDD_PLL
21
I
Analog power supply for the DAC
6
I
Analog power supply for the PLL
AVSS_DAC
AVSS_PLL
18
I
Analog ground for the DAC
5
I
Analog ground for the PLL
CAP_VREF
CS1
14
O
31
I
10 µF // 0.1 µF to AVSS_DAC (recommended values)†
I2C address bit A0; low = 0, high = 1
CS2
32
I
I2C address bit A1; low = 0, high = 1
DM
29
I
De-emphasis at 44.1 kHz; off when pin low, on when pin high (default = on
when pin not driven or biased)
DVDD
34
I
Digital power supply
DVDD_DAC
20
I
Digital power supply for the DAC
DVSS
33
I
Digital ground
DVSS_DAC
19
I
Digital ground for the DAC
LRCLK
3
I
Serial audio left/right clock sampling frequency (fs)
MCLK
2
I
Master clock
NC
11–13 15, 17,
23, 24 26–28
No connection
OUT_L
22
O
Analog output voltage left channel
OUT_R
16
O
Analog output voltage right channel
PLL–FLT
7
O
C1 = 1500 pF // R1 = 27.4 Ω + C2 = 0.068 µF (recommended values)
RESERVED
8, 9, 30
For internal use only, must be connected to GND
RESET
10
I
SCL
36
I/O
Reset, low = current state, high = reinitialized the device
Slave serial I2C clock
SCLK
4
I
SDA
35
I/O
Shift clock (bit clock)
Slave serial I2C data
SDIN1
37
I
Serial audio data input one
SDIN2
38
I
Serial audio data input two
SDOUT
1
O
Serial audio data output
SMUTE
25
I
Soft mute off when pin low; on when pin high (default = off when pin not
driven or biased)
† If only one capacitor is used, a 10-µF capacitor connected to AVSS_DAC should be used.
1–4
2 Description
2.1
Serial Audio Interface
•
Programmable audio serial port
–
•
Dual input data channels (SDIN1 and SDIN2)
–
•
2.3
2.4
16-,18-, or 20-bit resolution (see section 6.1, Audio Data)
Single output data channel (SDOUT)
–
2.2
I2S, left justified, and right justified
16-,18-, or 20-bit resolution (see section 6.1, Audio Data)
•
Accepts 32 fs or 64 fs (SCLK)†
•
I2C slave port
•
Two I2C programmable address pins (CS1 and CS2)
Audio Processing
•
Programmable multi band digital parametric EQ (updateable)
•
Programmable volume control (dynamically updateable)
•
Soft mute software controlled
•
Digital mixing of SDIN1 and SDIN2 with independent gain control
•
Programmable bass and treble tone control (dynamically updateable)
•
De-emphasis supported for CD applications at 44.1 kHz
Power Supply
•
Digital supply voltage – DVDD, DVSS of 3.3 V
•
Digital supply voltage – DVDD_DAC, DVSS_DAC of 3.3 V
•
Analog supply voltage – AVDD_PLL, AVSS_PLL of 3.3 V
•
Analog supply voltage – AVDD_DAC, AVSS_DAC of 5 V or 3.3 V
DAC
•
Stereo sigma-delta D/A converter
•
98-dB signal-to-noise ratio (SNR) typical
•
94-dB dynamic range typical
•
Soft mute hardware control pin
•
De-emphasis hardware control pin (44.1 kHz)
•
0.6 Vrms at AVDD = 3.3 V or 1 Vrms at AVDD = 5 V analog output
† 32 fs serial input mode is left justified 16 bit only
2–1
2.5
Serial Audio Interface
2.5.1
I2S Serial Format
SCLK
LRCLK = fs
SDIN
X
MSB
LSB
X
MSB
LSB
SDOUT
X
MSB
LSB
X
MSB
LSB
Left Channel
Right Channel
Figure 2–1. I2S Compatible Serial Format
2.5.2
Protocol
1.
LRCLK = Sampling frequency (fs)
2.
Left channel is transmitted when LR is low
3.
SCLK = 64 × LRCLK. SCLK is sometimes referred to as the bit clock.
4.
Serial data is sampled with the rising edge of SCLK.
5.
Serial data is transmitted on the falling edge of SCLK.
6.
LRCLK must have a 50% duty cycle
2.5.3
Implementation
1.
2.5.4
LRCLK and SCLK are both inputs
Timing
See Figure 4–1 for I2S timing.
2–2
2.6
Left-Justified Serial Format
SCLK
LRCLK = fs
SDIN
MSB
LSB
MSB
LSB
SDOUT
MSB
LSB
MSB
LSB
Left Channel
Right Channel
Figure 2–2. Left-Justified Serial Format
2.6.1
Protocol
1.
LRCLK = Sampling frequency (fs)
2.
Left channel is transmitted when LRCLK is high
3.
The SDIN1 data is justified to the leading edge of the LRCLK
4.
Serial data is sampled on the rising edge of SCLK
5.
Serial data is transmitted on the falling edge of SCLK
6.
SCLK = 32 LRCLK (32 fs SCLK is only supported for 16 bit data) or 64 LRCLK
7.
In this mode, LRCLK does not have to be a 50% duty cycle clock. The number of bits used in the
interface sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.
2.6.2
Implementation
1.
2.6.3
LRCLK and SCLK are both inputs
Timing
See Figure 4–1 for I2S timing.
2–3
2.7
Right-Justified Serial Format
SCLK
LRCLK = fs
SDIN1
X
MSB
LSB
X
MSB
LSB
SDOUT
X
MSB
LSB
X
MSB
LSB
Left Channel
Right Channel
Figure 2–3. Right-Justified Serial Format
2.7.1
Protocol
1.
LRCLK = Sampling frequency (fs)
2.
Left channel is transmitted when LRCLK is high
3.
The SDIN1 data is justified to the trailing edge of the LRCLK
4.
Serial data is sampled on the rising edge of SCLK
5.
Serial data is transmitted on the falling edge of SCLK
6.
SCLK = 64 LRCLK
7.
In this mode, LRCLK does not have to be a 50% duty cycle clock. The number of bits used in the
interface sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.
2.7.2
Implementation
1.
2.7.3
LRCLK and SCLK are both inputs
Timing
See Figure 4–1 for I2S timing.
2–4
2.8
Serial Control Interface
Control parameters for the TLC320AD81C are loaded with an I2C master interface. Information is loaded
into the registers defined in appendix A, Software Interface. The I2C bus uses two pins, SDA (data) and SCL
(clock), to communicate between integrated circuits in a system. This device may be addressed by sending
a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same pins via a
bidirectional bus using a wire-ANDed connection. A pullup resistor must be used to set the high level on the
bus. The TLC320AD81C operates in standard mode up to 100 kbps with as many devices on the bus as
desired up to the capacitance load limit of 400 pF. Additionally, the TLC320AD81C operates only in slave
mode; therefore, at least one device connected to the I2C bus with this device must operate in master mode.
2.8.1
I2C Protocol
The bus standard uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop
condition. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown
in Figure 2–4. These start and stop conditions for the I2C bus are required by standard protocol to be
generated by the master. The master must also generate the 7-bit slave address and the read/write (R/W)
bit to open communication with another device and then wait for an acknowledge condition. The slave holds
the SDA bit low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the
master begins transmitting. After each 8-bit word, an acknowledgment must be transmitted by the receiving
device. There is no limit on the number of bytes that may be transmitted between a start and stop condition.
When the last word has been transferred, the master must generate a stop condition to release the bus. A
generic data transfer sequence is shown in Figure 2–4.
7 Bit Slave Address
SDA
7 6
5
4
3
2 1
R/W A
0
8 Bit Register Address (N)
7 6
5
4
3
2 1
0
A
8 Bit Register Data For
Address (N)
7 6
5
4
3
2 1
A
0
8 Bit Register Data For
Address (N)
7 6
5
4
3
2 1
A
0
SCL
Start
Stop
Figure 2–4. Typical I2C Data Transfer Sequence
The definitions used by the I2C protocol are listed below.
Transmitter
The device that sends data
Receiver
The device that receives data
Master
The device that initiates a transfer, generates clock signals, and terminates the
transfer
Slave
The device addressed by the master
Multi-master
More than one master can attempt to control the bus at the same time without
corrupting the message.
Arbitration
Procedure to ensure the message is not corrupted when two masters attempt to
control the bus
Synchronization
Procedure to synchronize the clock signals of two or more devices
2–5
2.8.2
Operation
The 7-bit address for the TLC320AD81C is 01101XX, where X is a programmable address bit. Using the
CS1 and CS2 pins on the device, the two LSB address bits may be programmed. These four addresses are
licensed I2C addresses and will not conflict with other licensed I2C audio devices. To communicate with the
TLC320AD81C, the I2C master must use 01101XX. In addition to the 7-bit device address, subaddresses
are used to direct communication to the proper memory location within the device. A complete table of
subaddresses and control registers is provided in the appendix A, Software Interface. For example, to
change the bass setting to 10-dB gain, section 2.8.2.1, Write Cycle shows how the data is written to the I2C
port:
Table 2–1. I2C Address Byte
I2C ADDRESS
BYTE
A6–A2
CS2(A1)
CS1(A0)
R/W†
0x68
01101
0
0
0
0x6A
01101
0
1
0
0x6C
01101
1
0
0
0x6E
01101
1
1
0
† The TLC320AD81 is a write only device.
2.8.2.1
Write Cycle
When writing to a subaddress, the correct number of data bytes must follow in order to complete the write
cycle. For example, if the volume control register with subaddress 04 (hex) is written to, six bytes of data
must follow, otherwise the cycle will be incomplete. The correct number of bytes corresponding to each
subaddress is shown in appendix A, Software Interface.
Start
Slave Address
R/W
A
FUNCTION
Subaddress
Data
A
Stop
DESCRIPTION
Start
Start condition as defined in I2C
Slave Address
0110100 (CS1 = CS2 = 0)
R/W
0 (write)
A
Acknowledgement as defined in I2C (slave)
Sub-Address
00000110 (see appendix A, Software Interface)
Data
00011100 (see appendix A, Software Interface)
Stop condition as defined in I2C
Stop
A
NOTE: This table applies to serial data (SDA). Serial clock (SCL) information is not shown since the same conditions
apply as well.
2–6
2.9
Filter Processor
2.9.1
Biquad Block
The biquad block consists of multiple digital biquad filters per channel organized in a cascade structure as
shown in Figure 2–5. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each
stereo channel has independent coefficients.
Biquad 1
Biquad 2
Biquad N
Figure 2–5. Biquad Cascade Configuration
2.9.2
Filter Coefficients
The filter coefficients for the TLC320AD81C are downloaded through the I2C port and loaded into the biquad
memory space. Digital audio data coming into the device is processed by the biquad block and then
converted into analog waveforms by the DAC. Any biquad filter may be downloaded and processed by the
TLC320AD81C. The biquad structure that is used for the parametric equalization filters is as follows:
H (z )
–1
–2
+ ba0 )) ba1zz–1 )) ba2zz–2
0
1
2
NOTE: a0 is fixed at value 1 and is not downloadable
The coefficients for these filters are quantized and represented in 4.20 format – 4 bits for the integer part
and 20 bits for the fractional part. In order to transmit them over I2C, it is necessary to separate each
coefficient into three bytes. The first nibble of byte 2 is the integer part, and the second nibble of byte 2 and
bytes 1 and 0 are the fractional parts.
2–7
2.10 Volume Control Functions
The 0.5-dB steps are based on characterized data (SDOUT).
2.10.1
Soft Volume Update
The TLC320AD81C uses a soft volume update. This allows a smooth change from one volume level to the
next. The volume is represented in 4.16 format – 4 bits for the integer part and 16 bits for the fractional part.
The volume level is user adjustable (software downloadable) and has a total range of 18 dB to –70 dB plus
mute. There are 0.5-dB steps with a gain error of less than 0.12 dB over the entire range excluding mute.
Soft mute is the lowest setting (see section 2.10.2, Software Soft Mute and also see appendix A, Software
Interface).
2.10.2
Software Soft Mute
Soft mute may be implemented by inputting all 0s into the volume control register. This will cause the
TLC320AD81C to ramp the volume down to the lowest volume setting (mute) (see appendix A, Software
Interface).
2.10.3
Hardware Soft Mute
Alternatively, an external hardware control pin (smute), may be used to activated soft mute. This mutes the
output of the DAC only. This has no effect on the volume setting for the DSP in the volume control register.
2.10.4
Mixer Control
The TLC320AD81C is capable of mixing serial audio data. The mixing is controlled through two mixer control
registers. SDIN1 and SDIN2 can be mixed with a user selectable gain for each channel. The gain control
registers are represented in 4.20 format– 4 bits for the integer part and 20 bits for the fractional part. The
gain level has a total range of 18 dB to –70 dB plus mute. There are 0.5 dB steps from 18 dB to –70 dB (see
appendix A, Software Interface ). Mixer mute is implemented by inputting all 0s into the mixer 1 or mixer 2
control registers. The mixer controls are not intended to be dynamically updateable. Changes during
operation may cause audible artifacts.
2.10.5
Treble Control
The treble gain level may be adjusted within the range of 18 dB to –18 dB with 0.5 dB step resolution. The
level changes are accomplished by downloading treble codes shown in appendix A, Software Interface
section.
2.10.6
Bass Control
The bass gain level may be adjusted within the range of 18 dB to –18 dB with 0.5 dB step resolution. The
level changes are accomplished by downloading bass codes shown in appendix A, Software Interface.
2.10.7
De-Emphasis (DM)
De-emphasis is implemented in the DAC and is hardware pin controlled. De-emphasis is only valid at
44.1 kHz.
2–8
2.11 Device Initialization
2.11.1
Reset
The reset pin allows the device to be reset. That is the TLC320AD81C returns to its default state as defined
in this section. The device does not reset automatically when power is applied to the device. A reset is
required after the following condition occurs:
1. Power is applied to any of the power pins.
Or before the following conditions occur:
1. The main control register is written to.
2. Any biquad register is written to.
2.11.2
Device Power On Plus Reset
When power is applied to the TLC320AD81C, the device will power up in an unknown state. It must be reset
before the device will be in a known state. Upon reset, the EQDAC will initialize to its default state (fast load
mode). The main control register will be configured to 1XXXXXXX, where X is don’t care, as shown in
Figure 2–7. Only the fast load bit will be set to a 1 in the main control register. This puts the device into fast
load mode (see section 2.12.1, Fast Load). All random access memory (RAM) will be initialized (previous
data will be overwritten).
Bit 7
Bit 0
1
X
X
X
X
X
X
X
Figure 2–6. Main Control Register
The I2C address pins (CS1 and CS2) should be driven or biased to set the TLC320AD81C to a known I2C
address. This also ensures the I2C port will be active immediately after the reset initialization phase.
Furthermore, when implementing a three or six speaker system, the CS1 and CS2 pins must always be
driven or set to unique addresses on all devices. If the DM pin is not driven, the internal bias will pull the pin
to a high logic level and de-emphasis will be on. If the SMUTE pin is not driven, the internal bias will pull the
pin to a low logic level and mute will be off. DM is not valid for any sampling frequency except 44.1 kHz. MCLK
must be driven by a 256 fs clock. The I2C port will be powered up but will not acknowledge any I2C bus activity
until the entire device has been initialized. This typically takes 5 ms for the TLC320AD81C to fully initialize
from a powered off state or all power supply pins = 0 V.
2.11.3
Fast Load
Upon entering fast load mode, the following occurs in addition to initialization:
1.
2.
3.
4.
All of the parametric EQ will be initialized to 0 dB (all-pass).
The tone (bass/treble) will be set to 0 dB.
The mix function will set SDIN1 to 0 dB and SDIN2 to mute (no-pass).
The volume will be set to mute.
While in fast load mode, it is possible to update the parametric EQ without any audio processing delay. The
audio processor will be paused while the RAM is being updated in this mode. It is recommended that
parametric EQ be downloaded in this mode. Bass and treble may not be downloaded in this mode. Mixer1
and Mixer2 registers may be downloaded in this mode or normal mode (FL bit = 0). It is not recommended
to download the volume control register and mixer registers in this mode. Once the download is complete,
the fast load bit needs to be cleared by writing a 0 into bit 7 of the main control register. This puts the
TLC320AD81C into normal mode.
NOTE:
When writing to the FL bit in the MCR, the audio serial format is also written to at
this time. However, the device will not recognize any serial audio until it has
returned to normal mode. Entering fast load mode only by resetting the
TLC320AD81C is recommended. Once back in normal mode, treble, bass, and
volume control may be downloaded to complete device setup.
2–9
2–10
3 Specifications
3.1
Absolute Maximum Ratings Over Operating Free-air Temperature Range
(unless otherwise noted)†
Supply voltage range, AVDD_PLL, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to + 5 V
Supply voltage range, AVDD_DAC, DVDD_DAC . . . . . . . . . . . . . . . . . . . . . . –0.3 to + 7 V
Digital Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to VDD + 0.3 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to + 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3°C
Lead temperature from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97.8°C
ESD tolerance‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
‡ Human Body Model per Method 3015.2 of MIL-STD-883B.
3.2
Recommended Operating Conditions
MIN
NOM
MAX
PLL supply voltage, AVDD
TEST CONDITIONS
3
3.3
3.6
V
Digital IC supply voltage, DVDD
3
3.3
3.6
V
3
3.3
3.6
4.5
5
5.5
3
3.3
3.6
DAC supply voltage
AVDD
DVDD
PLL and digital IC supply current, IDD
DAC supply current,
current IDD
Capacitive load for each bus line CL(bus)
VDD = 3.3 V
AVDD = 3.6 V,
AVDD = 3.6 V,
SDA, SCL
mA
DVDD = 5.5 V
15
mA
DVDD = 3.6 V
7.5
0
25
mA
400
pF
70
°C
Static Digital Specifications, TA = 0°C to 70°C, all VDD = 3.3 V ± 0.3 V
PARAMETER
VIH
VIL
High-level input voltage
VOH
VOL
High-level output voltage
TEST CONDITIONS
Low-level input voltage
Low-level output voltage
Output leakage current
MIN
2
SCL, SDA
TYP
MAX
UNIT
VDD +0.3
0.8
V
VDD
0.4
V
–10
10
µA
–10
10
µA
–0.3
IO = –1 mA
IO = 4 mA
Input leakage current
Ilkg
V
20
Operating free-air temperature, TA
3.3
UNIT
2.4
V
V
3–1
3.4
DAC Performance Characteristics, TA = 25°C, AVDD_DAC = 5 V,
All Other VDD = 3.3 V, fs = 44.1 kHz (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
DAC resolution
DAC signal
signal-to-noise
to noise ratio (SNR) (see Note 2)
MAX
16
AVDD_DAC = 5 V
AVDD_DAC = 3.3 V
90
98
90
95
Dynamic range
0.005
–60 dB
dB
dB
0.01
–32
Crosstalk
0
DAC conversion latency
%
dB
90
Frequency response
UNIT
Bits
94
Total harmonic distortion (THD)
Total harmonic distortion + noise (THD + N)
TYP
dB
20
kHz
16
fs
Periods
1
Vrms
0.6
Vrms
OUTPUT DRIVER LEVELS
Full-scale output voltage (into 10 kΩ)
AVDD_DAC = 5 V
AVDD_DAC = 3.3 V
Output dc level
VDD/2
V
10
kΩ
100
pF
OUTPUT DRIVER LOADING
Minimum output load impedance
2
Maximum output load capacitance
DC ACCURACY
Transition band
20
Out of band attenuation
Interchannel gain mismatch
Output drivers
Potential divider resistance
AVDD_DAC to CAP and
CAP to AVSS_DAC
Voltage at CAP
kHz
–40
80
dB
±1%
±5%
FSR
100
120
kΩ
VDD/2
V
NOTES: 1. All measurements done with 20-kHz low-pass filter.
2. Ratio of RMS output level with 1-kHz full-scale input, to the RMS output level with all zeros into the digital
input, measured with A-weighted filter over a 20 Hz to 20 kHz bandwidth.
3–2
3.5
Audio Serial Port Timing Requirements (see Note 3)
PARAMETER
MIN
32 fs†
TYP
MAX
UNIT
MHz
f(SCLK)
tr(SCLK)
Frequency, SCLK
Rise time, SCLK (see Note 4)
5
16.3
64 fs
25
tf(SCLK)
td(SLR)
Fall time, SCLK (see Note 4)
5
16.3
25
td(SDOUT)
tsu(SDIN)
Delay time, SDOUT valid from SCLK falling
Delay time, SCLK rising to LRCLK edge (see Note 5)
Setup time, SDIN before SCLK rising edge
50
ns
ns
100
10
ns
ns
th(SDIN)
Hold time, SDIN from SCLK rising edge
100
† Valid in 16-bit left justified mode only.
NOTES: 3. Timing relative to 256 fs MCLK.
4. SCLK rising and falling are measured from 20% to 80%.
5. The rising edge of SCLK must not occur at the same time as either edge of LRCLK.
3.6
ns
ns
I2C Serial Port Timing Requirements
PARAMETER
MIN
MAX
UNIT
0
100
kHz
f(scl)
tBUF
SCL clock frequency
Bus free time between start and stop
4.7
µs
tw(low)
tw(high)
Pulse duration, SCL clock low (see Note 6)
4.7
µs
Pulse duration, SCL clock high (see Note 7)
4
µs
th(STA)
tsu(STA)
Hold time, repeated start
4
th(DAT)
tsu(DAT)
Hold time, data
4.7
0†
Setup time, data
250
tr
tf
Rise time for SDA and SCL
1000
ns
Fall time for SDA and SCL
300
ns
Setup time, repeated start
µs
20
µs
µs
ns
tsu(STO)
Setup time for stop condition
4
µs
† A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the
falling edge of SCL.
NOTES: 6. tw(low) is measured from the end of tf to the beginning of tr.
7. tw(high) is measured from the end of tr to the beginning of tf.
3–3
3–4
4 Parameter Measurement Information
tc(SCLK)
tr(SCLK)
SCLK
tf(SCLK)
td(SLR)
LRCK
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
td(SDOUT)
SDOUT
td(SLR)
tsu(SDIN)
SDIN
th(SDIN)
Figure 4–1. I2S Timing
P
SDA
P
S
Valid
tBUF
th(STA)
th(DAT)
th(STA)
tr
Change of Data
Allowed
tsu(DAT)
tf
tsu(STO)
tsu(STA)
SCL
Data Line
Stable
Figure 4–2. I2C Timing
4–1
4–2
5 Typical Characteristics
At TA = 25°C, AVDD_DAC = 5 V, DVDD_DAC = 5 V, all other VDD = 3.3 V, fs = 44.1 kHz, SYSCLK = 256fs,
unless otherwise noted.
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
0.009
Total Harmonic Distortion – dB
0.008
0.007
0.006
0.005
0 dB
0.004
0.003
0.002
0.001
0
0
50
25
TA – Temperature – °C
70
5–1
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
Total Harmonic Distortion + Noise – dB
38
36
34
–60 dB
32
30
28
26
24
22
20
0
5–2
25
50
TA – Temperature – °C
70
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
SNR – Signal-To-Noise Ratio – dB
99
98
SNR
97
96
95
94
93
92
0
50
25
TA – Temperature – °C
70
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
99
Dynamic Range – dB
98
97
96
95
Dynamic Range
94
93
92
0
50
25
TA – Temperature – °C
70
5–3
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
0.009
Total Harmonic Distortion – dB
0.008
0.007
0.006
0.005
0 dB
0.004
0.003
0.002
0.001
0
4.5
5.25
5
5.5
4.75
AVDD_DAC, DVDD_DAC – Supply Voltage – V
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
Total Harmonic Distortion + Noise – dB
38
36
34
–60 dB
32
30
28
26
24
22
20
4.5
4.75
5
5.25
5.5
AVDD_DAC, DVDD_DAC – Supply Voltage – V
5–4
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE
99
SNR – Signal-To-Noise Ratio – dB
SNR
98
97
96
95
94
93
5
5.5
4.5
4.75
5.25
AVDD_DAC, DVDD_DAC – Supply Voltage – V
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
99
Dynamic Range – dB
98
97
96
95
Dynamic Range
94
93
5.25
4.5
4.75
5
5.5
AVDD_DAC, DVDD_DAC – Supply Voltage – V
5–5
5–6
6 Application Information
Typical applications for the TLC320AD81C include:
•
Digital speakers
•
Multi media monitors with speakers
•
USB audio devices
The TLC320AD81C is designed to interface to a serial audio source and can handle up to two SDIN audio
data streams. In a multiple SDIN application as shown, latency of the ADC should be taken into account.
A controller is used to translate between USB audio and serial audio. Audio control functions are
downloaded to the TLC320AD81C through the I2C port. One option is for this to be the same controller as
the USB controller, although shown as separate controllers. The output of the device interfaces to the power
amplifiers, however, prefiltering is recommended. Voltage regulators, and bypass capacitors (not shown)
on the power supplies are recommended good practices.
USB
to
I2C
Controller
Digital Audio
I2S Data
USB Data Stream
USB
to
I2S
Controller
SCL
MCLK
LRCLK
SDIN1
SCLK
SDIN2
Power
Amplifier
SDA
Left
TLC320AD81C
Right
ADC
MIC1
MIC2
Figure 6–1. Example USB Audio System
6–1
I2C
Controller
SCL
MCLK
SPDIF
Data
SPDIF
RECEIVER
SDA
LRCLK
TLC320AD81C
SDIN1
SCLK
Left
Right
Figure 6–2. Example SPDIF Audio System
6.1
Audio Data
The TLC320AD81C handles three data lengths for received audio data. In 20-bit mode, the two least
significant bits are truncated to 18 bits before the data is processed. These 18 bits are available after
processing at the SDOUT pin. However, two more bits are truncated before the digital-to-analog (D/A)
conversion of the data, therefore 16-bit analog performance is seen at the analog output pins (Out_L and
Out_R). In 18-bit mode, all 18 bits are passed through or processed digitally. The 18 bits are available at
the SDOUT pin. Again two bits are truncated before the digital-to-analog conversion for 16-bit analog output
performance. In 16-bit mode, all 16 bits are passed through or processed both digitally and through D/A
conversion, but the 16 bits are shifted up two significant bit places before processing. Thus 18 bits are
available at SDOUT with 16 bits being data and the two least significant bits being padded zeros. The original
16 bits are passed through the D/A converter.
6–2
Appendix A
Software Interface
Table A–1. Register Map
REGISTER
ADDRESS
Reserved
0x00
MCR
0x01
Reserved
0x02
Reserved
Volume†
0x03
NO. of
BYTES
BYTE DESCRIPTION
1
C(7–0)
0x04
6
VL(23–16), VL(15–8), VL(7–0), VR(23–16), VR(15–8), VR(7–0)
Treble
0x05
1
T(7–0)
Bass
0x06
1
B(7–0)
Mixer 1‡
Mixer 2‡
0x07
3
S(23–16), S(15–8), S(7–0)
0x08
3
S(23–16), S(15–8), S(7–0)
Reserved
0x09
Left
Biquad 0
0x0A
15
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
Left
Biquad 1‡
0x0B
15
Left
Biquad 2‡
0x0C
15
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
Left
Biquad 3‡
0x0D
15
Left
Biquad 4‡
0x0E
15
Left
Biquad 5‡
0x0F
15
Reserved
0x10
Reserved
0x11
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0) A2(23–16), A2(15–8),
A2(7–0)
Reserved
0x12
† The volume value is a 4.16 coefficient. In order to transmit it over I2C, it is necessary to separate the value into three
bytes. Byte 2 is the integer part and bytes 1 and 0 are the fractional parts.
‡ The mixer gain values and biquad coefficients are 4.20 coefficients. In order to transmit them over I2C, it is necessary
to separate the value into three bytes. The first nibble of byte 2 is the integer part and the second nibble of byte 2 and
bytes 1 and 0 being the fractional parts.
A–1
Table A–1. Register Map (Continued)
ADDRESS
NO. of
BYTES
Right
Biquad 0‡
0x13
15
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
Right
Biquad 1‡
0x14
15
Right
Biquad 2‡
0x15
15
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
Right
Biquad 3‡
0x16
15
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
Right
Biquad 4‡
0x17
15
Right
Biquad 5‡
0x18
15
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
B0(23–16), B0(15–8), B0(7–0), B1(23–16), B1(15–8), B1(7–0), B2(23–16),
B2(15–8), B2(7–0), A1(23–16), A1(15–8), A1(7–0), A2(23–16), A2(15–8),
A2(7–0)
Reserved
0x19 to
0xFF
REGISTER
BYTE DESCRIPTION
† The volume value is a 4.16 coefficient. In order to transmit it over I2C, it is necessary to separate the value into three
bytes. Byte 2 is the integer part and bytes 1 and 0 are the fractional parts.
‡ The mixer gain values and biquad coefficients are 4.20 coefficients. In order to transmit them over I2C, it is necessary
to separate the value into three bytes. The first nibble of byte 2 is the integer part and the second nibble of byte 2 and
bytes 1 and 0 being the fractional parts.
A–2
Main Control Register (MCR)
The serial port for this device is flexible, making it easier to interface with many different compatible systems.
Configuration of the digital audio serial interface is set up through the main control register as shown below.
Bits F0 and F1 allow selection between three different serial data formats (right justified = 00, right
justified = 01, and I2S standard = 10). The output serial port mode set by E0 and E1 must be set to the same
value as the input serial port mode set by F0 and F1. Bits W0 and W1 allow selection between three different
word widths (16-bit word = 00, 18-bit word = 01, and 20-bit word = 10). The SC bit selects 32fs (0) or 64fs
(1) bit clock. The FL bit is primarily for use during initialization and is defined in the device initialization
section. See section 2.8 Serial Control Interface for additional information on how to address the main
control register.
Table A–2. Main Control Register (MCR)
C7
C6
C5
C4
C3
C2
C1
C0
FL
SC
E1
E0
F1
F0
W1
W0
1
x
x
x
x
x
x
x
Table A–3. Main Control Register (MCR) Description
BIT
C(7)
DESCRIPTOR
FL
FUNCTION
Fast load
VALUE
0
1 (default)
C(6)
C(5,4)
C(3,2)
C(1,0)
SC
E(1,0)
F(1,0)
W(1,0)
SCLK frequency
Output serial port mode
Input serial port mode
Serial port word length
FUNCTION
Normal operating mode
Fast load mode
0
SCLK = 32 fs
1
SCLK = 64 fs
00
Left justified
01
10
Right justified
I2S
11
Reserved
00
Left justified
01
10
Right justified
I2S
11
Reserved
00
16 bit
01
18 bit
10
20 bit
11
Reserved
A–3
Table A–4. Volume Gain Values
[The gain error is less than 0.12 dB (excluding mute)]
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
18.0
07, F1, 7B
0.0
01, 00, 00
–18.5
00, 1E, 6D
–37.0
00, 03, 9E
17.5
07, 7F, BB
–0.5
00, F1, AE
–19.0
00, 1C, B9
–37.5
00, 03, 6A
17.0
07, 14, 57
–1.0
00, E4, 29
–19.5
00, 1B, 1E
–38.0
00, 03, 39
16.5
06, AE, F6
–1.5
00, D7, 66
–20.0
00, 19, 9A
–38.5
00, 03, 0B
16.0
06, 4F, 40
–2.0
00, CB, 59
–20.5
00, 18, 2B
–39.0
00, 02, DF
15.5
05, F4, E5
–2.5
00, BF, F9
–21.0
00, 16, D1
–39.5
00, 02, B6
15.0
05, 9F, 98
–3.0
00, B5, 3C
–21.5
00, 15, 8A
–40.0
00, 02, 8F
14.5
05, 4F, 10
–3.5
00, AB, 19
–22.0
00, 14, 56
–40.5
00, 02, 6B
14.0
05, 03, 0A
–4.0
00, A1, 86
–22.5
00, 13, 33
–41.0
00, 02, 48
04, BB, 44
–4.5
00, 98, 7D
–23.0
00, 12, 20
–41.5
00, 02, 27
–5.0
00, 8F, F6
–23.5
00, 11, 1C
–42.0
00, 02, 09
–5.5
00, 87, E8
–24.0
00, 10, 27
–42.5
00, 01, EB
–6.0
00, 80, 4E
–24.5
00, 0F, 40
–43.0
00, 01, D0
–6.5
00, 79, 20
–25.0
00, 0E, 65
–43.5
00, 01, B6
–7.0
00, 72, 5A
–25.5
00, 0D, 97
–44.0
00, 01, 9E
–7.5
00, 6B, F4
–26.0
00, 0C, D5
–44.5
00, 01, 86
–8.0
00, 65, EA
–26.5
00, 0C, 1D
–45.0
00, 01, 71
–8.5
00, 60, 37
–27.0
00, 0B, 6F
–45.5
00, 01, 5C
–9.0
00, 5A, D5
–27.5
00, 0A, CC
–46.0
00, 01, 48
–9.5
00, 55, C0
–28.0
00, 0A, 31
–46.5
00, 01, 36
–10.0
00, 50, F4
–28.5
00, 09, 9F
–47.0
00, 01, 25
–10.5
00, 4C, 6D
–29.0
00, 09, 15
–47.5
00, 01, 14
–11.0
00, 48, 27
–29.5
00, 08, 93
–48.0
00, 01, 05
13.5
13.0
04, 77, 83
12.5
04, 37, 8B
12.0
03, FB, 28
11.5
03, C2, 25
11.0
03, 8C, 53
10.5
03, 59, 83
10.0
03, 29, 8B
9.5
02, FC, 42
9.0
02, D1, 82
8.5
02, A9, 25
8.0
02, 83, 0B
7.5
02, 5F, 12
7.0
02, 3D, 1D
6.5
02, 1D, 0E
6.0
01, FE, CA
5.5
01, E2, 37
5.0
–11.5
00, 44, 1D
–30.0
00, 08, 18
–48.5
00, 00, F6
–12.0
00, 40, 4E
–30.5
00, 07, A5
–49.0
00, 00, E9
–12.5
00, 3C, B5
–31.0
00, 07, 37
–49.5
00, 00, DC
–13.0
00, 39, 50
–31.5
00, 06, D0
–50.0
00, 00, CF
01, C7, 3D
–13.5
00, 36, 1B
–32.0
00, 06, 6E
–50.5
00, 00, C4
4.5
01, AD, C6
–14.0
00, 33, 14
–32.5
00, 06, 12
–51.0
00, 00, B9
4.0
01, 95, BC
–14.5
00, 30, 39
–33.0
00, 05, BB
–51.5
00, 00, AE
3.5
01, 7F, 09
–15.0
00, 2D, 86
–33.5
00, 05, 69
–52.0
00, 00, A5
3.0
01, 69, 9C
–15.5
00, 2A, FA
–34.0
00, 05, 1C
–52.5
00, 00, 9B
2.5
01, 55, 62
–16.0
00, 28, 93
–34.5
00, 04, D2
–53.0
00, 00, 93
2.0
01, 42, 49
–16.5
00, 26, 4E
–35.0
00, 04, 8D
–53.5
00, 00, 8B
1.5
01, 30, 42
–17.0
00, 24, 29
–35.5
00, 04, 4C
–54.0
00, 00, 83
1.0
01, 1F, 3D
–17.5
00, 22, 23
–36.0
00, 04, 0F
–54.5
00, 00, 7B
0.5
01, 0F, 2B
–18.0
00, 20, 3A
–36.5
00, 03, D5
–55.0
00, 00, 75
A–4
Table A–4. Volume Gain Values
[The gain error is less than 0.12 dB (excuding mute)] (Continued)
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
GAIN
(dB)
VOLUME
V(23–16),
V(15–8),
V(7–0)
–55.5
00, 00, 6E
–59.5
00, 00, 45
–63.5
00, 00, 2C
–67.5
00, 00, 1C
–56.0
00, 00, 68
–60.0
00, 00, 42
–64.0
00, 00, 29
–68.0
00, 00, 1A
–56.5
00, 00, 62
–60.5
00, 00, 3E
–64.5
00, 00, 27
–68.5
00, 00, 19
–57.0
00, 00, 5D
–61.0
00, 00, 3A
–65.0
00, 00, 25
–69.0
00, 00, 17
–57.5
00, 00, 57
–61.5
00, 00, 37
–65.5
00, 00, 23
–69.5
00, 00, 16
–58.0
00, 00, 53
–62.0
00, 00, 34
–66.0
00, 00, 21
–70.0
00, 00, 15
–58.5
00, 00, 4E
–62.5
00, 00, 31
–66.5
00, 00, 1F
Mute
00, 00, 00
–59.0
00, 00, 4A
–63.0
00, 00, 2E
–67.0
00, 00, 1D
Table A–5. Treble Control Register
(Both left and right channel will be given the same treble gain setting)
Gain
(dB)
T(7–0)
(hex)
Gain
(dB)
T(7–0)
(hex)
Gain
(dB)
T(7–0)
(hex)
Gain
(dB)
T(7–0)
(hex)
18.0
0x01
8.5
0x57
–0.5
0x73
–10.0
0x86
17.5
0x09
8.0
0x5A
–1.0
0x74
–10.5
0x87
17.0
0x10
7.5
0x5C
–1.5
0x75
–11.0
0x88
16.5
0x16
0x5E
–2.0
0x76
–11.5
0x89
16.0
0x1C
6.5
0x60
–2.5
0x77
–12.0
0x8A
15.5
0x22
6.0
0x62
–3.0
0x78
–12.5
0x8B
15.0
0x28
–3.5
0x79
–13.0
0x8C
14.5
0x2D
–4.0
0x7A
–13.5
0x8D
14.0
0x32
–4.5
0x7B
–14.0
0x8E
13.5
0x36
–5.0
0x7C
–14.5
0x8F
–5.5
0x7D
–15.0
0x90
–6.0
0x7E
–15.5
0x91
–6.5
0x7F
–16.0
0x92
13.0
0x3A
12.5
0x3E
12.0
0x42
7.0
5.5
0x63
5.0
0x65
4.5
0x66
4.0
0x68
3.5
0x69
3.0
0x6B
0x6C
11.5
0x45
2.5
–7.0
0x80
–16.5
0x93
11.0
0x49
2.0
0x6D
–7.5
0x81
–17.0
0x94
10.5
0x4C
1.5
0x6E
–8.0
0x82
–17.5
0x95
10.0
0x4F
1.0
0x70
–8.5
0x83
–18.0
0x96
9.5
0x52
0.5
0x71
–9.0
0x84
9.0
0x55
0.0
0x72
–9.5
0x85
A–5
Table A–6. Bass Control Register
(Both left and right channel will be given the same bass setting)
Gain
(dB)
B(7–0)
(hex)
Gain
(dB)
B(7–0)
(hex)
Gain
(dB)
B(7–0)
(hex)
Gain
(dB)
B(7–0)
(hex)
18.0
0x01
8.5
0x23
–0.5
17.5
0x03
8.0
0x25
–1.0
0x40
–9.5
0x5F
0x42
–10.0
17.0
0x06
0x61
7.5
0x26
16.5
0x08
7.0
0x28
–1.5
0x44
–10.5
0x64
–2.0
0x46
–11.0
16.0
0x0A
0x66
6.5
15.5
0x0B
0x29
–2.5
0x49
–11.5
0x69
15.0
0x0D
6.0
0x2B
–3.0
0x4B
–12.0
0x6B
5.5
0x2C
–3.5
0x4D
–12.5
0x6D
14.5
0x0F
14.0
0x10
5.0
0x2E
–4.0
0x4F
–13.0
0x6E
4.5
0x30
–4.5
0x51
–13.5
13.5
0x12
0x70
13.0
0x13
4.0
0x31
–5.0
0x53
–14.0
0x72
12.5
0x14
3.5
0x33
–5.5
0x54
–14.5
0x74
3.0
0x35
–6.0
0x55
–15.0
0x76
12.0
0x16
11.5
0x17
2.5
0x36
–6.5
0x56
–15.5
0x78
11.0
0x18
2.0
0x38
–7.0
0x58
–16.0
0x7A
10.5
0x19
1.5
0x39
–7.5
0x59
–16.5
0x7D
10.0
0x1C
1.0
0x3B
–8.0
0x5A
–17.0
0x7F
9.5
0x1F
0.5
0x3C
–8.5
0x5C
–17.5
0x82
9.0
0x21
0.0
0x3E
–9.0
0x5D
–18.0
0x86
Table A–7. Mixer1 and Mixer2 Gain Values
[The gain error is less than 0.12 dB (excluding mute)]
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
18.0
7F, 17, AF
11.0
38, C5, 28
4.0
19, 5B, B8
–3.0
0B, 53, BE
17.5
77, FB, AA
10.5
35, 98, 2F
3.5
17, F0, 94
–3.5
0A, B1, 89
17.0
71, 45, 75
10.0
32, 98, B0
3.0
16, 99, C0
–4.0
0A, 18, 66
16.5
6A, EF, 5D
9.5
2F, C4, 20
2.5
15, 56, 1A
–4.5
09, 87, D5
16.0
64, F4, 03
9.0
2D, 18, 18
2.0
14, 24, 8E
–5.0
08, FF, 59
15.5
5F, 4E, 52
8.5
2A, 92, 54
1.5
13, 04, 1A
–5.5
08, 7E, 80
15.0
59, F9, 80
8.0
28, 30, AF
1.0
11, F3, C9
–6.0
08, 04, DC
14.5
54, F1, 06
7.5
25, F1, 25
0.5
10, F2, B4
–6.5
07, 92, 07
14.0
50, 30, A1
7.0
23, D1, CD
0.0
10, 00, 00
–7.0
07, 25, 9D
13.5
4B, B4, 46
6.5
21, D0, D9
–0.5
0F, 1A, DF
–7.5
06, BF, 44
13.0
47, 78, 28
6.0
1F, EC, 98
–1.0
0E, 42, 90
–8.0
06, 5E, A5
12.5
43, 78, B0
5.5
1E, 23, 6D
–1.5
0D, 76, 5A
–8.5
06, 03, 6E
12.0
3F, B2, 78
5.0
1C, 73, D5
–2.0
0C, B5, 91
–9.0
05, AD, 50
11.5
3C, 22, 4C
4.5
1A, DC, 61
–2.5
0B, FF, 91
–9.5
05, 5C, 04
A–6
Table A–7. Example Mixer1 and Mixer2 Gain Values
[The gain error is less than 0.12 dB (excluding mute)] (Continued)
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
Gain
(dB)
Gain
S(23–16),
S(15–8),
S(7–0)
–10.0
05, 0F, 44
–25.0
00, E6, 55
–40.0
00, 28, F5
–55.5
00, 06, E0
–10.5
04, C6, D0
–25.5
00, D9, 73
–40.5
00, 26, AB
–56.0
00, 06, 7D
–11.0
04, 82, 68
–26.0
00, CD, 49
–41.0
00, 24, 81
–56.5
00, 06, 20
00, 22, 76
–57.0
00, 05, C9
–11.5
04, 41, D5
–26.5
00, C1, CD
–41.5
–12.0
04, 04, DE
–27.0
00, B6, F6
–42.0
00, 20, 89
–57.5
00, 05, 76
00, 1E, B7
–58.0
00, 05, 28
–12.5
03, CB, 50
–27.5
00, AC, BA
–42.5
–13.0
03, 94, FA
–28.0
00, A3, 10
–43.0
00, 1C, FF
–58.5
00, 04, DE
00, 99, F1
–43.5
00, 1B, 60
–59.0
00, 04, 98
–44.0
00, 19, D8
–59.5
00, 04, 56
–44.5
00, 18, 65
–60.0
00, 04, 18
–45.0
00, 17, 08
–60.5
00, 03, DD
–45.5
00, 15, BE
–61.0
00, 03, A6
–46.0
00, 14, 87
–61.5
00, 03, 72
–46.5
00, 13, 61
–62.0
00, 03, 40
–47.0
00, 12, 4B
–62.5
00, 03, 12
–47.5
00, 11, 45
–63.0
00, 02, E6
–48.0
00, 10, 4E
–63.5
00, 02, BC
–48.5
00, 0F, 64
–64.0
00, 02, 95
–49.0
00, 0E, 88
–64.5
00, 02, 70
–49.5
00, 0D, B8
–65.0
00, 02, 4D
–50.0
00, 0C, F3
–65.5
00, 02, 2C
–50.5
00, 0C, 3A
–66.0
00, 02, 0D
–13.5
03, 61, AF
–28.5
–14.0
03, 31, 42
–29.0
00, 91, 54
–14.5
03, 03, 8A
–29.5
00, 89, 33
–15.0
02, D8, 62
–30.0
00, 81, 86
–15.5
02, AF, A3
–30.5
00, 7A, 48
–16.0
02, 89, 2C
–31.0
00, 73, 70
–16.5
02, 64, DB
–31.5
00, 6C, FB
–17.0
02, 42, 93
–32.0
00, 66, E3
–17.5
02, 22, 35
–32.5
00, 61, 21
–18.0
02, 03, A7
–33.0
00, 5B, B2
–18.5
01, E6, CF
–33.5
00, 56, 91
–19.0
01, CB, 94
–34.0
00, 51, B9
–19.5
01, B1, DE
–34.5
00, 4D, 27
–20.0
01, 99, 99
–35.0
00, 48, D6
–20.5
01, 82, AF
–35.5
00, 44, C3
–51.0
00, 0B, 8B
–66.5
00, 01, F0
–21.0
01, 6D, 0E
–36.0
00, 40, EA
–51.5
00, 0A, E5
–67.0
00, 01, D4
–21.5
01, 58, A2
–36.5
00, 3D, 49
–52.0
00, 0A, 49
–67.5
00, 01, BA
–22.0
01, 45, 5B
–37.0
00, 39, DB
–52.5
00, 09, B6
–68.0
00, 01, A1
–22.5
01, 33, 28
–37.5
00, 36, 9E
–53.0
00, 09, 2B
–68.5
00, 01, 8A
–23.0
01, 21, F9
–38.0
00, 33, 90
–53.5
00, 08, A8
–69.0
00, 01, 74
–23.5
01, 11, C0
–38.5
00, 30, AE
–54.0
00, 08, 2C
–69.5
00, 01, 5F
–24.0
01, 02, 70
–39.0
00, 2D, F5
–54.5
00, 07, B7
–70.0
00, 01, 4B
–24.5
00, F3, FB
–39.5
00, 2B, 63
–55.0
00, 07, 48
Mute
00, 00, 00
A–7
A–8
Appendix B
Mechanical Data
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PIN SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°– 8°
0,75
0,50
A
Seating Plane
1,20 MAX
0,15
0,05
0,10
PINS **
DIM
28
30
38
44
50
A MAX
7,90
7,90
9,80
11,10
12,60
A MIN
7,70
7,70
9,60
10,90
12,40
4073252/C 10/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15.
Falls within JEDEC MO-153
B–1
B–2
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated