TI TPA6203A1ZQVR

TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
1.25 W Into 8 Ω From a 5-V Supply at
THD = 1% (Typ)
Low Supply Current: 1.7 mA typ
Shutdown Control <1 µA
Only Five External Components
– Improved PSRR (90 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
– Fully Differential Design Reduces RF
Rectification
– Improved CMRR Eliminates Two Input
Coupling Capacitors
– C(BYPASS) Is Optional Due to Fully Differential
Design and High PSRR
– ZQV (Pb - free) and GQV Options
Avaliable in a 2 mm x 2 mm MicroStar
Junior™ BGA Package
– ZQV (Pb - free) and GQV Options
Designed for Wireless or Cellular Handsets
and PDAs
DESCRIPTION
The TPA6203A1 is a 1.25-W mono fully differential
amplifier designed to drive a speaker with at least 8-Ω
impedance while consuming less than 37 mm2 total
printed-circuit board (PCB) area in most applications.
This device operates from 2.5 V to 5.5 V, drawing only
1.7 mA of quiescent supply current. The TPA6203A1 is
available in the space-saving 2 mm x 2 mm MicroStar
Junior™ BGA package.
Features like 85-dB PSRR from 90 Hz to 5 kHz,
improved RF-rectification immunity, and small PCB
area makes the TPA6203A1 ideal for wireless
handsets. A fast start-up time of 4 µs with minimal pop
makes the TPA6203A1 ideal for PDA applications.
APPLICATION CIRCUIT
Actual Solution Size
VDD A3
RF
To Battery
RF
RI
C3 IN-
+ RI
C2 IN+
In From
DAC
Cs
_
VO+
RF
SHUTDOWN
VO+ B3
A1
CS
(1)C
B
5,25 mm
GND B2
B1
C1
RI
Bias
Circuitry
RI
(1)C
(BYPASS)
(1)
C(BYPASS) is optional
RF
6,9 mm
MicroStar Junior is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2002 – 2003, Texas Instruments Incorporated
TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Supply voltage, VDD
-0.3 V to 6.0 V
Input voltage, VI
-0.3 V to VDD +0.3V
Continuous total power dissipation
See Dissipation Rating Table
Operating free-air temperature, TA
-40°C to 85°C
Junction temperature, TJ
-40°C to 125°C
Storage temperature, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
(1)
ZQV
260°C
GQV
235°C
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VDD
TYP
MAX
2.5
High-level input voltage, VIH
SHUTDOWN
Low-level input voltage, VIL
SHUTDOWN
Common-mode input voltage, VIC
VDD = 2.5 V, 5.5 V, CMRR ≤ -60 dB
5.5
2
V
V
0.8
Operating free-air temperature, TA
UNIT
V
0.5
VDD-0.8
V
-40
85
°C
DISSIPATION RATINGS
PACKAGE
TA≤ 25°C
POWER RATING
DERATING FACTOR
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
GQV, ZQV
885 mW
8.8 mW/°C
486 mW
354 mW
ORDERING INFORMATION
PACKAGED DEVICES (1) (2)
(1)
(2)
2
MICROSTAR JUNIOR™
(GQV)
MICROSTAR JUNIOR™
(ZQV)
Device
TPA6203A1GQVR
TPA6203A1ZQVR
Symbolization
AADI
AAEI
The GQV is the standard MicroStar Junior package. The ZQV is a lead-free option and is qualified for 260° lead-free assembly.
The GQV and ZQV packages are only available taped and reeled. The suffix R designates taped and reeled parts.
TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
ELECTRICAL CHARACTERISTICS
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
|VOO|
Output offset voltage (measured
differentially)
VI = 0 V, VDD = 2.5 V to 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
CMRR
Common-mode rejection ratio
VOL
Low-level output voltage
MIN
TYP MAX
UNIT
9
mV
-90
-70
dB
VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD-0.8
-70
-65
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
-62
-55
VDD = 5.5 V
0.30
0.46
VDD = 3.6 V
0.22
RL = 8 Ω, VIN+ = VDD, VIN- = 0 V or VIN+
= 0 V, VIN- = VDD
VDD = 2.5 V
VDD = 5.5 V
0.19
4.8
dB
V
0.26
5.12
VOH
High-level output voltage
RL = 8 Ω, VIN+ = VDD, VIN- = 0 V or VIN+
= 0 V, VIN- = VDD
|IIH|
High-level input current
VDD = 5.5 V, VI = 5.8 V
1.2
µA
|IIL|
Low-level input current
VDD = 5.5 V, VI = -0.3 V
1.2
µA
IDD
Supply current
VDD = 2.5 V to 5.5 V, no load, SHUTDOWN = 2 V
1.7
2
mA
IDD(SD)
Supply current in shutdown mode SHUTDOWN = 0.8 V, VDD = 2.5 V to 5.5 V, no load
0.01
0.9
µA
VDD = 3.6 V
VDD = 2.5 V
3.28
2.1
V
2.24
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 1 V/V, RL = 8 Ω
PARAMETER
PO
Output power
TEST CONDITIONS
THD + N = 1%, f = 1 kHz
kSVR
SNR
Total harmonic distortion
plus noise
Supply ripple rejection
ratio
Signal-to-noise ratio
VDD = 3.6 V
0.63
VDD = 5 V, PO = 1 W, f = 1 kHz
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz
0.07
%
VDD = 2.5 V, PO = 200 mW, f = 1 kHz
0.08
%
C(BYPASS) = 0.47 µF, VDD = 3.6 V to
f = 217 Hz to 2 kHz,
5.5 V,
VRIPPLE = 200 mVPP
Inputs ac-grounded with CI = 2 µF
-87
C(BYPASS) = 0.47 µF, VDD = 2.5 V to
f = 217 Hz to 2 kHz,
3.6 V,
VRIPPLE = 200 mVPP
Inputs ac-grounded with CI = 2 µF
-82
C(BYPASS) = 0.47 µF, VDD = 2.5 V to
f = 40 Hz to 20 kHz,
5.5 V,
VRIPPLE = 200 mVPP
Inputs ac-grounded with CI = 2 µF
≤-74
VDD = 5 V, PO= 1 W
Output voltage noise
f = 20 Hz to 20 kHz
CMRR
Common-mode rejection
ratio
VDD = 2.5 V to 5.5 V,
VICM = 200 mVPP
ZI
Input impedance
f = 20 Hz to 20 kHz, RF = RI = 20 kΩ
MAX
UNIT
W
0.3
0.06
%
Vn
Shutdown attenuation
TYP
1.25
VDD = 2.5 V
THD+N
MIN
VDD = 5 V
104
No weighting
17
A weighting
13
f = 20 Hz to 1 kHz
≤-85
f = 20 Hz to 20 kHz
≤-74
dB
dB
µVRMS
dB
2
MΩ
-80
dB
3
TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
MicroStar Junior (GQV or ZQV) Package
(TOP VIEW)
VO–
SHUTDOWN
BYPASS
A
B
C
GND
1 2 3
VDD
VO+
IN–
IN+
(SIDE VIEW)
Terminal Functions
TERMINAL
I/O
DESCRIPTION
C1
I
Mid-supply voltage. Connect a capacitor to GND for BYPASS voltage filtering. Bypass capacitor is optional.
GND
B2
I
High-current ground
IN-
C3
I
Negative differential input
IN+
C2
I
Positive differential input
SHUTDOWN
B1
I
Shutdown terminal. Pull this pin low (≤0.8 V) to place the device in shutdown and pull it high (≥2 V) for
active mode.
VDD
A3
I
Supply voltage terminal
VO+
B3
O
Positive BTL output
VO-
A1
O
Negative BTL output
NAME
NO.
BYPASS
4
TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Supply voltage
1
vs Load resistance
2, 3
4, 5
PO
Output power
PD
Power dissipation
vs Output power
Maximum ambient temperature
vs Power dissipation
vs Output power
Total harmonic distortion + noise
vs Frequency
vs Common-mode input voltage
CMRR
IDD
6
7, 8
9, 10, 11, 12
13
Supply voltage rejection ratio
vs Frequency
Supply voltage rejection ratio
vs Common-mode input voltage
18
GSM Power supply rejection
vs Time
19
GSM Power supply rejection
vs Frequency
20
vs Frequency
21
Common-mode rejection ratio
14, 15, 16, 17
vs Common-mode input voltage
22
Closed loop gain/phase
vs Frequency
23
Open loop gain/phase
vs Frequency
24
vs Supply voltage
25
vs Shutdown voltage
26
vs Bypass capacitor
27
Supply current
Start-up time
5
TPA6203A1
www.ti.com
SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
1.8
THD+N = 10%
1
0.8
0.6
THD+N = 1%
0.4
0.4
0
0
3.5
4
4.5
5
VDD = 2.5 V
0.6
0.2
3
VDD = 3.6 V
0.8
0.2
2.5
13
18
0.25
0.2
0.15
16 Ω
0.1
0.05
8Ω
0.5
0.4
0.3
16 Ω
0.2
0.1
0.8
0.2
Figure 4.
60
50
40
30
20
10
0.4
0.6
0.8
1
1.2
0
1.4
3.6 V
0.5
5V
0.2
0.1
RL = 8 Ω, f = 1 kHz
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
1
2 3
5
2
RL = 16 Ω
f = 1 kHz
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
1
0.5
0.2
2.5 V
5V
3.6 V
0.1
0.05
0.02
0.01
10 m
100 m
PO - Output Power - W
PO - Output Power - W
Figure 7.
Figure 8.
0.3
0.4
0.5
0.6
0.7
0.8
TOTAL HARMONIC DISTORTION
+ NOISE
vs
FREQUENCY
1
2
THD+N - Total Harmonic Distortion + Noise - %
2.5 V
10
0.2
Figure 6.
TOTAL HARMONIC DISTORTION
+ NOISE
vs
OUTPUT POWER
THD+N - Total Harmonic Distortion + Noise - %
5
0.1
PD - Power Dissipation - W
Figure 5.
10
100 m
70
PO - Output Power - W
PO - Output Power - W
0.01
10 m
80
0
0
TOTAL HARMONIC DISTORTION
+ NOISE
vs
OUTPUT POWER
32
MAXIMUM AMBIENT
TEMPERATURE
vs
POWER DISSIPATION
0
0.6
28
Figure 3.
Maximum Ambient Temperature - ° C
PD - Power Dissipation - W
PD - Power Dissipation - W
8Ω
1
13
18
23
RL - Load Resistance - Ω
90
0.6
0
THD+N - Total Harmonic Distortion + Noise - %
8
32
28
VDD = 5 V
0.35
6
23
0.7
2
0.4
POWER DISSIPATION
vs
OUTPUT POWER
VDD = 3.6 V
0.4
VDD = 2.5 V
0.6
Figure 2.
0.4
0.2
0.8
RL - Load Resistance - Ω
POWER DISSIPATION
vs
OUTPUT POWER
0
VDD = 3.6 V
1
0
8
Figure 1.
0.3
VDD = 5 V
1.2
0.2
VDD - Supply Voltage - V
0.02
1.4
VDD = 5 V
1
f = 1 kHz
THD+N = 10%
Gain = 1 V/V
1.6
PO - Output Power - W
1.2
f = 1 kHz
THD+N = 1%
Gain = 1 V/V
1.2
PO - Output Power - W
1.4
PO - Output Power - W
1.8
1.4
RL = 8 Ω
f = 1 kHz
Gain = 1 V/V
1.6
0.05
OUTPUT POWER
vs
LOAD RESISTANCE
10
5
0.5
VDD = 5 V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
0.2
250 mW
2
1
50 mW
0.1
0.05
0.02
1W
0.01
0.005
0.002
0.001
20
100 200
1k 2k
f - Frequency - Hz
Figure 9.
10 k 20 k
TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS (continued)
0.5
0.2
0.1
125 mW
0.05
0.02
500 mW
0.01
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
5 k 10 k 20 k
VDD = 2.5 V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
2
1
0.5
0.2
0.1
75 mW
0.05
0.02
200 mW
0.01
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
Figure 10.
1
VDD = 2.5 V
0.10
VDD = 3.6 V
- Supply Voltage Rejection Ratio - dB
SVR
f = 1 kHz
PO = 200 mW
0.01
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0.47 µF
Vp-p = 200 mV
Inputs ac-Grounded
Gain = 1 V/V
-20
-30
-40
-50
-60
VDD =2. 5 V
-70
VDD = 5 V
-80
-90
VDD = 3.6 V
-100
20
0.5
1
1.5
2
2.5
3
3.5
VIC - Common Mode Input Voltage - V
50 100 200
-40
-50
VDD =2. 5 V
VDD = 5 V
VDD = 3.6 V
-80
-90
-100
20
50 100 200
500 1 k 2 k
5 k 10 k 20 k
500 1 k 2 k
125 mW
0.1
0.02
0.01
250 mW
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
0
-30
-20
-30
-40
-50
-80
VDD = 3.6 V
-90
-100
20
50 100 200
500 1 k 2 k
Figure 15.
C(Bypass) = 0
C(Bypass) = 1 µF
-70
C(Bypass) = 0.1 µF
-80
-90
-100
20
VDD = 5 V
-70
Figure 14.
C(Bypass) = 0.47 µF
-60
VDD =2. 5 V
-60
f - Frequency - Hz
-40
-50
Gain = 5 V/V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0.47 µF
Vp-p = 200 mV
Inputs ac-Grounded
-10
5 k 10 k 20 k
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Inputs ac-Grounded
Gain = 1 V/V
-20
50 100 200
500 1 k 2 k
f - Frequency - Hz
f - Frequency - Hz
Figure 16.
Figure 17.
5 k 10 k 20 k
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
f - Frequency - Hz
0
-10
25 mW
0.05
5 k 10 k 20 k
5 k 10 k 20 k
SUPPLY VOLTAGE REJECTION
RATIO
vs
COMMON MODE INPUT VOLTAGE
SVR
CI = 2 µF
RL = 8 Ω
Inputs Floating
Gain = 1 V/V
-70
0.2
k
- Supply Voltage Rejection Ratio - dB
SVR
0
-60
0.5
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
k
k
- Supply Voltage Rejection Ratio - dB
SVR
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
-30
1
Figure 12.
0
-10
Figure 13.
-20
VDD = 3.6 V
CI = 2 µF
RL = 16 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
2
SUPPLY VOLTAGE REJECTION
RATIO
vs
FREQUENCY
k
THD+N - Total Harmonic Distortion + Noise - %
10
-10
5 k 10 k 20 k
10
5
Figure 11.
TOTAL HARMONIC DISTORTION
+ NOISE
vs
COMMON MODE INPUT VOLTAGE
0
15 mW
THD+N - Total Harmonic Distortion + Noise - %
1
10
5
- Supply Voltage Rejection Ratio - dB
SVR
2
25 mW
k
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
C(Bypass) = 0 to 1 µF
Gain = 1 V/V
TOTAL HARMONIC DISTORTION
+ NOISE
vs
FREQUENCY
- Supply Voltage Rejection Ratio - dB
10
5
TOTAL HARMONIC DISTORTION
+ NOISE
vs
FREQUENCY
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION
+ NOISE
vs
FREQUENCY
-10
f = 217 Hz
C(Bypass) = 0.47 µF
RL = 8 Ω
Gain = 1 V/V
-20
-30
VDD = 2.5 V
-40
VDD = 3.6 V
-50
-60
-70
-80
VDD = 5 V
-90
0
1
2
3
4
VIC - Common Mode Input Voltage - V
5
Figure 18.
7
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS (continued)
COMMON MODE REJECTION
RATIO
vs
FREQUENCY
0
C1
Frequency
217.41 Hz
-50
C1 - Duty
20 %
-100
C1 Pk-Pk
504 mV
VO
Ch1 100 mV/div
Ch4 10 mV/div
t - Time - ms
2 ms/div
0
-150
VDD Shown in Figure 19
CI = 2 µF,
C(Bypass) = 0.47 µF,
Inputs ac-Grounded
Gain = 1V/V
-50
-100
-150
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
VDD = 5 V
20
-20
-30
-60
-70
-40
-100
-80
-50
-60
VDD = 3.6 V
2.5 3
3.5 4
VDD = 3.6 V
RL = 8 Ω
Gain = 1 V/V
50 100 200 500 1 k 2 k
10
4.5 5
100
1k
200
VDD = 3.6 V
RL = 8 Ω
100
Gain
50
50
0
0
-50
-50
Phase
-100
-100
-180
-150
-150
-220
10 M
-200
10 k
100 k 1 M
100
1.6
1.6
1.4
1.4
10 k
100 k
1M
-200
10 M
Figure 24.
START-UP TIME(1)
vs
BYPASS CAPACITOR
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
1.8
1k
f - Frequency - Hz
Figure 23.
1.8
150
100
f - Frequency - Hz
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
5 k 10 k 20 k
-140
-70
Figure 22.
6
1.2
1
0.8
0.6
0.4
VDD = 2.5 V
1.2
1.0
VDD = 3.6 V
0.8
VDD = 5 V
0.6
Start-Up Time - ms
5
I DD - Supply Current - mA
I DD - Supply Current - mA
60
-10
VIC - Common Mode Input Voltage - V
0.4
0
0 0.5 1
1.5 2 2.5 3 3.5
4 4.5 5
5.5
4
3
2
1
0.2
0.2
8
20
150
100
Gain
-20
-60
1.5 2
-90
-100
140
Gain - dB
VDD = 2.5 V
0.5 1
-80
200
Phase - Degrees
Gain - dB
CMRR - Common Mode Rejection Ratio - dB
20
0
0
-70
OPEN LOOP GAIN/PHASE
vs
FREQUENCY
180
10
-90
-60
Figure 21.
220
Phase
30
-30
-100
-50
f - Frequency - Hz
40
RL = 8 Ω
Gain = 1 V/V
-50
-40
CLOSED LOOP GAIN/PHASE
vs
FREQUENCY
0
-40
-30
Figure 20.
COMMON MODE REJECTION
RATIO
vs
COMMON MODE INPUT VOLTAGE
-20
VDD = 2.5 V to 5 V
VIC = 200 mVp-p
RL = 8 Ω
Gain = 1 V/V
-20
f - Frequency - Hz
Figure 19.
-10
0
-10
Phase - Degrees
C1 High
3.598 V
VO - Output Voltage - dBV
Voltage - V
VDD
V DD - Supply Voltage - dBV
GSM POWER SUPPLY
REJECTION
vs
FREQUENCY
CMRR - Common Mode Rejection Ratio - dB
GSM POWER SUPPLY
REJECTION
vs
TIME
0
0
0
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
VDD - Supply Voltage - V
Voltage on SHUTDOWN Terminal - V
Figure 25.
Figure 26.
(1)
0.5
1
1.5
C(Bypass) - Bypass Capacitor - µF
2
Start-Up time is the time it takes (from a
low-to-high transition on SHUTDOWN) for the
gain of the amplifier to reach -3 dB of the final
gain.
Figure 27.
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
APPLICATION INFORMATION
shift in the mid-supply affects both positive and
negative channels equally and cancels at the
differential output. However, removing the bypass
capacitor slightly worsens power supply rejection
ratio (kSVR), but a slight decrease of kSVR may be
acceptable when an additional component can be
eliminated (see Figure 17).
Better RF-immunity: GSM handsets save power
by turning on and shutting off the RF transmitter
at a rate of 217 Hz. The transmitted signal is
picked-up on input and output traces. The fully
differential amplifier cancels the signal much
better than the typical audio amplifier.
FULLY DIFFERENTIAL AMPLIFIER
The TPA6203A1 is a fully differential amplifier with
differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a
common- mode amplifier. The differential amplifier
ensures that the amplifier outputs a differential
voltage that is equal to the differential input times the
gain. The common-mode feedback ensures that the
common-mode voltage at the output is biased around
VDD/2 regardless of the common- mode voltage at the
input.
•
Advantages of Fully Differential Amplifiers
• Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the
TPA6203A1, allows the inputs to be biased at
voltage other than mid-supply. For example, if a
DAC has mid-supply lower than the mid-supply of
the TPA6203A1, the common-mode feedback
circuit adjusts for that, and the TPA6203A1 outputs are still biased at mid-supply of the
TPA6203A1. The inputs of the TPA6203A1 can
be biased from 0.5 V to VDD - 0.8 V. If the inputs
are biased outside of that range, input coupling
capacitors are required.
• Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not
require a bypass capacitor. This is because any
APPLICATION SCHEMATICS
Figure 28 through Figure 30 show application
schematics for differential and single-ended inputs.
Typical values are shown in Table 1.
Table 1. Typical Component Values
COMPONENT
VALUE
RI
10 kΩ
RF
10 kΩ
C(BYPASS)(1)
0.22 µF
CS
1 µF
CI
0.22 µF
(1) C(BYPASS) is optional
VDD A3
RF
In From
DAC
– RI
C3 IN–
+ RI
C2 IN+
Cs
_
+
RF
SHUTDOWN
†
VO+ B3
VO– A1
GND B2
B1
C1
†
To Battery
Bias
Circuitry
C(BYPASS)
C(BYPASS) is optional
Figure 28. Typical Differential Input Application Schematic
9
TPA6203A1
www.ti.com
SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
VDD A3
RF
CI
–
IN
+
RI
C3 IN–
RI
C2 IN+
CI
†
VO+ B3
VO– A1
+
GND B2
B1
Bias
Circuitry
C1
†
Cs
_
RF
SHUTDOWN
To Battery
C(BYPASS)
C(BYPASS) is optional
Figure 29. Differential Input Application Schematic Optimized With Input Capacitors
VDD A3
RF
CI
RI
IN
RI
CI
C3 IN–
C2 IN+
†
VO+ B3
VO– A1
+
GND B2
B1
Bias
Circuitry
C1
†
Cs
_
RF
SHUTDOWN
To Battery
C(BYPASS)
C(BYPASS) is optional
Figure 30. Single-Ended Input Application Schematic
Selecting Components
Resistors (RF and RI)
The input (RI) and feedback resistors (RF) set the
gain of the amplifier according to Equation 1.
Gain = RF/RI
(1)
RF and RI should range from 1 kΩ to 100 kΩ. Most
graphs were taken with RF = RI = 20 kΩ.
10
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second
harmonic distortion diminishes if resistor mismatch
occurs. Therefore, it is recommended to use 1%
tolerance resistors or better to keep the performance
optimized.
TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this
device sets a mid-supply voltage for internal
references and sets the output common mode
voltage to VDD/2. Adding a capacitor to this pin filters
any noise into this pin and increases the kSVR.
C(BYPASS)also determines the rise time of VO+ and VOwhen the device is taken out of shutdown. The larger
the capacitor, the slower the rise time. Although the
output rise time depends on the bypass capacitor
value, the device passes audio 4 µs after taken out of
shutdown and the gain is slowly ramped up based on
C(BYPASS).
Input Capacitor (CI)
The TPA6203A1 does not require input coupling
capacitors if using a differential input source that is
biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance
or better gain-setting resistors if not using input
coupling capacitors.
In the single-ended input application an input
capacitor, CI, is required to allow the amplifier to bias
the input signal to the proper dc level. In this case, CI
and RI form a high-pass filter with the corner
frequency determined in Equation 2.
1
fc 2R C
I I
(2)
–3 dB
In this example, CI is 0.16 µF, so one would likely
choose a value in the range of 0.22 µF to 0.47 µF. A
further consideration for this capacitor is the leakage
path from the input source through the input network
(RI, CI) and the feedback resistor (RF) to the load.
This leakage current creates a dc offset voltage at the
input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason, a
ceramic capacitor is the best choice. When polarized
capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications,
as the dc level there is held at VDD/2, which is likely
higher than the source dc level. It is important to
confirm the capacitor polarity in the application.
Decoupling Capacitor (CS)
The TPA6203A1 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic
distortion (THD) is as low as possible. Power supply
decoupling also prevents oscillations for long lead
lengths between the amplifier and the speaker. For
higher frequency transients, spikes, or digital hash on
the line, a good low equivalent-series- resistance
(ESR) ceramic capacitor, typically 0.1 µF to 1 µF,
placed as close as possible to the device VDD lead
works best. For filtering lower frequency noise
signals, a 10-µF or greater capacitor placed near the
audio power amplifier also helps, but is not required
in most applications because of the high PSRR of this
device.
USING LOW-ESR CAPACITORS
fc
The value of CI is important to consider as it directly
affects the bass (low frequency) performance of the
circuit. Consider the example where RI is 10 kΩ and
the specification calls for a flat bass response down
to 100 Hz. Equation 2 is reconfigured as Equation 3.
1
C I
2R f c
I
(3)
Low-ESR capacitors are recommended throughout
this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in
series with an ideal capacitor. The voltage drop
across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent
value of this resistance the more the real capacitor
behaves like an ideal capacitor.
11
TPA6203A1
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SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
DIFFERENTIAL OUTPUT VERSUS
SINGLE-ENDED OUTPUT
Figure 31 shows a Class-AB audio power amplifier
(APA) in a fully differential configuration. The
TPA6203A1 amplifier has differential outputs driving
both ends of the load. There are several potential
benefits to this differential drive configuration, but
initially consider power to the load. The differential
drive to the speaker means that as one side is
slewing up, the other side is slewing down, and vice
versa. This in effect doubles the voltage swing on the
load as compared to a ground referenced load.
Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from
the same supply rail and load impedance (see
Equation 4).
V
O(PP)
V (rms) 2 2
V
Power 2
(rms)
R
L
(4)
VDD
VO(PP)
In a typical wireless handset operating at 3.6 V,
bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 200
mW to 800 mW. In sound power that is a 6-dB
improvement—which is loudness that can be heard.
In addition to increased power there are frequency
response concerns. Consider the single-supply SE
configuration shown in Figure 32. A coupling
capacitor is required to block the dc offset voltage
from reaching the load. This capacitor can be quite
large (approximately 33 µF to 1000 µF) so it tends to
be expensive, heavy, occupy valuable PCB area, and
have
the
additional
drawback
of
limiting
low-frequency performance of the system. This
frequency-limiting effect is due to the high pass filter
network created with the speaker impedance and the
coupling capacitance and is calculated with Equation
5.
1
fc 2R C
L C
(5)
For example, a 68-µF capacitor with an 8-Ω speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which
eliminates the need for the blocking capacitors.
Low-frequency performance is then limited only by
the input network and speaker response. Cost and
PCB space are also minimized by eliminating the
bulky coupling capacitor.
VDD
VO(PP)
RL
VDD
2x VO(PP)
CC
RL
VO(PP)
–VO(PP)
–3 dB
Figure 31. Differential Output Configuration
fc
Figure 32. Single-Ended Output and Frequency
Response
12
TPA6203A1
www.ti.com
SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the
BTL configuration produces 4× the output power of
the SE configuration.
VO
V(LRMS)
FULLY DIFFERENTIAL AMPLIFIER
EFFICIENCY AND THERMAL INFORMATION
IDD
Class-AB amplifiers are inefficient. The primary cause
of these inefficiencies is voltage drop across the
output stage transistors. There are two components
of the internal voltage drop. One is the headroom or
dc voltage drop that varies inversely to output power.
The second component is due to the sinewave nature
of the output. The total voltage drop can be
calculated by subtracting the RMS value of the output
voltage from VDD. The internal voltage drop multiplied
by the average value of the supply current, IDD(avg),
determines the internal power dissipation of the
amplifier.
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the
power supply to the power delivered to the load. To
accurately calculate the RMS and average values of
power in the load and in the amplifier, the current and
voltage waveform shapes must first be understood
(see Figure 33).
P
Efficiency of a BTL amplifier P
IDD(avg)
Figure 33. Voltage and Current Waveforms for
BTL Amplifiers
Although the voltages and currents for SE and BTL
are sinusoidal in the load, currents from the supply
are very different between SE and BTL
configurations. In an SE application the current
waveform is a half-wave rectified shape, whereas in
BTL it is a full-wave rectified waveform. This means
RMS conversion factors are different. Keep in mind
that for most of the waveform both the push and pull
transistors are not on at the same time, which
supports the fact that each amplifier in the BTL
device only draws current from the supply for half the
waveform. The following equations are the basis for
calculating amplifier efficiency.
L
SUP
where:
2
V rms 2
V
V
P L
, and V
P , therefore, P P
L
LRMS
L
2
R
2R
L
L
1
and P SUP VDD I DDavg and I DDavg 2V
V
P
P sin(t) dt 1 P [cos(t)]
0
R
R
R
L
L
0
L
V
Therefore,
2V
V
DD P
SUP
R
L
substituting PL and PSUP into equation 6,
P
2
Efficiency of a BTL amplifier where:
V
P
2 PL RL
VP
2 RL
2 V DD V P
RL
VP
4 VDD
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the
power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
(6)
13
TPA6203A1
www.ti.com
SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
Therefore,
BTL 2 PL RL
4V
(7)
DD
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8-Ω BTL Systems
Output
Power
(W)
Efficienc
y
(%)
Internal
Dissipation
(W)
Power From
Supply
(W)
Max Ambient
Temperature
(°C)
0.25
31.4
0.55
0.75
62
0.50
44.4
0.62
1.12
54
1.00
62.8
0.59
1.59
58
1.25
70.2
0.53
1.78
65
Table 2 employs Equation 7 to calculate efficiencies
for four different output power levels. Note that the
efficiency of the amplifier is quite low for lower power
levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less
than in the half power range. Calculating the
efficiency for a specific system is the key to proper
power supply design. For a 1.25-W audio system with
8-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 1.8 W.
A final point to remember about Class-AB amplifiers
is how to manipulate the terms in the efficiency
equation to the utmost advantage when possible.
Note that in Equation 7, VDD is in the denominator.
This indicates that as VDD goes down, efficiency goes
up.
A simple formula for calculating the maximum power
dissipated, PDmax, may be used for a differential
output application:
2 V2
DD
P D max 2 RL
(8)
PDmax for a 5-V, 8-Ω system is 634 mW.
The maximum ambient temperature depends on the
heat sinking ability of the PCB system. The derating
factor for the 2 mm x 2 mm Microstar Junior™
package is shown in the dissipation rating table.
Converting this to θJA:
1
1
Θ
113°CW
JA
0.0088
Derating Factor
(9)
14
Given θJA, the maximum allowable junction
temperature, and the maximum internal dissipation,
the maximum ambient temperature can be calculated
with the following equation. The maximum
recommended
junction
temperature
for
the
TPA6203A1 is 125°C.
T A Max T J Max ΘJA P Dmax
125 113(0.634) 53.3°C
(10)
Equation 10 shows that the maximum ambient
temperature is 53.3°C at maximum power dissipation
with a 5-V supply.
Table 2 shows that for most applications no airflow is
required to keep junction temperatures in the
specified range. The TPA6203A1 is designed with
thermal protection that turns the device off when the
junction temperature surpasses 150°C to prevent
damage to the IC. Also, using more resistive than 8-Ω
speakers dramatically increases the thermal
performance by reducing the output current.
PCB LAYOUT
In making the pad size for the BGA balls, it is
recommended
that
the
layout
use
solder-mask-defined (SMD) land. With this method,
the copper pad is made larger than the desired land
area, and the opening size is defined by the opening
in the solder mask material. The advantages normally
associated with this technique include more closely
controlled size and better copper adhesion to the
laminate. Increased copper also increases the
thermal performance of the IC. Better size control is
the result of photo imaging the stencils for masks.
Small plated vias should be placed near the center
ball connecting ball B2 to the ground plane. Added
plated vias and ground plane act as a heatsink and
increase the thermal performance of the device.
Figure 34 shows the appropriate diameters for a 2
mm X 2 mm MicroStar Junior™ BGA layout.
It is very important to keep the TPA6203A1 external
components very close to the TPA6203A1 to limit
noise pickup. The TPA6203A1 evaluation module
(EVM) layout is shown in the next section as a layout
example.
TPA6203A1
www.ti.com
SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
0.38 mm
0.25 mm
0.28 mm
C1
B1
C2
B2
C3
B3
A1
VIAS to Ground Plane
A3
Solder Mask
Paste Mask (Stencil)
Copper Trace
Figure 34. MicroStar Junior™ BGA Recommended Layout
TPA6203A1 EVM PCB Layers
The following illustrations depict the TPA6203A1 EVM PCB layers and silkscreen. These drawings are enlarged
to better show the routing. Gerber plots can be obtained from any TI sales office.
Only Required
Circuitry for Most
Applications
Figure 35. TPA6203A1 EVM Top Layer (Not to scale)
15
TPA6203A1
SLOS364C – MARCH 2002 – REVISED SEPTEMBER 2003
Figure 36. TPA6203A1 EVM Bottom Layer (Not to scale)
16
www.ti.com
MECHANICAL DATA
MPBG144C – JUNE 2000 – REVISED FEBRUARY 2002
GQV (S-PBGA-N8)
PLASTIC BALL GRID ARRAY
2,10
SQ
1,90
1,00 TYP
0,50
C
1,00 TYP
B
A
0,50
1
A1 Corner
2
3
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,35
0,25
∅ 0,05 M
0,25
0,15
0,08
4201040/E 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior configuration
Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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