Data Sheet No. PD60293 IRS254(0,1)(S)PbF LED BUCK REGULATOR CONTROL IC Description Features The IRS254(0,1) are high voltage, high frequency buck control ICs for constant LED current regulation. They incorporate a continuous mode time-delayed hysteretic buck regulator to directly control the average load current, using an accurate on-chip bandgap voltage reference. • 200 V (IRS2540) and 600 V (IRS2541) half bridge driver • Micropower startup (<500 µA) • ±2% voltage reference • 140 ns deadtime • 15.6 V zener clamp on VCC • Frequency up to 500 kHz • Auto restart, non-latched shutdown • PWM dimmable • Small 8-Lead DIP/8-Lead SOIC packages The application is inherently protected against short circuit conditions, with the ability to easily add opencircuit protection. An external high-side bootstrap circuit drives the buck switching element at high frequencies. A low-side driver is also provided for synchronous rectifier designs. All functions are realized within a simple 8 pin DIP or SOIC package. Packages 8-Lead PDIP IRS254(0,1)PbF 8-LeadSOIC IRS254(0,1)SPbF Typical Application Diagram VBUS L2 VOUT+ RS1 RS2 DBOOT IC1 VCC CVCC1 COM DCLAMP CBUS2 CVCC2 2 IFB 3 CBUS1 DOV ENN ROV2 CEN 4 IRS254(0,1) ROV1 1 8 7 6 5 VB HO VS RG1 M1 CBOOT LO L1 M2 RG2 COUT VOUT- RF RCS ROUT CF COM EN DEN1 www.irf.com Page 1 IRS254(0,1)(S)PbF Alternate application circuit using a single MOSFET IRS254(0,1) www.irf.com Page 2 IRS254(0,1)(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. IRS2540 -0.3 225 IRS2541 -0.3 625 VB High-side floating supply voltage VS High-side floating supply offset voltage VB – 25 VB + 0.3 VHO High-side floating output voltage VS – 0.3 VB + 0.3 VLO Low-side output voltage -0.3 VCC + 0.3 Units V VIFB Feedback voltage -0.3 VCC + 0.3 VENN Enable voltage -0.3 VCC + 0.3 Supply current (Note 1) -20 20 mA V/ns ICC dV/dt PD RTHJA Allowable offset voltage slew rate Package power dissipation @ TA ≤ +25 ºC PD = (TJMAX-TA)/RTHJA Thermal resistance, junction to ambient -50 50 (8-Pin DIP) --- 1 (8-Pin SOIC) --- 0.625 (8-Pin DIP) --- 125 (8-Pin SOIC) --- 200 TJ Junction temperature -55 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) --- 300 W ºC/W ºC Note 1: This IC contains a zener clamp structure between the chip VCC and COM, with a nominal breakdown voltage of 15.6 V. Please note that this supply pin should not be driven by a low impedance DC power source greater than VCLAMP specified in the electrical characteristics section. Recommended Operating Conditions For proper operation the device should be used within recommended conditions. Symbol Definition VBS High side floating supply voltage VS Steady state high-side floating supply offset voltage VCC Min. Max. VCC – 0.7 VCLAMP Units IRS2540 -1 200 IRS2541 -1 600 Supply voltage VCCUV+ VCLAMP ICC Supply current Note 2 10 mA TJ Junction temperature -25 125 ºC V Note 2: Sufficient current should be supplied to VCC to keep the internal 15.6 V zener regulating at VCLAMP. www.irf.com Page 3 IRS254(0,1)(S)PbF Electrical Characteristics VCC = VBS = VBIAS = 14 V +/- 0.25 V, CLO=CHO=1000 pF, CVCC=CVBS=0.1 µF, TA=25 °C unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions Supply Characteristics VCCUV+ VCC supply undervoltage positive going threshold 8.0 9.0 10.0 VCCUV- VCC supply undervoltage negative going threshold 6.5 7.5 8.5 VUVHYS VCC supply undervoltage lockout hysteresis 1.0 1.2 2.0 IQCCUV UVLO mode quiescent current --- 50 150 IQCCENN Diesabled mode quiescent current --- 1.0 2.0 IQCC Quiescent VCC supply current --- 1.0 2.0 ICC50k VCC supply current, f = 50 kHz --- 2.0 3.0 14.6 15.6 16.6 VCLAMP VCC zener clamp voltage VCC rising from 0 V V VCC falling from 14 V µA VCC=6 V EN>VENTH+ mA IFB = 1 V Duty Cycle = 50% f = 50 kHz V ICC = 10 mA Floating Supply Characteristics IQBS0 Quiescent VBS supply current --- 1.0 2.0 IQBS1 Quiescent VBS supply current --- 2.0 3.0 VBSUV+ VBS supply undervoltage positive going threshold 6.5 7.5 8.5 VBSUV- VBS supply undervoltage negative going threshold 6.0 7.0 8.0 Offset supply leakage current --- 1 50 ILK mA VHO = VS IFB = 0 V V µA IRS2540:VB=VS=200 V IRS2541:VB=VS=600 V Current Control Operation VENNTH+ ENN pin positive threshold 2.5 2.7 3.0 VENNTH- ENN pin negative threshold 1.7 2.0 2.3 0.5 V voltage reference (die level test) 490 500 510 IFB pin threshold 455 500 540 --- 500 --- kHz V V0.5 VIFBTH f Maximum frequency V mV Gate Driver Output Characteristics www.irf.com VOL Low level output voltage (HO or LO) --- COM --- VHL High level output voltage (HO or LO) --- VCC --- tr Turn-on rise time --- 50 120 tf Turn-off fall time --- 30 50 IO+/- Output source/sink short circuit pulsed current --- 0.5/0.7 --- DT Deadtime --- 140 --- tLO,ON Delay between VIFB>VIFBTH and LO turn-on --- 320 --- tLO,OFF Delay between VIFB<VIFBTH and LO turn-off --- 180 --- tHO,ON Delay between VIFB<VIFBTH and HO turn-on --- 320 --- tHO,OFF Delay between VIFB>VIFBTH and HO turn-off --- 180 --- ns A ns IFB = 50 kHz square wave, 200 mV pk-pk DC offset = 400 mV Duty Cycle = 50% Page 4 IRS254(0,1)(S)PbF Electrical Characteristics VCC = VBS = VBIAS = 14 V +/- 0.25 V, CLO=CHO=1000 pF, CVCC=CVBS=0.1 µF, TA=25 °C unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions Watchdog timer tWD PWWD Watchdog timer period --- 20 --- LO pulse width --- 1.0 --- µs IFB =1 V Functional Block Diagram DELAY LEVEL SHIFT PULSE FILTER & LATCH IFB 3 UVN UVLO DELAY 15.6 V 8 VB 7 HO 6 VS 1 VCC 5 LO 2 COM ENN 4 2V BANDGAP REFERENCE 0. 5 V 100 K Watchdog Timer20 µS 1 µS Pulse Generator Values in block diagram are typical values Lead Assignment Pin Assignments VCC 1 2 IFB 3 ENN 4 IRS254(0,1) www.irf.com COM 8 VB 7 HO 6 VS 5 LO Pin # Symbol Description 1 2 3 VCC Supply voltage COM IFB IC power & signal ground Current feedback 4 5 ENN LO Disable outputs (LO=High, HO=Low) Low-side gate driver output 6 VS High-side floating return 7 8 HO VB High-side gate driver output High-side gate driver floating supply Page 5 IRS254(0,1)(S)PbF STATE DIAGRAM www.irf.com Page 6 IRS254(0,1)(S)PbF is large enough to maintain a low ripple on IFB, Iout,avg can be calculated: Functional Description Operating Mode Iout (avg ) = VIFBTH The IRS254(0,1) operates as a time-delayed hysteritic buck controller. During normal operating conditions the output current is regulated via the IFB pin voltage (nominal value of 500 mV). This feedback is compared to an internal high precision bandgap voltage reference. An on-board dV/dt filter has also been used to ignore erroneous transitioning. Once the supply to the IC reaches VCCUV+, the LO output is held high and the HO output low for a predetermined period of time. This initiates charging of the bootstrap capacitor, establishing the VBS floating supply for the high-side output. The IC then begins toggling HO and LO outputs as needed to regulate the current. RCS (A) (B) Fig.2 (A) Storing Energy in Inductor (B) Releasing Inductor Stored Energy HO 50% 50% 50% t_HO_off t_HO_on DT1 Iout DT2 50% 50% LO HO t_LO_on t_LO_off IFB IFBTH LO Fig.1 IRS254(0,1) Control Signals, Iavg=1.2 A As long as VIFB is below VIFBTH, HO is on, modulated by the watchdog timer described below, the load is receiving current from VBUS, which simultaneously stores energy in the inductor, as VIFB increases, unless the load is open. Once VIFB crosses VIFBTH, the control loop switches HO off after the delay tHO,OFF. Once HO is off, LO will turn on after the deadtime (DT), the inductor releases the stored energy into the load and VIFB starts decreasing. When VIFB crosses VIFBTH again, the control loop switches HO on after the delay tHO,ON and LO off after the delay tHO,ON + DT. The switching continues to regulate the current at an average value determined as follows. When the inductance value www.irf.com Fig.3 IRS254(0,1) Time Delayed Hysterisis The control method is based upon a free running frequency, in constrast to a more widely used fixed frequency regulation. This reduces the part count since there is no need for frequency setting components and also provides an inherently stable sytem, which acts as a current source. A deadtime of approximately 140 ns between the two gate drive signals is necessary to prevent a “shoot-through” condition. At higher frequencies, the switching losses become very large in the absence of this deadtime. The deadtime has been adjusted to maintain precise current regulation, while still preventing shoot-through. Page 7 IRS254(0,1)(S)PbF Watchdog Timer During an open circuit condition, without the watchdog timer, the HO output would remain high at all times and the charge stored in the bootstrap capacitor CBOOT would gradually discharge the floating power supply for the high-side driver, which would then be unable to fully switch on the upper MOSFET causing high losses. To maintain sufficient charge on the bootstrap capacitor, a watchdog timer has been implemented. In the condition where VIFB remains below VIFBTH, the HO output will be forced low after 20 µs and the LO output forced high. This toggling of the outputs will last for approximately 1 µs to maintain and replenish sufficient charge on CBOOT. HO Design Tip (DT 98-2), “Bootstrap Component Selection For Control ICs” at www.irf.com under Design Support Disable (ENN) Pin The disable pin can be used for dimming and opencircuit protection. When the ENN pin is held low, the chip remains in a fully functional state with no alterations to the operating environment. To disable the control feedback and regulation, a voltage greater than VENTH (approximately 2.5 V) needs to be applied to the ENN pin. With the chip in a disabled state, HO output will remain low, whereas the LO output will remain high to prevent VS from floating, in addition to maintaining charge on the bootstrap capacitor. The threshold for disabling the IRS254(0,1) has been set to 2.5 V to enhance immunity to any externally generated noise, or application ground noise. This 2.5 V threshold also makes it ideal to receive a drive signal from a local microcontroller. Dimming Mode LO Fig.4 Illustration of Watchdog Timer Bootstrap Capacitor and Diode The bootstrap capacitor value needs to be chosen so that it maintains sufficient charge for at least the approximately 20 µs interval until the watchdog timer allows the capacitor to recharge. If the capacitor value is too small, the charge will dissipate in less than 20 µs. The typical bootstrap capacitor is approximately 100 nF. The bootstrap diode should be a fast recovery or ultrafast recovery component to maintain good efficiency. Since the cathode of the bootstrap diode will be switching between zero and to the high voltage bus, the reverse recovery time of this diode is of critical importance. For additional information concerning the bootstrap components, refer to the www.irf.com To achieve dimming, a signal with constant frequency and set duty cycle can be fed into the ENN pin. There is a direct linear relationship between the average load current and duty cycle. If the ratio is 50%, 50% of the maximum set light output will be realized. Likewise if the ratio is 30%, 70% of the maximum set light output will be realized. A sufficiently high frequency of the dimming signal must be chosen to avoid flashing or “strobe light” effect. A signal on the order of a few kHz should be sufficient. The minimum amount of dimming achievable (light output approaches 0%) will be determined by the “on” time of the HO output, when in a fully functional regulating state. To maintain reliable dimming, it is recommended to keep the “off” time of the enable signal at least 10 times that of the HO “on” time. For example, if the application is running at 75 kHz with an input voltage of 100 V and an output voltage of 20 V, the HO “on” time will be 3.3 µs (one-fourth of the period – see calculations below) according to standard buck topology theory. This will set the minimum “off” time of the enable signal to 33 µs. Duty Cycle = V out 20V ∗100 = *100 = 20% Vin 100V HOon time = 20% * 1 75kHz = 3.3µs Page 8 IRS254(0,1)(S)PbF form the voltage clamp. The repetition of the spikes can be reduced by simply increasing the capacitor size. Enable Duty Cycle Relationship to Light Output 100 90 Enable Pin Duty Cycle 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 Percentage of Light Output Fig.5 Light Output vs Enable Pin Duty Cycle The two resistors form a voltage divider for the output, which is then fed into the cathode of the zener diode. The diode will only conduct, flooding the enable pin, when its nominal voltage is exceeded. The chip will enter a disabled state once the divider network produces a voltage at least 2.5 V greater than the zener rating. The capacitor serves only to filter and slow the transients/switching at the positive output terminal. The clamped output voltage can be determined by the following analysis. The choice of capacitor is at the designer’s discretion. Vout = EN (2.5V + DZ )(R1 + R2 ) R2 DZ = Zener Diode Nominal Rated Voltage HO LO Fig.6 IRS254(0,1) Dimming Signals Open Circuit Protection Mode IRS2540/1 By using the suggested Vout voltage divider, R1 capacitor, and zener diode, the output IFB voltage can be clamped 3 at any desired value. In EN open-circuit condition 4 without output clamp, R2 the positive output terminal will float at the Fig.7 Open Circuit high-side input voltage. Protection Scheme Switching will still occur between the HO and LO outputs, whether due to the output voltage clamp or the watchdog timer. Transients and switching will be observed at the positive output terminal as seen in Fig. 8. The difference in signal shape, between the output voltage and the IFB, is due to the capacitor used to www.irf.com Fig.8 Open Circuit Fault Signals, with Clamp Under-voltage Lock-out Mode The under-voltage lock-out mode (UVLO) is defined as the state IRS254(0,1) is in when VCC is below the turn-on threshold of the IC. During startup conditions, if the IC supply remains below VCCUV+, the IRS254(0,1) will enter the UVLO mode. This state is very similar to when the IC has been disabled via control signals, except that LO is also held low. When the supply is increased to VCCUV+, the IC enters the normal operation mode. If already in normal Page 9 IRS254(0,1)(S)PbF To maintain tight hysteretic current regulation the inductor and output capacitor COUT (in parallel with the LEDs) need to be large enough to maintain the supply to the load during tHO,ON and avoid significant undershooting of the load current, which in turn causes the average current to fall below the desired value. First, we are going to look at the effect of the inductor when there is no output capacitor to clearly demonstrate the impact of the inductor. In this case, the load current is identical to the inductor current. Fig. 9 shows how the inductor value impacts the frequency over a range of input voltages. As can be seen, the input voltage has a great impact on the frequency and the inductor value has the greatest impact at reducing the frequency for smaller input voltages. add capacitance no longer has a significant effect on the operating frequency or current regulation, as can be seen in Figs. 13 and 14. 400 390 380 Iout (mA) operation, the IC does not enter UVLO unless the supply voltage falls below VCCUV--. Inductance Selection 470uH 370 680uH 360 1mH 1.5mH 350 340 330 30 80 130 180 Vin (V) Fig.10 Current Regulation for Chosen Inductances Iout = 350 mA, Vout = 16.8 V 400 425 380 360 470uH 325 680uH 1mH 275 1.5mH Frequency (kHz) Frequency (kHz) 375 340 470uH 320 680uH 300 1mH 280 1.5mH 260 240 225 220 200 175 30 80 130 13 180 18 The output capacitor can be used simultaneously to achieve the target frequency and current control accuracy. Fig. 11 shows how the capacitance reduces the frequency over a range of input voltage. A small capacitance of 4.7 µF has a large effect on reducing the frequency. Fig. 12 shows how the current regulation is also improved with the output capacitance. There is a point at which continuing to www.irf.com 28 33 Fig.11 Frequency Response for Chosen Inductances Iout = 350 mA, Vin = 50 V Fig.9 Frequency Response for Chosen Inductances Iout = 350 mA, Vout = 16.8 V 345 343 341 339 Iout (mA) Fig. 10 shows how the variation in load current increases over a span of input voltages, as the inductance is decreased. Fig. 11 shows the variation of frequency over different output voltages and different inductance values. Finally Fig. 12 shows how the load current variation increases with lower inductance over a range of output voltages. 23 Vout (V) Vin (V) 470uH 337 680uH 335 1mH 333 1.5mH 331 329 327 325 13 18 23 28 33 Vout (V) Fig.12 Current Regulation for Chosen Inductances Iout = 350 mA, Vin = 50 V Page 10 IRS254(0,1)(S)PbF 0uF 1000 from the output needs to be implemented, as seen in Fig. 16. 4.7uF 10uF Frequency (kHz) 22uF 33uF 47uF 100 10 30 50 70 90 110 130 150 170 Vin (V) Fig. 13 Iout = 350 mA, Vout = 16.8 V, L = 470 µH 400 350 Fig. 15 Iout = 350 mA, Vin = 100 V, Vout = 16.85 V, L = 470 µH, C out = 33 µF Frequency (kHz) 300 250 40V 200 100V 160V 150 100 50 0 0 10 20 30 40 50 Capacitance (uF) Fig. 14 I out = 350 mA, Vout = 16.8 V, L = 470 µH The addition of the COUT increases the amount of energy that can be stored in the output stage, which also means it can supply current for an increased period of time. Therefore by slowing down the di/dt transients in the load, the frequency is effectively decreased. With the COUT capacitor, the inductor current is no longer identical to that seen in the load. The inductor current will still have a perfectly triangular shape, where as the load will see the same basic trend in the current, but all sharp corners will be rounded with all peaks significantly reduced, as can be seen in Fig. 15 The resistance between VBUS and VCC supply should be large enough to minimize the current sourced directly from the input voltage line; value should be on the order of hundreds of kΩ. Through the supply resistor, a current will flow to charge the VCC capacitor. Once the capacitor is charged up to the VCCUV+ threshold, the IRS254(0,1) enters the micro start-up regime and begins to operate, activating the LO and HO outputs. After the first few cycles of switching, the resistor connected between the output and VCC will take over and source all necessary current for the IC. The resistor connecting the output to the supply should be carefully designed according to its power rating. RS 2 = PRS 2 = (10mA) 2 RS 2 ≤ PRS 2 _ Rated 2 Icc ≈ 10mA VBUS VCC COM IFB ENN ENN 1 2 3 4 IRS254(0,1) VCC Supply Since the IRS245(0,1) is rated for 200 V (or 600 V), VBUS can reach values of this magnitude. If only a supply resistor to VBUS is used, it will experience extremely high power losses. For higher voltage applications an alternate VCC supply scheme utilizing the micro-power start-up and a resistor feed-back Vout − 15.6V 10mA 8 7 6 5 VB HO VS LO COM Fig. 16 Alternate Supply Diagram www.irf.com Page 11 IRS254(0,1)(S)PbF www.irf.com Page 12 IRS254(0,1)(S)PbF 8-Lead SOIC Tape & Reel LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60 8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 Page 13 IRS254(0,1)(S)PbF ORDER INFORMATION 8-Lead PDIP IRS2540PbF 8-Lead PDIP IRS2541PbF 8-Lead SOIC IRS2540SPbF 8-Lead SOIC IRS2541SPbF 8-Lead SOIC Tape & Reel IRS2540STRPbF 8-Lead SOIC Tape & Reel IRS2541STRPbF The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com <http://www.irf.com> IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice 2/2/2007 www.irf.com Page 14