SCPS068C - JULY 2001 − REVISED JANUARY 2004 D Low Standby-Current Consumption of 15 3 14 4 13 5 12 6 11 7 10 8 9 SCL NC SDA VCC A0 A1 NC A2 P7 2 VCC SDA SCL INT P7 P6 P5 P4 1 20 DGV OR PW PACKAGE (TOP VIEW) 19 P6 18 NC 2 3 17 P5 16 P4 4 5 15 GND 14 P3 6 7 13 NC 12 P2 8 9 10 11 P1 16 INT 1 Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II RGY PACKAGE (TOP VIEW) DW OR N PACKAGE (TOP VIEW) A0 A1 A2 P0 P1 P2 P3 GND D P0 D D D D Latched Outputs With High-Current Drive 10 µA Maximum I2C to Parallel-Port Expander Open-Drain Interrupt Output Compatible With Most Microcontrollers INT SCL NC SDA VCC A0 A1 NC A2 P0 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 P7 P6 NC P5 P4 GND P3 NC P2 P1 NC − No internal connection NC − No internal connection description/ordering information This 8-bit input/output (I/O) expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 6-V VCC operation. The PCF8574 provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The device features an 8-bit quasi-bidirectional I/O port (P0−P7), including latched outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to VCC is active. An additional strong pullup to VCC allows fast rising edges into heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be high before being used as inputs. ORDERING INFORMATION −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING QFN − RGY Tape and reel PCF8574RGYR PF574 PDIP − N Tube PCF8574N PCF8574N Tube PCF8574DW Tape and reel PCF8574DWR TSSOP − PW Tape and reel PCF8574PWR PF574 TVSOP − DGV Tape and reel PCF8574DGVR PF574 SOIC − DW PCF8574 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCPS068C - JULY 2001 − REVISED JANUARY 2004 description/ordering information (continued) The PCF8574 provides an open-drain output (INT) that can be connected to the interrupt input of a microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge bit after the rising edge of the SCL signal or in the write mode at the acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or writing to, another device does not affect the interrupt circuit. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Therefore, the PCF8574 can remain a simple slave device. logic diagram (positive logic) PCF8574 INT A0 A1 A2 SCL SDA 13 Interrupt Logic LP Filter 1 4 2 5 3 6 14 15 Input Filter I2C Bus Control 7 Shift Register 8 Bit I/O Port 9 10 11 12 Write Pulse VCC GND Read Pulse 16 8 Power-On Reset Pin numbers shown are for the DW and N packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P0 P1 P2 P3 P4 P5 P6 P7 SCPS068C - JULY 2001 − REVISED JANUARY 2004 simplified schematic diagram of each P-port input/output VCC Write Pulse 100 µA Data From Shift Register D Q FF P0−P7 CI S Power-On Reset D Q GND FF CI Read Pulse S To Interrupt Logic Data to Shift Register I2C interface I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. The address inputs (A0−A2) of the slave device must not be changed between the start and the stop conditions. The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data will be valid at time tpv after the low-to-high transition of SCL and during the clock cycle for the acknowledge. A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master. INTERFACE DEFINITION BIT BYTE I2C slave address I/O data bus 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H L L A2 A1 AO R/W P7 P6 P5 P4 P3 P2 P1 P0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCPS068C - JULY 2001 − REVISED JANUARY 2004 ADDRESS REFERENCE INPUTS A0 I2C-BUS SLAVE ADDRESS A2 A1 L L L 32 (decimal), 20 (hexadecimal) L L H 33 (decimal), 21 (hexadecimal) L H L 34 (decimal), 22 (hexadecimal) L H H 35 (decimal), 23 (hexadecimal) H L L 36 (decimal), 24 (hexadecimal) H L H 37 (decimal), 25 (hexadecimal) H H L 38 (decimal), 26 (hexadecimal) H H H 39 (decimal), 27 (hexadecimal) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Input/Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 µA Continuous output low current, IOL (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output high current, IOH (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −4 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions MIN 4 VCC VIH Supply voltage High-level input voltage 0.7 × VCC 2.5 VIL IOH Low-level input voltage −0.5 IOL TA MAX 6 UNIT V VCC + 0.5 0.3 × VCC V High-level output current −1 mA Low-level output current 25 mA 85 °C Operating free-air temperature −40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SCPS068C - JULY 2001 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN 2.5 V to 6 V −1.2 VIK VPOR Input diode clamp voltage Power-on reset voltage‡ II = −18 mA VI = VCC or GND, IOH IOHT P port VO = GND High during acknowledge VOH = GND 2.5 V to 6 V 2.5 V to 6 V P port VO = 0.4 V VO = 1 V 5V 10 INT VO = 0.4 V 2.5 V to 6 V 1.6 P-port transient pullup current SDA IOL IO = 0 6V TYP† MAX 1.3 2.4 V 30 2.5 V 300 INT P port Operating mode ICC Standby mode Ci SCL 25 mA 3 ±5 VI = VCC or GND ±5 2.5 V to 6 V P port µA ±5 VI ≥ VCC or VI ≤ GND VI = VCC or GND, IO = 0, VI = VCC or GND, VI = VCC or GND ±400 2.5 V to 6 V fSCL = 100 kHz IO = 0 6V 2.5 V to 6 V SDA Cio µA mA A0, A1, A2 IIHL V −1 SCL, SDA II UNIT VIO = VCC or GND 2.5 V to 6 V 40 100 2.5 10 1.5 7 3 7 4 10 µA µA A pF pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ The power-on reset circuit resets the I2C-bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC). I2C interface timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) MIN fscl tsch I2C clock frequency I2C clock high time tscl tsp I2C clock low time I2C spike time 4.7 tsds tsdh I2C serial data setup time I2C serial data hold time 250 ticr ticf I2C input rise time I2C input fall time tocf tbuf I2C output fall time (10-pF to 400-pF bus) I2C-bus free time between stop and start tsts tsth I2C start or repeated start condition setup I2C start or repeated start condition hold tsps tvd I2C stop-condition setup Cb MAX UNIT 100 kHz µs 4 µs 100 0 Valid data time I2C-bus capacitive load POST OFFICE BOX 655303 ns 900 ns 1 µs 0.3 µs 300 SCL low to SDA output valid • DALLAS, TEXAS 75265 ns ns 4.7 µs 4.7 µs 4 µs 4 µs 3.4 µs 400 pF 5 SCPS068C - JULY 2001 − REVISED JANUARY 2004 switching characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 2) PARAMETER 6 FROM (INPUT) TO (OUTPUT) SCL P port MIN MAX µs tpv Output data valid tsu Input data setup time P port SCL 0 µs th Input data hold time P port SCL 4 µs tiv Interrupt valid time P port INT 4 µs tir Interrupt reset delay time SCL INT 4 µs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4 UNIT SCPS068C - JULY 2001 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ DUT Pn CL = 10 pF to 400 pF LOAD CIRCUIT 2 Bytes for Complete Device Programming Stop Condition (P) Start Condition (S) Bit 7 MSB Bit 0 LSB (R/W) Bit 6 tscl Acknowledge (A) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr tPHL ticf tbuf tsts tPLH tsp 0.7 × VCC SDA 0.3 × VCC ticf tsth Start or Repeat Start Condition ticr tsdh tsds tsps Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE 1 DESCRIPTION 2 I C address 2 P-port data Figure 1. I2C Interface Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCPS068C - JULY 2001 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION Acknowledge From Slave Start Condition Acknowledge From Slave R/W Slave Address (PCF8574) S Data From Port 0 1 0 0 A2 A1 A0 1 A 1 2 3 4 A 5 6 7 8 Data 1 Data From Port Data 3 A 1 P A tir tir B B INT tiv A tsps A Data Into Port Data 1 Data 2 0.7 × VCC INT 0.3 × VCC SCL 0.7 × VCC R/W tiv 0.3 × VCC 0.7 × VCC INT 0.3 × VCC 0.3 × VCC View A−A View B−B Figure 2. Interrupt-Timing Waveforms 8 A tir 0.7 × VCC Pn Data 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCPS068C - JULY 2001 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 0.7 × VCC SCL W A D 0.3 × VCC Slave Acknowledge SDA ÎÎÎ ÎÎÎ Pn Unstable Data tpv Last Stable Bit Figure 3. Write-Mode Timing VCC VCC RL = 1 kΩ DUT RL = 4.7 kΩ SDA DUT INT CL = 10 pF to 400 pF CL = 10 pF to 400 pF GND GND SDA LOAD CONFIGURATION INTERRUPT LOAD CONFIGURATION Figure 4. Load Circuits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCF8574DGVR ACTIVE TVSOP DGV 20 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM PCF8574DW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM PCF8574DWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM PCF8574N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC PCF8574PW ACTIVE TSSOP PW 20 70 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM PCF8574PWR ACTIVE TSSOP PW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM PCF8574RGYR ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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