TI SN74LVC573APW

SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
D
D
D
D
D
D
description
SN54LVC573A . . . J OR W PACKAGE
SN74LVC573A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54LVC573A . . . FK PACKAGE
(TOP VIEW)
3D
4D
5D
6D
7D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
The SN54LVC573A octal transparent D-type latch
is designed for 2.7-V to 3.6-V VCC operation and
the SN74LVC573A octal transparent D-type latch
is designed for 1.65-V to 3.6-V VCC operation.
1Q
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Power Off Disables Outputs, Permitting
Live Insertion
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and DIPs (J)
2D
1D
OE
VCC
D
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
description (continued)
The SN54LVC573A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC573A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
EN
C1
19
1D
3
18
4
17
5
16
6
15
7
14
8
13
9
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
LE
1
11
C1
1D
2
19
1D
To Seven Other Channels
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1Q
SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVC573A
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High level output current
High-level
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
1.5
UNIT
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
SN74LVC573A
MIN
V
1.7
2
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.7
0.8
V
0.8
0
5.5
0
5.5
V
High or low state
0
0
VCC
5.5
0
3 state
VCC
5.5
V
0
VCC = 1.65 V
VCC = 2.3 V
–4
–8
VCC = 2.7 V
VCC = 3 V
–12
–12
–24
–24
VCC = 1.65 V
VCC = 2.3 V
mA
4
8
VCC = 2.7 V
VCC = 3 V
12
12
24
0
6
mA
24
0
6
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
2.7 V to 3.6 V
IOH = –4 mA
IOH = –8 mA
SN74LVC573A
TYP†
MAX
MIN
1.65 V to 3.6 V
IOH = –100
100 µA
VOH
SN54LVC573A
TYP†
MAX
VCC
MIN
VCC–0.2
VCC–0.2
1.65 V
1.2
2.3 V
IOH = –12
12 mA
IOH = –24 mA
V
1.7
2.7 V
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
1.65 V to 3.6 V
IOL = 100 µA
UNIT
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
0.4
3V
0.55
0.55
II
VI = 0 to 5.5 V
3.6 V
±5
±5
µA
Ioff
VI or VO = 5.5 V
IOZ
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V‡
VOL
ICC
IO = 0
∆ICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
Co
±10
µA
±15
±10
µA
10
10
10
10
500
500
0
3.6 V
VO = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This applies in the disabled state only.
36V
3.6
2.7 V to 3.6 V
V
µA
µA
3.3 V
4
4
pF
3.3 V
5.5
5.5
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 3)
SN54LVC573A
VCC = 2.7 V
MIN
4
tw
tsu
Pulse duration, LE high
th
Hold time, data after LE↓
Setup time, data before LE↓
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
3.3
3.3
ns
2
2
ns
2.5
2.5
ns
SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
SN74LVC573A
VCC = 1.8 V
± 0.15 V
MIN
tw
tsu
VCC = 2.5 V
± 0.2 V
MAX
MIN
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
Pulse duration, LE high
†
†
3.3
3.3
ns
Setup time, data before LE↓
†
†
2
2
ns
†
†
1.5
1.5
ns
th
Hold time, data after LE↓
† This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC573A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 2.7 V
MIN
D
tpd
d
Q
LE
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
7.7
1
6.9
8.4
1
7.7
UNIT
ns
ten
OE
Q
8.5
1
7.5
ns
tdis
OE
Q
7
0.5
6.7
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC573A
PARAMETER
FROM
(INPUT)
D
tpd
d
LE
TO
(OUTPUT)
Q
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
†
†
†
†
†
†
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
†
7.7
1.5
6.9
†
8.4
2
7.7
UNIT
ns
ten
OE
Q
†
†
†
†
8.5
1.5
7.5
ns
tdis
OE
Q
†
†
†
†
7
1.6
6.5
ns
1
ns
tsk(o)‡
† This information was not available at the time of publication.
‡ Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per latch
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
TYP
†
†
37
†
†
4
UNIT
pF
† This information was not available at the time of publication.
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SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1k Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1k Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOL
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
Input
1.5 V
1.5 V
tsu
Input
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
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Copyright  1998, Texas Instruments Incorporated