SGLS230A − JANUARY 2004 − REVISED JUNE 2008
D Meets AEC-Q100-011 C3A CDM
D
D
D
D
D
D
D
D
D
D
D
D
D
Classification
Qualified for Automotive Applications
8-Bit Resolution, 35 MSPS Sampling
Analog-to-Digital Converter (ADC)
Low Power Consumption: 90 mW Typ
Using External References
Wide Analog Input Bandwidth: 600 MHz Typ
3.3-V Single-Supply Operation
3.3-V TTL /CMOS-Compatible Digital I/O
Internal Bottom and Top Reference
Voltages
Adjustable Reference Input Range
Power-Down (Standby) Mode
Separate Power Down for Internal Voltage
References
Three-State Outputs
28-Pin Thin Shrink SOP (TSSOP) Packages
Applications
− Digital Communications (IF Sampling)
− High-Speed DSP Front-End
(TMS320C6000)
− Video Processing (Scan Rate/Format
Conversion)
− DVD Read Channel Digitization
PW PACKAGE
(TOP VIEW)
DRVDD
D0
D1
D2
D3
D4
D5
D6
D7
DRVSS
DVSS
CLK
OE
DVDD
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AVSS
AVDD
AIN
CML
PWDN_REF
AVSS
REFBO
REFBI
REFTI
REFTO
AVSS
BG
AVDD
STBY
description/ordering information
The TLV5535 is an 8-bit, 35 MSPS, high-speed A/D converter. It converts the analog input signal into 8-bit
binary-coded digital words up to a sampling rate of 35 MHz. All digital inputs and outputs are 3.3 V
TTL /CMOS-compatible.
The device consumes very little power due to the 3.3-V supply and an innovative single-pipeline architecture
implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage
references from user-supplied voltages. If no external references are available, on-chip references are
available for internal and external use. The full-scale range is 1 Vpp up to 1.6 Vpp, depending on the analog
supply voltage. If external references are available, the internal references can be disabled independently from
the rest of the chip, resulting in an even greater power saving.
ORDERING INFORMATION{
TJ
PACKAGE}
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
TSSOP (PW)
Tape and reel
TLV5535IPWRQ1
TLV5535Q1
† For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2008 Texas Instruments Incorporated
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1
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description (continued)
While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed
graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD
read channel digitization, medical imaging, and communications. This device is suitable for IF sampling of
communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth.
functional block diagram
+
ADC
−
SHA
SHA
ADC
SHA
SHA
SHA
SHA
2
DAC
2
2
2
2
2
2
Correction Logic
Output Buffers
D0(LSB)−D7(MSB)
The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a
resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from
each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction
logic ensures no missing codes over the full operating temperature range.
2
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circuit diagrams of inputs and outputs
ALL DIGITAL INPUT CIRCUITS
AIN INPUT CIRCUIT
DVDD
AVDD
0.5 pF
REFERENCE INPUT CIRCUIT
AVDD
Internal
Reference
Generator
REFTO
or
REFBO
D0−D7 OUTPUT CIRCUIT
DRVDD
D
AVDD
D_Out
OE
REFBI
or
REFTI
DRVSS
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3
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Terminal Functions
TERMINAL
NAME
AIN
AVDD
AVSS
NO.
I/O
DESCRIPTION
26
I
Analog input
16, 27
I
Analog supply voltage
18, 23, 28
I
Analog ground
BG
17
O
Band gap reference voltage. A 1-µF capacitor (with an optional 0.1-µF capacitor in parallel) should be
connected between this terminal and AVSS for external filtering.
CLK
12
I
Clock input. The input is sampled on each rising edge of CLK.
CML
25
O
Common mode level. This voltage is equal to (AVDD − AVSS) ÷ 2. An external 0.1-µF capacitor should be
connected between this terminal and AVSS.
D0 − D7
2−9
O
Data outputs. D7 is the MSB.
DRVDD
DRVSS
1
I
Supply voltage for digital output drivers
10
I
Ground for digital output drivers
DVDD
14
I
Digital supply voltage
OE
13
I
Output enable. When high, the D0 − D7 outputs go in high-impedance mode.
DVSS
11
I
Digital ground
PWDN_REF
24
I
Power down for internal reference voltages. A high on this terminal disables the internal reference circuit.
REFBI
21
I
Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the
ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering
should be applied to this input. The use of a 0.1-µF capacitor connected between REFBI and AVSS is
recommended. Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.
REFBO
22
O
Reference voltage bottom output. An internally generated reference is available at this terminal. It can be
connected to REFBI or left unconnected. A 1-µF capacitor between REFBO and AVSS provides sufficient
decoupling required for this output.
REFTI
20
I
Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.
It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be
applied to this input. The use of a 0.1-µF capacitor between REFTI and AVSS is recommended.
Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.
REFTO
19
O
Reference voltage top output. An internally generated reference is available at this terminal. It can be
connected to REFTI or left unconnected. A 1-µF capacitor between REFTO and AVSS provides sufficient
decoupling required for this output.
STBY
15
I
Standby input. A high level on this input enables power-down mode.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range: AVDD to AVSS, DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V
AVDD to DVDD, AVSS to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 0.5 V
Digital input voltage range to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to DVDD + 0.5 V
Analog input voltage range to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to AVDD + 0.5 V
Digital output voltage range applied from external source to DGND . . . . . . . . . . . . . . −0.5 V to DVDD + 0.5 V
Reference voltage input range to AGND: V(REFTI), V(REFTO), V(REFBI), V(REFBO) −0.5 V to AVDD + 0.5 V
Operating free-air temperature range, TA: TLV5535I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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recommended operating conditions over operating free-temperature range
power supply
AVDD − AVSS
DVDD − DVSS
Supply voltage
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
DRVDD − DRVSS
analog and reference inputs
Reference input voltage (top), V(REFTI)
Reference input voltage (bottom), V(REFBI)
MIN
NOM
MAX
UNIT
(NOM) − 0.2
2 + (AVDD − 3)
(NOM) + 0.2
V
0.8
1
1.2
V
1 + (AVDD − 3)
V
V(REFTI)
V
Reference voltage differential, V(REFTI) − V(REFBI)
Analog input voltage, V(AIN)
V(REFBI)
digital inputs
MIN
High-level input voltage, VIH
NOM
2.0
Low-level input voltage, VIL
DGND
Clock period, tc
MAX
UNIT
DVDD
0.2xDVDD
V
V
28.6
ns
Pulse duration, clock high, tw(CLKH)
13
ns
Pulse duration, clock low, tw(CLKL)
13
ns
electrical characteristics over recommended operating conditions, fCLK = 35 MSPS, external
voltage references (unless otherwise noted)
power supply
PARAMETER
IDD
Operating supply current
TEST CONDITIONS
AVDD
DVDD
DRVDD
PD
Power dissipation
PD(STBY)
Standby power
MIN
TYP
MAX
27
34
AVDD = DVDD = 3.3 V, DRVDD = 3 V,
CL = 15 pF, VI = 1 MHz, −1-dB FS
1.5
2.6
4
6
PWDN_REF = L
106
139
PWDN_REF = H
90
113
STBY = H,
11
15
TYP
MAX
CLK held high or low
UNIT
mA
mW
digital logic inputs
PARAMETER
IIH
High-level input current on CLK†
IIL
Low-level input current on digital inputs
(OE, STDBY, PWDN_REF, CLK)
TEST CONDITIONS
AVDD = DVDD = DRVDD = CLK = 3.6 V
AVDD = DVDD = DRVDD = 3.6 V,
Digital inputs at 0 V
MIN
UNIT
10
µA
10
µA
CI
Input capacitance
5
pF
† IIH leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of
4 KΩ to DGND.
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electrical characteristics over recommended operating conditions, fCLK = 35 MSPS, external
voltage references (unless otherwise noted) (continued)
logic outputs
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA,
Digital output forced high
VOL
Low-level output voltage
AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA,
Digital output forced low
CO
Output capacitance
IOZH
High-impedance state output current to
high level
IOZL
MIN
TYP
MAX
2.8
V
0.1
5
High-impedance state output current to
low level
UNIT
V
pF
10
µA
10
µA
AVDD = DVDD = DRVDD = 3.6 V
dc accuracy
PARAMETER
TEST CONDITIONS
Integral nonlinearity (INL), best-fit
Internal references (see Note 1)
TA = 25°C
TA = −40°C to 85°C
Differential nonlinearity (DNL)
Internal references (see Note 2),
TA = −40°C to 85°C
Zero error
MIN
TYP
MAX
UNIT
−1.5
±0.7
1.5
LSB
−2.4
±0.7
2.4
LSB
−1
± 0.6
1.3
LSB
5
%FS
5
%FS
AVDD = DVDD = 3.3 V, DRVDD = 3 V,
Internal references (see Note 3)
Full-scale error
NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The
deviation is measured from the center of each particular code to the true straight line between these two endpoints.
2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test [i.e., (last transition level − first transition level) ÷ (2n − 2)]. Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than −1 LSB ensures no missing codes.
3. Zero error is defined as the difference in analog input voltage − between the ideal voltage and the actual voltage − that switches
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).
Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).
analog input
PARAMETER
CI
6
TEST CONDITIONS
Input capacitance
MIN
TYP
4
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MAX
UNIT
pF
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
electrical characteristics over recommended operating conditions, fCLK = 35 MSPS, external
voltage references (unless otherwise noted) (continued)
reference input (AVDD = DVDD = DRVDD = 3.6 V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Rref
Reference input resistance
400
Ω
Iref
Reference input current
2.5
mA
reference outputs
PARAMETER
V(REFTO)
V(REFBO)
Reference top offset voltage
Reference bottom offset voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Absolute min/max values valid
and tested for AVDD = 3.3 V
2.07
2 + [(AVDD − 3) ÷ 2]
2.21
V
1.09
1 + [(AVDD − 3) ÷ 2]
1.21
V
MIN
TYP
MAX
UNIT
6.6
7.4
6.6
7.4
dynamic performance†
PARAMETER
Effective number of bits (ENOB)
TEST CONDITIONS
fin = 1 MHz
fin = 4.2 MHz
fin = 15 MHz
fin = 1 MHz
Signal-to-noise ratio + distortion (SNRD)
Total harmonic distortion (THD)
fin = 4.2 MHz
fin = 15 MHz
fin = 1 MHz
fin = 4.2 MHz
fin = 15 MHz
fin = 1 MHz
Spurious free dynamic range (SFDR)
fin = 4.2 MHz
fin = 15 MHz
Analog input full-power bandwidth, BW
See Note 4
Bits
7
41.5
46
41.5
46
dB
43
−46
−55
−45.5
−54
dB
−50
48
58
48
58
dB
52
600
MHz
0.6°
Differential phase, DP
fCLK = 35 MHz, fin = 4.2 MHz,
20 IRE amplitude vs full-scale of 140 IRE
Differential gain, DG
0.2%
† Based on analog input voltage of − 1-dB FS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at
fCLK = 35 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3 V at 25°C.
NOTE 4: The analog input bandwidth is defined as the maximum frequency of a −1-dB FS input sine that can be applied to the device for which
an extra 3-dB attenuation is observed in the reconstructed output signal.
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electrical characteristics over recommended operating conditions, fCLK = 35 MSPS, external
voltage references (unless otherwise noted) (continued)
timing requirements
PARAMETER
TEST CONDITIONS
Maximum conversion rate
fCLK
MIN
TYP
td(o)
th(o)
Output delay time (see Figure 1)
CL = 10 pF,
See Notes 5 and 6
Output hold time
CL = 2 pF,
See Note 5
td(pipe)
Pipeline delay time (latency)
See Note 6
td(a)
tj(a)
Aperture delay time
tdis
ten
Disable time, OE rising to Hi-Z
10
kHz
9
ns
2
4.5
ns
4.5
4.5
3
See Note 5
Enable time, OE falling to valid data
UNIT
MHz
Minimum conversion rate
Aperture jitter
MAX
35
CLK
cycles
ns
1.5
ps, rms
5
8
ns
5
8
ns
NOTES: 5. Output timing td(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital
output load is not higher than 10 pF.
Output hold time th(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The
digital output is load is not less than 2 pF.
Aperture delay td(A) is measured from the 1.5 V level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing tdis is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The digital output load is
not higher than 10 pF.
OE timing ten is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max) output
levels. The digital output load is not higher than 10 pF.
6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to
know when data is stable on the output pins, the output delay time td(o) (i.e., the delay time through the digital output buffers) needs
to be added to the pipeline latency. Note that since the max td(o) is more than 1/2 clock period at 35 MHz, data cannot be reliably
clocked in on a rising edge of CLK at this speed. The falling edge should be used.
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PARAMETER MEASUREMENT INFORMATION
N+3
N
N+1
N+2
tj(a)
N+5
N+4
td(a)
VIL
(max)
VIH
(min)
CLK
1.5 V
1.5 V
tw(CLKH)
1/fCLK
tw(CLKL)
td(o)
th(o)
D0−D7
N−4
N−3
N−2
VOH(min)
N−1
N
90%
N+1
10%
tdis
td(pipe)
VOL(max)
ten
VIH(min)
VIL(max)
OE
Figure 1. Timing Diagram
TYPICAL CHARACTERISTICS
performance plots at 25°C
0.2
DNL − LSB
0.1
0.0
−0.1
−0.2
0
50
100
150
200
250
ADC Code
Figure 2. DNL vs Input Code at 35 MSPS (with external reference, PW Package)
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TYPICAL CHARACTERISTICS
performance plots at 25°C (continued)
0.4
0.3
INL − LSB
0.2
0.1
−0.0
−0.1
−0.2
−0.3
−0.4
0
50
100
150
200
250
ADC Code
Figure 3. INL vs Input Code at 35 MSPS (with external reference, PW package)
50
45
40
SNRD − dB
35
30
25
20
15
10
5
0
0
10
20
30
40
50
Analog Input Frequency − MHz
Figure 4. SNRD vs fin at 35 MSPS (external reference)
10
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TYPICAL CHARACTERISTICS
performance plots at 25°C (continued)
8
7
6
ENOB
5
4
3
2
1
0
0
10
20
30
40
50
Analog Input Frequency − MHz
Power − dBFS
Figure 5. ENOB vs FIN, 35 MSPS (external reference)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
5
10
15
f − Frequency − MHz
Figure 6. Spectral Plot fin = 1.0 MHz at 35 MSPS
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TYPICAL CHARACTERISTICS
Power − dB
performance plots at 25°C (continued)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
5
10
15
f − Frequency − MHz
Power − dB
Figure 7. Spectral Plot fin = 4.2 MHz at 35 MSPS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
5
10
f − Frequency − MHz
Figure 8. Spectral Plot fin = 15.527 MHz at 35 MSPS
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15
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TYPICAL CHARACTERISTICS
performance plots at 25°C (continued)
120
2.5
100
Supply Current − mA
2.0
60
40
1.5
1.0
0.5
20
0
0.0
0
10
20
30
40
50
0
10
Input Clock Frequency − MHz
Figure 9. Power vs fCLK
at fin = 1 MHz, −1-dB FS
20
30
40
Input Frequency − MHz
50
Figure 10. DRVDD Supply Current vs fCLK
at fin = 1 MHz, −1-dB FS
0
−1
−2
Fundamental − dB
Power − mV
80
−3
−4
−5
−6
−7
1
10
100
1000
Input Frequency − MHz
Figure 11. ADC Output Power With Respect to −1-dB FS VIN
(internal reference, PW package)
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PRINCIPLES OF OPERATION
The TLV5535 implements a high-speed 35 MSPS converter in a cost-effective CMOS process. Powered from
3.3 V, the single-pipeline design architecture ensures low-power operation and 8-bit accuracy. Signal input and
clock signals are all single-ended. The digital inputs are 3.3-V TTL / CMOS compatible. Internal voltage
references are included for both bottom and top voltages. Therefore the converter forms a self-contained
solution. Alternatively, the user may apply externally generated reference voltages. In doing so, both input offset
and input range can be modified to suit the application.
A high-speed sampling-and-hold captures the analog input signal. Multiple stages generate the output code with
a pipeline delay of 4.5 CLK cycles. Correction logic combines the multistage data and aligns the 8-bit output
word. All digital logic operates at the rising edge of CLK.
analog input
A first-order approximation for the equivalent analog input circuit of the TLV5535 is shown in Figure 12. The
equivalent input capacitance CI is 4 pF typical. The input must charge/discharge this capacitance within the
sample period of one half clock cycle. When a full-scale voltage step is applied, the input source provides the
charging current through the switch resistance RSW (200 Ω) of S1 and quickly settles. In this case, the input
impedance is low. Alternatively, when the source voltage equals the value previously stored on CI, the hold
capacitor requires no input current and the equivalent input impedance is very high.
To maintain the frequency performance outlined in the specifications, the total source impedance should be
limited to about 80 Ω, as follows from the equation with fCLK = 35 MHz, CI = 4 pF, RSW = 200 Ω:
R
14
S
ƪ ǒ
t 1 ÷ 2f
CLK
C
I
Ǔ
In(256) –R
ƫ
SW
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PRINCIPLE OF OPERATION
analog input (continued)
So, for applications running at a lower fCLK, the total source resistance will increase proportionally.
TLV5535
RS
S1
AIN
RSW
VS
CI
Figure 12. Simplified Equivalent Input Circuit
dc coupled input
For dc-coupled systems an op amp can level-shift a ground-referenced input signal. A circuit as shown in
Figure 13(a) is acceptable. Alternatively, the user might want a bipolar shift together with the bottom reference
voltage as seen in Figure 13(b). In this case the AIN voltage is given by:
ǒ
AIN + 2
R2 ÷ R ) R2
1
Ǔ
V
REF
–V
IN
REFTI
REFTI
RIN
REFTO
VIN
TLV5535
+
_
AIN
AVDD
VIN
RIN
VREF
REFBI
REFTO
_
TLV5535
AIN
+
R1
REFBO
REFBI
REFBO
R2
(b)
(a)
Figure 13. DC-Coupled Input Circuit
ac coupled input
For many applications, especially in single supply operation, ac coupling offers a convenient way for biasing
the analog input signal at the proper signal range. Figure 14 shows a typical configuration. To maintain the
outlined specifications, the component values need to be carefully selected. The most important issue is the
positioning of the 3-dB high-pass corner point f−3 dB, which is a function of R2 and the parallel combination of
C1 and C2, called Ceq. This is given by the following equation:
f
–3 dB
ǒ
Ǔ
+ 1 ÷ 2π x R 2 x C eq
where Ceq is the parallel combination of C1 and C2.
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Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher
frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01 µF, which is not
inductive within the frequency range of interest, maintains low impedance. If the minimum expected input signal
frequency is 20 kHz, and R2 equals 1 kΩ and R1 equals 50 Ω, the parallel capacitance of C1 and C2 must be
a minimum of 8 nF to avoid attenuating signals close to 20 kHz.
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SGLS230A − JANUARY 2004 − REVISED JUNE 2008
PRINCIPLE OF OPERATION
ac coupled input (continued)
C1
TLV5535
R1
VIN
AIN
R2
C2
+
−
VBIAS
Figure 14. AC-Coupled Input Circuit
reference terminals
The voltages on terminals REFBI and REFTI determine the TLV5535 input range. Since the device has an
internal voltage reference generator with outputs available on REFBO and REFTO respectively, corresponding
terminals can be directly connected externally to provide a contained ADC solution. Especially at higher
sampling rates, it is advantageous to have a wider analog input range. The wider analog input range is
achievable by using external voltage references (e.g., at AVDD = 3.3 V, the full-scale range can be extended
from 1 Vpp (internal reference) to 1.3 Vpp (external reference) as shown in Table 1). These voltages should not
be derived via a voltage divider from a power supply source. Instead, a bandgap-derived voltage reference
should be used to derive both references via an op amp circuit. Refer to the schematic of the TLV5535 evaluation
module for an example circuit.
When using external references, the full-scale ADC input range and its dc position can be adjusted. The
full-scale ADC range is always equal to VREFT – VREFB. The maximum full-scale range is dependent on AVDD
as shown in the specification section. In addition to the limitation on their difference, VREFT and VREFB each also
have limits on their useful range. These limits are also dependent on AVDD.
Table 1 summarizes these limits for 3 cases.
Table 1. Recommended Operating Modes
AVDD
3V
VREFB(min)
0.8 V
VREFB(max)
1.2 V
VREFT(min)
1.8 V
VREFT(max)
2.2 V
(VREFT−VREFB)max
1V
3.3 V
0.8 V
1.2 V
2.1 V
2.5 V
1.3 V
3.6 V
0.8 V
1.2 V
2.4 V
2.8 V
1.6 V
digital inputs
The digital inputs are CLK, STDBY, PWDN_REF, and OE. All of these signals, except CLK, have an internal
pulldown resistor to connect to digital ground. This provides a default active operation mode using internal
references when left unconnected.
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PRINCIPLE OF OPERATION
digital inputs (continued)
The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be
minimized by proper termination of the signal close to the TLV5535. An important cause of performance
degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the
ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by
its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2N) of a signal
that needs to be sampled and the maximum amount of aperture error dtmax that is tolerable. The following
formula shows the relation:
ƪ
dt max + 1 B p f 2 ǒN)1Ǔ
ƫ
As an example, for an 8-bit converter with a 15-MHz input, the jitter needs to be kept < 41 pF in order not to have
changes in the LSB of the ADC output due to the total aperture error.
digital outputs
The output of the TLV5535 is standard binary code. Capacitive loading on the output should be kept as low as
possible (a maximum loading of 10 pF is recommended) to provide the best performance. Higher output loading
causes higher dynamic output currents and can increase noise coupling into the analog front end of the device.
To drive higher loads, the use of an output buffer is recommended.
When clocking output data from the TLV5535, it is important to observe its timing relation to CLK. The pipeline
ADC delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the
specification section for more details.
layout, decoupling and grounding rules
It is necessary for any PCB using the TLV5535 to have proper grounding and layout to achieve the stated
performance. Separate analog and digital ground planes that are spliced underneath the device are advisable.
The TLV5535 has digital and analog terminals on opposite sides of the package to make proper grounding
easier. Since there is no internal connection between the analog and digital grounds, they have to be joined on
the PCB. Joining the digital and analog grounds at a point in close proximity to the TLV5535 is advised.
As for power supplies, separate analog and digital supply terminals are provided on the device (AVDD/DVDD).
The supply to the digital output drivers is kept separate also (DRVDD). Lowering the voltage on this supply from
the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output
buffers.
Due to the high sampling rate and switched-capacitor architecture, the TLV5535 generates transients on the
supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic
of the TLV5535 EVM is recommended.
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TLV5535 EVALUATION MODULE
TLV5535 evaluation module
TI provides an evaluation module (EVM) for TLV5535. The EVM also includes a 10b 80 MSPS DAC so that the
user can convert the digitized signal back to the analog domain for functional testing. Performance
measurements can be done by capturing the ADC’s output data.
The EVM provides the following additional features:
D Provision of footprint for the connection of an onboard crystal oscillator, instead of using an external clock
input.
D Use of TLV5535 internal or external voltage references. In the case of external references, an onboard
circuit is used that derives adjustable bottom and top reference voltages from a bandgap reference. Two
potentiometers allow for the independent adjustments of both references. The full scale ADC range can be
adjusted to the input signal amplitude.
D All digital output, control signal I/O (output enable, standby, reference powerdown) and clock I/O are
provided on a single connector. The EVM can thus be part of a larger (DSP) system for prototyping.
D Onboard prototyping area with analog and digital supply and ground connections.
Figure 15 shows the EVM schematic.
The EVM is factory shipped for use in the following configuration:
D Use of external (onboard) voltage references
D External clock input
analog input
A signal in the range between V(REFBI) and V(REFTI) should be applied to avoid overflow/underflow on connector
J10. This signal is onboard terminated with 50Ω. There is no onboard biasing of the signal. When using external
(onboard) references, these levels can be adjusted with R7 (V(REFTI)) and R6 (V(REFBI)). Adjusting R7 causes
both references to shift. R6 only impacts the bottom reference. The range of these signals for which the device
is specified depends on AVDD and is shown in the Recommended Operating Conditions.
Internally generated reference levels are also dependent on AVDD as shown in the electrical characteristics
section.
clock input
A clock signal should be applied with amplitudes ranging from 0 to AVDD with a frequency equal to the desired
sampling frequency on connector J9. This signal is onboard terminated with 50 Ω. Both ADC and DAC run off
the same clock signal. Alternatively the clock can be applied from terminal 1 on connector J11. A third option
is using a crystal oscillator. The EVM board provides the footprint for a crystal oscillator that can be populated
by the end-user, depending on the desired frequency. The footprint is compatible with the Epson EG-8002DC
series of programmable high-frequency crystal oscillators. Refer to the TLV5535 EVM Settings for selecting
between the different clock modes.
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TLV5535 EVALUATION MODULE
power supplies
The board provides seven power supply connectors (see Table 2). For optimum performance, analog and digital
supplies should be kept separate. Using separate supplies for the digital logic portion of TLV5535 (DVDD) and
its output drivers (DRVDD) benefits dynamic performance, especially when DRVDD is put at the minimum
required voltage (3 V), while DVDD might be higher (up to 3.6 V). This lowers the switching noise on the die
caused by the output drivers.
Table 2. Power Supplies
SIGNAL
NAME
CONNECTOR
BOARD
LABEL
DRV3
J1
3DRV
DV3
J2
3VD
3.3 V digital supply for TLV5535 (digital logic) and peripherals
DV5
J3
5VD
5 V digital supply for D/A converter and peripherals
AV3
J4
3VA
3.3 V analog supply for TLV5535
AV5
J5
5VA
5 V analog supply for onboard reference circuit and D/A converter. Can be left unconnected if
internal references are used and no D/A conversion is required.
AV+12
J6
12VA
12 V analog supply for onboard reference circuit. Can be left unconnected if internal references
are used.
AV−12
J7
−12VA
−12 V analog supply for onboard reference circuit. Can be left unconnected if internal
references are used.
DESCRIPTION
3.3 V digital supply for TLV5535 (digital output drivers)
voltage references
SW1 and SW2 switch between internal and external top and bottom references respectively. The external
references are onboard generated from a stable bandgap-derived 3.3 V signal (using TI’s TPS7133 and
quad-opamp TLE2144). They can be adjusted via potentiometers R6 (V(REFBI)) and R7 (V(REFTI)). It is advised
to power down the internal voltage references by asserting PWN_REF when onboard references are used.
The references are measured at test points TP3 (V(REFB)) and TP4 (V(REFT)).
DAC output
The onboard DAC is a 10-bit 80 MSPS converter. It is connected back-to-back to the TLV5535. While the user
could use its analog output for measurements, the DAC output is directly connected to connector J8 and does
not pass through an analog reconstruction filter. So mirror spectra from aliased signal components feed through
into the analog output.
For this reason and to separate ADC and DAC contributions, performance measurements should be made by
capturing the ADC output data available on connector J11 and not by evaluating the DAC output.
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TLV5535 EVALUATION MODULE
TLV5535 EVM settings
clock input settings
REFERENCE
DESIGNATOR
FUNCTION
W1
Clock selection switch
1−2 J11: clock from pin1 on J11 connector
2−3 J9: clock from J9 SMA connector
W2
Clock source switch
J XTL: clock from onboard crystal oscillator
j CLK: clock from pin 1 on J11 connector (if W1/1−2) or J9 SMA connector (if W1/2−3)
NOTE: If set to XTL and a XTL oscillator is populated, no clock signal should be applied to J9 or J11, depending on the W1
setting.
W3
Clock output switch
1−2 Rising: clock output on J11 connector is the same phase as the clock to the digital output buffer. Data changes on rising
CLK edge.
2−3 Falling: clock output on J11 connector is the opposite phase as the digital output buffer. Data changes on falling CLK edge.
reference settings
REFERENCE
DESIGNATOR
SW1
FUNCTION
REFT external/internal switch
Jj REFT internal: REFT from TLV5535 internal reference
jJ REFT external: REFT from onboard voltage reference circuit
SW2
REFB external/internal switch
Jj REFB internal: REFB from TLV5535 internal reference
jJ REFB external: REFB from onboard voltage reference circuit
control settings
REFERENCE
DESIGNATOR
FUNCTION
W4
TLV5535 and digital output buffer output enable control (1)
J 5535-574 OE-connected: Connects OEs of TLV5535 and digital output buffer (574 buffer). Use this when no
board-external OE is used. In addition, close W5 to have both OEs permanently enabled.
j 5535-574 OE-disconnected: Disconnects OEs of TLV5535 and digital output buffer (574 buffer). The OE for the output
buffer needs to be pulled low from pin 5 on J11 connector to enable. The OE for TLV5535 is independently controlled from
pin 7 on J11 connector (W5 open) or is permanently enabled if W5 is closed.
W5
TLV5535 and digital output buffer output enable control (2)
J 5535 OE to GND: Connects OEs of TLV5535 to GND. Additionally connects OE of 74ALS574 to GND if W4 is 5535-574
OE-connected.
j 5535 OE external: Enables control of OE of TLV5535 via pin 7 on J11 connector. When taken high (internal pulldown)
the output can be disabled.
W6
TLV5535 STDBY control
J Stdby: STDBY is active (high).
j Active: STDBY is low, via internal pulldown. STDBY can be taken high from pin 9 on J11 connector to enable standby
mode.
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TLV5535 EVALUATION MODULE
control settings (continued)
REFERENCE
DESIGNATOR
W7
FUNCTION
TLV5535 PWDN REF control
J Pwdn_ref: PWDN_REF is active (high).
j Active: PWDN_REF is low, via internal pulldown. PWDN_REF can be taken high from pin 10 on J11 connector to enable
pwdn_ref mode.
W8
DAC enable
J Active: D/A on
j Standby: D/A off
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POST OFFICE BOX 655303
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J9
R48
R47
R46
R45
R44
R43
R42
R41
CLOCK IN
DV5
DV5
DAC_OUT
J8
TP1
1
R28 3
49.9
2
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
C30
.1 µ F
TP2
2
1
10
9
13
8
3
SN74ALVC00
U2A
SN74ALVC00
U2C
SN74ALVC00
11
GND
OUT
U2D
VCC
OE
X1
12
W2
DV5
W1
0
AVSS
NC
DVSS
DVDD
NC
D0
D1
D2
R24
20
25
26
27
28
29
30
31
32
R2
200
24
23
22
21
20
19
18
3.24 kΩ
U3
11
CE
16
NC
15
DVSS
14
VB
13
DVDD
12
NC
10
BLK 9
CLK
R4
.1 µ F
C26
17
W3
5
6
19
18
17
16
15
14
13
12
CLK_OUT
J11
CLK_IN
20
R37
R14
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
DV3
DGND
W8
1
11
2
3
4
5
6
7
8
9
R11
10 kΩ
10 SN74LVT574DW
1D
2D
3D
4D
5D
6D
7D
8D
OC
CLK
.1 µ F U5
C41
C28
.1 µ F
20
DV3
DV5
DV5
C29
.1 µ F
10 kΩ
SN74ALVC00
20
U2B
4
R17
20
R29
20
R13
C24
.1 µ F
DV5
CXD2306Q
IREF
IO
IO
VG
AVDD
AVDD
VREF
SREF
D3
D4
D5
D6
D7
D8
D9
8
NC
1
2
3
4
5
6
7
R25
R23
R22
R21
R20
R19
R18
20
20
20
20
20
20
20
R3
C25
.1 µ F
R40
W5
DV3
20
20
20
20
20
20
20
20
10 kΩ
W4
R39
R38
R36
R35
R33
R32
R31
R30
DV5
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
REFBO
EXT_REFB
AV3
C36
.01 µ F
1 kΩ
R8
.1 µ F
C39
R5
C42
.1 µ F
C38
10 µ F
+
TP3
.1 µ F
C40
R12
C43
1 kΩ
1
C31
.1 µ F
SW1
R27 EXT_REFT
10
TLE2144CDW
REFTO
EXT_REFT
C44
10 µ F
+
10
R26 EXT_REFB
U4D
4OUT
16
1 kΩ
R16
C32
.1 µ F
2OUT
7
C23
10 µ F
REF3V
+
U4B
TLE2144CDW
−
2IN 5 +
7
5
6
8
2IN 6
TPS7133QD
−
4IN 14 +
4IN 15
OUT
OUT
PG
GND SENSE
EN
IN
IN
U1
U4A
1OUT
1
AV −12
13
−
1IIN 3 +
C37
.1 µ F .01 µ F
TP4
U4C
3OUT
10
1 kΩ
R10
R15
4
2
3
4
R1
10 kΩ
1 kΩ
AV +12
C27
.1 µ F
1IN 2
C22
10 µ F
+
R9
1 kΩ
R6 5 kΩ
REFTI
REFBI
−
3IN 12 +
AV5
R34
49.9
2.1 k Ω
W7
J10
3IN 11
REF3V
R7 1 kΩ
SW2
C33
.1 µ F
C34
.1 µ F
ANALOG IN
C46
.1 µ F
AV3
W6
Q(0−7)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REF3V
DV3
DRVDD
AVSS
D0
AVDD
D1
AIN
D2
CML
D3
PWDN_REF
D4
AVSS
D5
REFBO
D6
REFBI
D7
REFTI
DRVSS
REFTO
DVSS
AVSS
CLK
BG
OE
AVDD
DVDD
STDBY
.1 µ F
C45
TLV5535PW
C35
.1 µ F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U6
DRV3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AV5
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
Figure 15. EVM Schematic
23
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TLV5535 EVALUATION MODULE
Digital +5 V
Analog +12 V
J6
J3
L6
1
C11
2 1 µF
4.7 µH
C12
10 µF
+
AV +12 V
+
C5
2 1 µF
C20
10 µF
J2
L7
1
2
AV −12 V
C13
1 µF
4.7 µH
C14
C21
+ 10 µF
+ 10 µF
Analog +5 V
J5
L5
4.7 µH
C10
10 µF
+
C3
2 1 µF
J1
AV5
+
C19
10 µF
C1
2 1 µF
4.7 µH
C8
10 µF
+
AV3
+
C18
10 µF
Figure 15. EVM Schematic (continued)
24
4.7 µH
C4
10 µF
+
DV3
+
C16
10 µF
POST OFFICE BOX 655303
L1
1
L4
1
C7
2 1 µF
C17
10 µF
L2
1
Analog +3.3 V
J4
DV5
+
Digital +3.3 V (DRVDD)
1
C9
2 1 µF
4.7 µH
C6
10 µF
+
Digital +3.3 V (DVDD)
Analog −12 V
J7
L3
1
• DALLAS, TEXAS 75265
4.7 µH
C2
10 µF
+
DRV3
+
C15
10 µF
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TLV5535 EVALUATION MODULE
Figure 16. EVM Board Layout, Top Overlay
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25
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TLV5535 EVALUATION MODULE
Figure 17. EVM Board Layout, Top Layer
26
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SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TLV5535 EVALUATION MODULE
Figure 18. EVM Board Layout, Internal Plane 1
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SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TLV5535 EVALUATION MODULE
Figure 19. EVM Board Layout, Internal Plane 2
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
3350 (mil)
TLV5535 EVALUATION MODULE
4200 (mil)
Figure 20. EVM Board Layout, Drill Drawing for Through Hole
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SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TLV5535 EVALUATION MODULE
Figure 21. EVM Board Layout, Bottom Layer
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TLV5535 EVALUATION MODULE
Table 3. TLV5535EVM Bill of Material
QTY.
REFERENCE DESIGNATOR
VALUE
SIZE
DESCRIPTION
MANUFACTURER/
PART NUMBER†
7
C1, C11, C13, C3, C5, C7, C9
1 µF
1206
ceramic multilayer capacitor
Any
18
C10, C12, C14, C15, C16,
C17, C18, C19, C2, C20, C21,
C22, C23, C4, C6, C8, C38,
C44
10 µF
3216
16 V, 10 µF, tantalum capacitor
Any
2
C36, C43
0.01 µF
805
Ceramic multilayer
Any
19
C24, C25, C26, C27, C28,
C29, C30, C31, C32, C33,
C34, C35, C37, C39, C40,
C41, C42, C45, C46
0.1 µF
805
Ceramic multilayer capacitor
Any
7
J1, J2, J3, J4, J5, J6, J7
2 terminal screw connector
Lumberg
KRMZ2
3
J10, J8, J9
PCM mount, SMA Jack
Johnson Components
142-0701-206
1
J11
IDC26
13I × 2.025I square pin header
Samtec
TSW-113-07-L-D
7
L1, L2, L3, L4, L5, L6, L7
4.7 µH
4.7 µH DO1608C-472-Coil Craft
Coil Craft
DO1608-472
1
R2
2
R26, R27
12
R1, R11, R14, R40, R41, R42,
R43, R44, R45, R46, R47, R48
6
R10, R12, R15, R16, R8, R9
1
R5
20
R13, R17, R18, R19, R20,
R21, R22, R23, R24, R25,
R29, R30, R31, R32, R33,
R35, R36, R37, R38, R39
1
1
2
Screw Con
SMA
0
1206
Chip resistor
Any
10
1206
Chip resistor
Any
10 K
1206
Chip resistor
Any
1K
1206
Chip resistor
Any
2.1 K
1206
Chip resistor
Any
20
1206
Chip resistor
Any
R3
200
1206
Chip resistor
Any
R4
3.24 K
1206
Chip resistor
Any
R28, R34
49.9
1206
Chip resistor
Any
1
R6
5K
4 mm SM pot-top adjust
Bourns
3214W-5K
1
R7
1K
4 mm SM pot-top adjust
Bourns
3214W-1K
2
SW1, SW2
SPDT
C&K tiny series−slide switch
C&K
TS01CLE
4
TP1, TP2, TP3, TP4
TP
Test point, single 0.025I pin
Samtec
TSW-101-07-L-S
or equivalent
1
U3
CXD2306Q
1
U2
SN74ALVC00D
14-SOIC (D)
1
U5
SN74LVT574DW
20-SOP (DW)
Sony
CXD2306Q
Quad 2-input positive NAND
Texas Instruments
SN74ALVC00D
Texas Instruments
SN74LVT574DW
† Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.
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• DALLAS, TEXAS 75265
31
SGLS230A − JANUARY 2004 − REVISED JUNE 2008
TLV5535 EVALUATION MODULE
Table 3. TLV5535EVM Bill of Material (Continued)
QTY.
REFERENCE DESIGNATOR
VALUE
SIZE
1
U4
TLE2144CDW
16-SOP(D)
1
U6
TLV5535PW
28-TSSOP (PW)
1
U1
TPS7133
8-SOP(D)
6
W2, W4, W5, W6, W7, W8
2
W1, W3
1
X1
DESCRIPTION
Quad op amp
Texas Instruments
TLE2144CDW/
TLE2144IDW
Texas Instruments
TLV5535PW
Low-dropout voltage regulator
Texas Instruments
TPS7133QD
SPST
2 position jumper, 0.1I spacing
Samtec
TSW-102-07-L-S
or equivalent
DPFT
3 position jumper, 0.1I spacing
Samtec
TSW-103-07-L-S
or equivalent
Crystal oscillator
Epson
SG-8002DC series
NA
† Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.
32
MANUFACTURER/
PART NUMBER†
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
2000
TLV5535IPWRG4Q1
ACTIVE
TSSOP
PW
28
TLV5535IPWRQ1
ACTIVE
TSSOP
PW
28
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
TBD
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-1-260C-UNLIM
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV5535-Q1 :
• Catalog: TLV5535
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
• Catalog - TI's standard catalog product
Addendum-Page 2
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