TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 D D D D D D D D D D D D 8-Bit Resolution 80 MSPS Sampling Analog-to-Digital Converter (ADC) Low Power Consumption: 165 mW Typ Using External references Wide Analog Input Bandwidth: 700 MHz Typ 3.3 V Single-Supply Operation 3.3 V TTL /CMOS-Compatible Digital I/O Internal Bottom and Top Reference Voltages Adjustable Reference Input Range Power Down (Standby) Mode Separate Power Down for Internal Voltage References Three-State Outputs 28-Pin Small Outline IC (SOIC) and Thin Shrink SOP (TSSOP) Packages Applications – Digital Communications (IF Sampling) – Flat Panel Displays – High-Speed DSP Front-End (TMS320C6000) – Medical Imaging – Graphics Processing (Scan Rate/Format Conversion) – DVD Read Channel Digitization DW OR PW PACKAGE (TOP VIEW) DRVDD D0 D1 D2 D3 D4 D5 D6 D7 DRVSS DVSS CLK OE DVDD 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 AVSS AVDD AIN CML PWDN_REF AVSS REFBO REFBI REFTI REFTO AVSS BG AVDD STBY description The TLV5580 is an 8-bit 80 MSPS high-speed A/D converter. It converts the analog input signal into 8-bit binary-coded digital words up to a sampling rate of 80 MHz. All digital inputs and outputs are 3.3 V TTL /CMOS-compatible. The device consumes very little power due to the 3.3 V supply and an innovative single-pipeline architecture implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage references from user-supplied voltages. If no external references are available, on-chip references are available for internal and external use. The full-scale range is 1 Vpp up to 1.6 Vpp, depending on the analog supply voltage. If external references are available, the internal references can be disabled independently from the rest of the chip, resulting in an even greater power saving. While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD read channel digitization, medical imaging and communications. This device is suitable for IF sampling of communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 AVAILABLE OPTIONS PACKAGED DEVICES TA SOIC-28 TSSOP-28 0°C to 70°C TLV5580CDW TLV5580CPW – 40°C to 85°C TLV5580IDW TLV5580IPW functional block diagram + ADC – SHA SHA ADC SHA SHA SHA SHA 2 DAC 2 2 2 2 2 2 Correction Logic Output Buffers D0(LSB)–D7(MSB) The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction logic guarantees no missing codes over the full operating temperature range. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 circuit diagrams of inputs and outputs ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT DVDD AVDD 0.5 pF REFERENCE INPUT CIRCUIT AVDD Internal Reference Generator REFTO or REFBO D0–D7 OUTPUT CIRCUIT DRVDD D AVDD D_Out OE REFBI or REFTI DRVSS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 Terminal Functions TERMINAL NAME AIN AVDD AVSS 4 NO. I/O DESCRIPTION 26 I Analog input 16, 27 I Analog supply voltage 18, 23, 28 I Analog ground BG 17 O Band gap reference voltage. A 1 µF capacitor (with an optional 0.1 µF capacitor in parallel) should be connected between this terminal and AVSS for external filtering. CLK 12 I Clock input. The input is sampled on each rising edge of CLK. CML 25 O Common mode level. This voltage is equal to (AVDD – AVSS) ÷ 2. An external 0.1 µF capacitor should be connected between this terminal and AVSS. D0 – D7 2–9 O Data outputs. D7 is the MSB DRVDD 1 I Supply voltage for digital output drivers DRVSS 10 I Ground for digital output drivers DVDD 14 I Digital supply voltage OE 13 I Output enable. When high the D0 – D7 outputs go in high-impedance mode. DVSS 11 I Digital ground PWDN_REF 24 I Power down for internal reference voltages. A high on this terminal will disable the internal reference circuit. REFBI 21 I Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering should be applied to this input. The use a 0.1 µF capacitor connected between REFBI and AVSS is recommended. Additionaly, a 0.1 µF capacitor can be connected between REFTI and REFBI. REFBO 22 O Reference voltage bottom output. An internally generated reference is available at this terminal. It can be connected to REFBI or left unconnected. A 1 µF capacitor between REFBO and AVSS will provide sufficient decoupling required for this output. REFTI 20 I Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC. It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be applied to this input. The use of a 0.1 µF capacitor between REFTI and AVSS is recommended. Additionaly, a 0.1 µF capacitor can be connected between REFTI and REFBI. REFTO 19 O Reference voltage top output. An internally generated reference is available at this terminal. It can be connected to REFTI or left unconnected. A 1 µF capacitor between REFTO and AVSS will provide sufficient decoupling required for this output. STBY 15 I Standby input. A high level on this input enables a powerdown mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.5 V Supply voltage: AVDD to DVDD, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 0.5 V Digital input voltage range to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to DVDD + 0.5 V Analog input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to AVDD + 0.5 V Digital output voltage applied from external source to DGND . . . . . . . . . . . . . . . . . . . – 0.5 V to DVDD + 0.5 V Reference voltage input range to AGND: V(REFTI), V(REFTO), V(REFBI), V(REFBO) – 0.5 V to AVDD + 0.5 V Operating free-air temperature range, TA: TLV5580C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5580I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions over operating free-temperature range power supply AVDD DVDD Supply voltage MIN NOM MAX 3 3.3 3.6 UNIT V DRVDD analog and reference inputs Reference input voltage (top), V(REFTI) Reference input voltage (bottom), V(REFBI) MIN NOM MAX UNIT (NOM) – 0.2 2 + (AVDD – 3) (NOM) + 0.2 V 0.8 1 Reference voltage differential, V(REFTI) – V(REFBI) Analog input voltage, V(AIN) 1.2 V 1 + (AVDD – 3) V V(REFTI) V V(REFBI) digital inputs MIN High-level input voltage, VIH 2.0 Low-level input voltage, VIL DGND NOM MAX UNIT DVDD V 0.2xDVDD V Clock period, tc 12.5 ns Pulse duration, clock high, tw(CLKH) 5.25 ns Pulse duration, clock low, tw(CLKL) 5.25 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of external voltage references (unless otherwise noted) power supply PARAMETER IDD Operating supply current PD Power dissipation PD(STBY) Standby power TEST CONDITIONS AVDD DVDD DRVDD MIN TYP MAX 57 71 3 3.6 5 7.5 PWDN_REF = L 213 270 PWDN_REF = H 165 210 11 15 TYP MAX AVDD = DVDD = 3 3.3 3V V, DRVDD = 3 V, V CL = 15 pF F, VI = 1 MHz, MHz –1 dBFS STBY = H, CLK held high or low UNIT mA mW digital logic inputs IIH PARAMETER High-level input current on CLK† IIL Low-level input current on digital inputs (OE, STDBY, PWDN_REF, CLK) TEST CONDITIONS MIN AVDD = DVDD = DRVDD = CLK = 3.6 V AVDD = DVDD = DRVDD = 3.6 V, Digital inputs at 0 V UNIT 10 µA 10 µA CI Input capacitance 5 pF † IIH leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of 4 KΩ to DGND. logic outputs PARAMETER TEST CONDITIONS VOH High-level output voltage AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA, Digital output forced high VOL Low-level output voltage AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA, Digital output forced low CO Output capacitance IOZH High-impedance state output current to high level IOZL 6 MIN TYP MAX 2.8 V 0.1 5 High-impedance state output current to low level UNIT V pF 10 µA 10 µA 6V AVDD = DVDD = DRVDD = 3 3.6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of external voltage references (unless otherwise noted) dc accuracy PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Integral nonlinearity (INL), (INL) best-fit best fit Internal references (see Note 1) TA = 25°C TA = –40°C to 85°C –2 ±1 2 LSB –2.4 ±1 2.4 LSB Differential nonlinearity (DNL) Internal references (see Note 2), TA = –40°C to 85°C –1 ± 0.6 1.3 LSB AVDD = DVDD = 3 3.3 3V V, DRVDD = 3 V See Note 3 5 %FS 5 %FS Zero error Full scale error NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. 2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no missing codes. 3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). analog input PARAMETER CI TEST CONDITIONS MIN Input capacitance TYP MAX 4 UNIT pF reference input (AVDD = DVDD = DRVDD = 3.6 V) PARAMETER Rref Reference input resistance Iref Reference input current TEST CONDITIONS MIN TYP MAX UNIT Ω 200 5 mA reference outputs PARAMETER V(REFTO) V(REFBO) Reference top offset voltage Reference bottom offset voltage TEST CONDITIONS MIN TYP MAX UNIT Absolute min/max values valid and tested for AVDD = 3.3 V 2.07 2 + [(AVDD – 3) ÷ 2] 2.21 V 1.09 1 + [(AVDD – 3) ÷ 2] 1.21 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of external voltage references (unless otherwise noted) (continued) dynamic performance† PARAMETER TEST CONDITIONS fin = 1 MHz fin = 4.43 MHz Effective number of bits bits, ENOB Spurious free dynamic range (SFDR) TYP 6.6 7.0 6.6 7.0 fin = 15 MHz fin = 76 MHz Signal to total harmonic distortion + noise, Signal-to-total noise S/(THD+N) Total harmonic distortion (THD) MIN fin = 1 MHz fin = 4.43 MHz 6.5 43.5 41.5 43.5 41 Bits dB 41.5 –46 –50 –45.5 –49 fin = 15 MHz fin = 76 MHz fin = 1 MHz fin = 4.43 MHz UNIT 6.6 41.5 fin = 15 MHz fin = 76 MHz fin = 1 MHz fin = 4.43 MHz MAX –44 dB –45.5 48 53 48 53 dB fin = 15 MHz fin = 76 MHz 46.5 Analog input full-power bandwidth, BW See Note 4 700 MHz phase DP Differential phase, MH fin = 4.43 4 43 MHz, MH fclk = 40 MHz, 20 IRE amplitude am litude vs. full-scale full scale of 140 IRE 08 0.8 ° 06 0.6 % gain DG Differential gain, 48.5 † Based on analog input voltage of – 1 dBFS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at fclk = 80 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3.0 V at 25°C. NOTE 4: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which an extra 3 dB attenuation is observed in the reconstructed output signal. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of external voltage references (unless otherwise noted) (continued) timing requirements PARAMETER TEST CONDITIONS MIN fclk fclk Maximum conversion rate td(o) th(o) Output delay time (see Figure 1) CL = 10 pF, See Notes 5 and 6 Output hold time CL = 2 pF, See Note 5 TYP MAX UNIT 80 MHz Minimum conversion rate td(pipe) Pipeline delay (latency) td(a) tj(a) Aperture delay time tdis ten Disable time, OE rising to Hi-Z 10 kHz 9 ns 2 See Note 6 ns 4.5 4.5 4.5 CLK cycles 3 Aperture jitter ns 1.5 See Note 5 Enable, OE falling to valid data ps, rms 5 8 ns 5 8 ns NOTES: 5. Output timing td(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital output load is not higher than 10 pF. Output hold time th(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital output is load is not less than 2 pF. Aperture delay td(A) is measured from the 1.5 V level of the CLK input to the actual sampling instant. The OE signal is asynchronous. OE timing tdis is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The digital output load is not higher than 10 pF. OE timing ten is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max) output levels. The digital output load is not higher than 10 pF. 6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to know when data is stable on the output pins, the output delay time td(o) (i.e., the delay time through the digital output buffers) needs to be added to the pipeline latency. Note that since the max. td(o) is more than 1/2 clock period at 80 MHz; data cannot be reliably clocked in on a rising edge of CLK at this speed. The falling edge should be used. N+3 N N+1 N+2 tj(A) N+5 N+4 td(A) CLK VIH (min) tw(CLKH) tw(CLKL) VIL (max) 1.5 V 1.5 V 1/fCLK td(o) th(o) D0–D7 N–4 N–3 N–2 VOH(min) N–1 N 90% N+1 10% tdis td(pipe) VOL(max) ten VIH(min) VIL(max) OE Figure 1. Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 performance plots at 25°C 1 0.8 DNL – LSB 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 50 100 150 200 250 ADC Code Figure 2. DNL vs Input Code At 80 MSPS (With External Reference, PW Package) 2 1.5 INL – LSB 1 0.5 0 –0.5 –1 –1.5 –2 0 50 100 150 200 250 ADC Code Figure 3. INL vs Input Code At 80 MSPS (With External Reference, PW Package) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 performance plots at 25°C (continued) 50 45 40 60 MSPS 40 MSPS S(THD+N) – dB 35 80 MSPS 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 Analog Input Frequency – MHz Figure 4. S/(THD+N) vs VIN At 80 MSPS (Internal Reference), 60 MSPS (External Reference), 40 MSPS (External Reference) 0 –10 Power – dBFS –20 –30 –40 –50 –60 –70 –80 –90 0 5 10 15 20 25 30 f – Frequency – MHz Figure 5. Spectral Plot fIN = 1.011 MHz At 60 MSPS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 performance plots at 25°C (continued) 0 –10 Power – dBFS –20 –30 –40 –50 –60 –70 –80 –90 0 5 10 15 20 25 30 35 40 f – Frequency – MHz Figure 6. Spectral Plot fIN = 0.996 MHz At 80MSPS 0 Power – dBFS –10 –20 –30 –40 –50 –60 –70 –80 –90 0 5 10 15 20 25 30 35 40 35 40 f – Frequency – MHz Figure 7. Spectral Plot fIN = 15.527 MHz At 80 MSPS 0 –10 Power – dBFS –20 –30 –40 –50 –60 –70 –80 –90 0 5 10 15 20 25 30 f – Frequency – MHz Figure 8. Spectral Plot fIN = 75.02 MHz At 80MSPS (Plot shows folded spectrum of undersampled input signal) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 performance plots at 25°C (continued) 250 5 4.5 200 4 IDRVDD – mA 150 100 3 2.5 2 1.5 50 1 0.5 0 0 10 20 30 40 50 60 70 80 0 90 100 0 10 Sampling Frequency – MHz 20 30 40 50 60 70 80 90 100 Sampling Frequency – MHz Figure 9. Power vs fCLK At VIN = 1 MHz, –1 dBFS Figure 10. IDRVDD vs fCLK At VIN = 1 MHz, –1 dBFS 0 –1 Fundamental Power – dBFS Power – mW 3.5 –2 –3 –4 –5 –6 –7 –8 –9 –10 106 107 108 109 Analog Input Frequency – Hz Figure 11. ADC Output Power With Respect To –1 dBFS VIN (Internal Reference, DW Package) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 PRINCIPLE OF OPERATION The TLV5580 implements a high-speed 80 Msps converter in a cost-effective CMOS process. Powered from 3.3 V, the single-pipeline design architecture ensures low-power operation and 8 bit accuracy. Signal input and clock signals are all single-ended. The digital inputs are 3.3 V TTL / CMOS compatible. Internal voltage references are included for both bottom and top voltages. Therefore the converter forms a self-contained solution. Alternatively the user may apply externally generated reference voltages. In doing so, both input offset and input range can be modified to suit the application. A high-speed sampling-and-hold captures the analog input signal. Multiple stages will generate the output code with a pipeline delay of 4.5 CLK cycles. Correction logic combines the multistage data and aligns the 8-bit output word. All digital logic operates at the rising edge of CLK. analog input TLV5580 RS S1 AIN RSW VS CI Figure 12. Simplified Equivalent Input Circuit A first-order approximation for the equivalent analog input circuit of the TLV5580 is shown in Figure 12. The equivalent input capacitance CI is 4 pF typical. The input must charge/discharge this capacitance within the sample period of one half clock cycle. When a full-scale voltage step is applied, the input source provides the charging current through the switch resistance RSW (200 Ω) of S1 and quickly settles. In this case the input impedance is low. Alternatively, when the source voltage equals the value previously stored on CI, the hold capacitor requires no input current and the equivalent input impedance is very high. To maintain the frequency performance outlined in the specifications, the total source impedance should be limited to about 80 Ω, as follows from the equation with fCLK = 80 MHz, CI = 4 pF, RSW = 200 Ω: R S t ƪ ǒ 1 ÷ 2f CLK C I Ǔ ƫ In(256) –R SW So, for applications running at a lower fCLK, the total source resistance can increase proportionally. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 PRINCIPLE OF OPERATION dc coupled input REFTI REFTI RIN REFTO VIN VIN TLV5580 + _ AIN AVDD RIN VREF REFTO _ TLV5580 AIN + R1 REFBI REFBO REFBI REFBO R2 (b) (a) Figure 13. DC-Coupled Input Circuit For dc-coupled systems an opamp can level-shift a ground-referenced input signal. A circuit as shown in Figure 13(a) is acceptable. Alternatively, the user might want a bipolar shift together with the bottom reference voltage as seen in Figure 13(b). In this case the AIN voltage is given by: AIN +2 ǒ R2 ÷ R 1 Ǔ ) R2 V REF – V IN ac coupled input C1 TLV5580 R1 VIN AIN R2 C2 + VBIAS – Figure 14. AC-Coupled Input Circuit For many applications, especially in single supply operation, ac coupling offers a convenient way for biasing the analog input signal at the proper signal range. Figure 14 shows a typical configuration. To maintain the outlined specifications, the component values need to be carefully selected. The most important issue is the positioning of the 3 dB high-pass corner point f– 3 dB, which is a function of R2 and the parallel combination of C1 and C2, called Ceq. This is given by the following equation: f –3 dB +1 ǒ ÷ 2π x R 2 x C eq Ǔ where Ceq is the parallel combination of C1 and C2. Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01 µF, which is not inductive within the frequency range of interest, maintains low impedance. If the minimum expected input signal frequency is 20 kHz, and R2 equals 1 kΩ and R1 equals 50 Ω, the parallel capacitance of C1 and C2 must be a minimum of 8 nF to avoid attenuating signals close to 20 kHz. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 PRINCIPLE OF OPERATION reference terminals The voltages on terminals REFBI and REFTI determine the TLV5580’s input range. Since the device has an internal voltage reference generator with outputs available on REFBO respectively REFTO, corresponding terminals can be directly connected externally to provide a contained ADC solution. Especially at higher sampling rates, it is advantageous to have a wider analog input range. The wider analog input range is achievable by using external voltage references (e.g., at AVDD = 3.3 V, the full scale range can be extended from 1 Vpp (internal reference) to 1.3 Vpp (external reference) as shown in Table 1). These voltages should not be derived via a voltage divider from a power supply source. Instead, use a bandgap-derived voltage reference to derive both references via an opamp circuit. Refer to the schematic of the TLV5580 evaluation module for an example circuit. When using external references, the full-scale ADC input range and its dc position can be adjusted. The full-scale ADC range is always equal to VREFT – VREFB. The maximum full-scale range is dependent on AVDD as shown in the specification section. In addition to the limitation on their difference, VREFT and VREFB each also have limits on their useful range. These limits are also dependent on AVDD. Table 3 summarizes these limits for 3 cases. Table 1. Recommended Operating Modes AVDD 3V VREFB(min) 0.8 V VREFB(max) 1.2 V VREFT(min) 1.8 V VREFT(max) 2.2 V [VREFT–VREFB]max 1V 3.3 V 0.8 V 1.2 V 2.1 V 2.5 V 1.3 V 3.6 V 0.8 V 1.2 V 2.4 V 2.8 V 1.6 V digital inputs The digital inputs are CLK, STDBY, PWDN_REF, and OE. All these signals, except CLK, have an internal pull-down resistor to connect to digital ground. This provides a default active operation mode using internal references when left unconnected. The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be minimized by proper termination of the signal close to the TLV5580. An important cause of performance degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2N) of a signal that needs to be sampled and the maximum amount of aperture error dtmax that is tolerable. The following formula shows the relation: dt max +1B ƪ ǒ )Ǔ p f 2N 1 ƫ As an example, for an 8–bit converter with a 15-MHz input, the jitter needs to be kept <41 pF in order not to have changes in the LSB of the ADC output due to the total aperture error. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 PRINCIPLE OF OPERATION digital outputs The output of TLV5580 is a standard binary code. Capacitive loading on the output should be kept as low as possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading causes higher dynamic output currents and can increase noise coupling into the device’s analog front end. To drive higher loads, use an output buffer is recommended. When clocking output data from TLV5580, it is important to observe its timing relation to CLK. Pipeline ADC delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the specification section for more details. layout, decoupling and grounding rules It is necessary for any PCB using the TLV5580 to have proper grounding and layout to achieve the stated performance. Separate analog and digital ground planes that are spliced underneath the device are advisable. TLV5580 has digital and analog terminals on opposite sides of the package to make proper grounding easier. Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB. Joining the digital and analog grounds at a point in close proximity to the TLV5580 is advised. As for power supplies, separate analog and digital supply terminals are provided on the device (AVDD/DVDD). The supply to the digital output drivers is kept separate also (DRVDD). Lowering the voltage on this supply from the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output buffers. Due to the high sampling rate and switched-capacitor architecture, TLV5580 generates transients on the supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the TLV5580 EVM is recommended. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE TLV5580 evaluation module TI provides an evaluation module (EVM) for TLV5580. The EVM also includes a 10b 80 MSPS DAC so that the user can convert the digitized signal back to the analog domain for functional testing. Performance measurements can be done by capturing the ADC’s output data. The EVM provides the following additional features: D D D D Provision of footprint for the connection of an onboard crystal oscillator, instead of using an external clock input. Use of TLV5580 internal or external voltage references. In the case of external references, an onboard circuit is used that derives adjustable bottom and top reference voltages from a bandgap reference. Two potentiometers allow for the independent adjustments of both references. The full scale ADC range can be adjusted to the input signal amplitude. All digital output, control signal I/O (output enable, standby, reference powerdown) and clock I/O are provided on a single connector. The EVM can thus be part of a larger (DSP) system for prototyping. Onboard prototyping area with analog and digital supply and ground connections. Figure 15 shows the EVM schematic. The EVM is factory shipped for use in the following configuration: D D Use of external (onboard) voltage references External clock input analog input A signal in the range between V(REFBI) and V(REFTI) should be applied to avoid overflow/underflow on connector J10. This signal is onboard terminated with 50Ω. There is no onboard biasing of the signal. When using external (onboard) references, these levels can be adjusted with R7 (V(REFTI)) and R6 (V(REFBI)). Adjusting R7 causes both references to shift. R6 only impacts the bottom reference. The range of these signals for which the device is specified depends on AVDD and is shown under the Recommended Operating Conditions. Internally generated reference levels are also dependent on AVDD as shown in the electrical characteristics section. clock input A clock signal should be applied with amplitudes ranging from 0 to AVDD with a frequency equal to the desired sampling frequency on connector J9. This signal is onboard terminated with 50 Ω. Both ADC and DAC run off the same clock signal. Alternatively the clock can be applied from terminal 1 on connector J11. A third option is using a crystal oscillator. The EVM board provides the footprint for a crystal oscillator that can be populated by the end-user, depending on the desired frequency. The footprint is compatible with the Epson EG-8002DC series of programmable high-frequency crystal oscillators. Refer to the TLV5580 EVM Settings for selecting between the different clock modes. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE power supplies The board provides seven power supply connectors (see Table 2). For optimum performance, analog and digital supplies should be kept separate. Using separate supplies for the digital logic portion of TLV5580 (DVDD) and its output drivers (DRVDD) benefits dynamic performance, especially when DRVDD is put at the minimum required voltage (3 V), while DVDD might be higher (up to 3.6 V). This lowers the switching noise on the die caused by the output drivers. Table 2. Power Supplies SIGNAL NAME CONNECTOR BOARD LABEL DRV3 J1 3DRV DV3 J2 3VD 3.3 V digital supply for TLV5580 (digital logic) and peripherals DV5 J3 5VD 5 V digital supply for D/A converter and peripherals AV3 J4 3VA 3.3 V analog supply for TLV5580 AV5 J5 5VA 5 V analog supply for onboard reference circuit and D/A converter. Can be left unconnected if internal references are used and no D/A conversion is required. AV+12 J6 12VA 12 V analog supply for onboard reference circuit. Can be left unconnected if internal references are used. AV–12 J7 –12VA –12 V analog supply for onboard reference circuit. Can be left unconnected if internal references are used. DESCRIPTION 3.3 V digital supply for TLV5580 (digital output drivers) voltage references SW1 and SW2 switch between internal and external top and bottom references respectively. The external references are onboard generated from a stable bandgap-derived 3.3 V signal (using TI’s TPS7133 and quad-opamp TLE2144). They can be adjusted via potentiometers R6 (V(REFBI)) and R7 (V(REFTI)). It is advised to power down the internal voltage references by asserting PWN_REF when onboard references are used. The references are measured at test points TP3 (V(REFB)) and TP4 (V(REFT)). DAC output The onboard DAC is a 10-bit 80 MSPS converter. It is connected back-to-back to the TLV5580. While the user could use its analog output for measurements, the DAC output is directly connected to connector J8 and does not pass through an analog reconstruction filter. So mirror spectra from aliased signal components feed through into the analog output. For this reason and to separate ADC and DAC contributions, performance measurements should be made by capturing the ADC output data available on connector J11 and not by evaluating the DAC output. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE TLV5580 EVM settings clock input settings REFERENCE DESIGNATOR FUNCTION W1 Clock selection switch 1–2 J11: clock from pin1 on J11 connector 2–3 J9: clock from J9 SMA connector W2 Clock source switch XTL: clock from onboard crystal oscillator J j CLK: clock from pin 1 on J11 connector (if W1/1–2) or J9 SMA connector (if W1/2–3) NOTE: If set to XTL and a XTL oscillator is populated, no clock signal should be applied to J9 or J11, depending on the W1 setting. W3 Clock output switch 1–2 Rising: clock output on J11 connector is the same phase as the clock to the digital output buffer. Data changes on rising CLK edge. 2–3 Falling: clock output on J11 connector is the opposite phase as the digital output buffer. Data changes on falling CLK edge. reference settings REFERENCE DESIGNATOR SW1 SW2 FUNCTION REFT external/internal switch REFT internal: REFT from TLV5580 internal reference Jj jJ REFT external: REFT from onboard voltage reference circuit REFB external/internal switch REFB internal: REFB from TLV5580 internal reference Jj jJ REFB external: REFB from onboard voltage reference circuit control settings REFERENCE DESIGNATOR FUNCTION W4 TLV5580 and digital output buffer output enable control (1) 5580-574 OE-connected: Connects OEs of TLV5580 and digital output buffer (574 buffer). Use this when no board-external OE is used. In addition, close W5 to have both OEs permanently enabled. J j 5580-574 OE-disconnected: Disconnects OEs of TLV5580 and digital output buffer (574 buffer). The OE for the output buffer needs to be pulled low from pin 5 on J11 connector to enable. The OE for TLV5580 is independently controlled from pin 7 on J11 connector (W5 open) or is permanently enabled if W5 is closed. W5 TLV5580 and digital output buffer output enable control (2) 5580 OE to GND: Connects OEs of TLV5580 to GND. Additionally connects OE of 74ALS574 to GND if W4 is 5580-574 OE-connected. J j 5580 OE external: Enables control of OE of TLV5580 via pin 7 on J11 connector. When taken high (internal pulldown) the output can be disabled. W6 TLV5580 STDBY control Stdby: STDBY is active (high). J j Active: STDBY is low, via internal pulldown. STDBY can be taken high from pin 9 on J11 connector to enable standby mode. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE control settings (continued) REFERENCE DESIGNATOR W7 FUNCTION TLV5580 PWDN REF control Pwdn_ref: PWDN_REF is active (high). J j Active: PWDN_REF is low, via internal pulldown. PWDN_REF can be taken high from pin 10 on J11 connector to enable pwdn_ref mode. W8 DAC enable Active: D/A on J j Standby: D/A off POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 Figure 15. EVM Schematic POST OFFICE BOX 655303 J9 R48 R47 R46 R45 R44 R43 R42 R41 CLOCK IN DV5 DV5 DAC_OUT J8 • DALLAS, TEXAS 75265 TP1 1 R28 3 49.9 2 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ C30 .1 µ F 0 TP2 2 1 10 9 13 8 3 SN74ALVC00 U2A SN74ALVC00 U2C SN74ALVC00 11 GND OUT U2D VCC OE X1 12 W2 DV5 W1 24 23 22 21 20 19 18 AVSS NC DVSS DVDD NC D0 D1 D2 R24 20 25 26 27 28 29 30 31 32 R2 200 R3 C25 .1 µ F 3.24 kΩ U3 11 CE 16 NC 15 DVSS 14 VB 13 DVDD 12 NC 10 BLK 9 CLK R4 .1 µ F C26 17 W3 5 6 19 18 17 16 15 14 13 12 CLK_OUT J11 CLK_IN 20 R37 R14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q DV3 C41 C28 .1 µ F R11 10 kΩ W8 10 SN74LVT574DW .1 µ F U5 20 DV3 1 OC 11 CLK 2 1D 3 2D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D DGND DV5 DV5 C29 .1 µ F 10 kΩ SN74ALVC00 20 U2B 4 R17 20 R29 20 R13 C24 .1 µ F DV5 CXD2306Q IREF IO IO VG AVDD AVDD VREF SREF D3 D4 D5 D6 D7 D8 D9 8 NC 1 2 3 4 5 6 7 R25 R23 R22 R21 R20 R19 R18 20 20 20 20 20 20 20 22 R40 W5 DV3 20 20 20 20 20 20 20 20 10 kΩ W4 R39 R38 R36 R35 R33 R32 R31 R30 DV5 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 REFBO EXT_REFB AV3 C36 .01 µ F 1 kΩ R8 .1 µ F C39 R5 C42 .1 µ F C38 10 µ F + TP3 .1 µ F C40 R12 C43 1 kΩ 1 C31 .1 µ F SW1 R27 EXT_REFT 10 TLE2144CDW REFTO EXT_REFT C44 10 µ F + 10 R26 EXT_REFB U4D 4OUT 16 1 kΩ R16 C32 .1 µ F 2OUT 7 C23 10 µ F REF3V + U4B TLE2144CDW – 2IN 5 + 7 5 6 8 2IN 6 TPS7133QD – 4IN 14 + 4IN 15 OUT OUT PG GND SENSE EN IN IN U1 U4A 1OUT 1 AV –12 13 – 1IIN 3 + C37 .1 µ F .01 µ F TP4 U4C 3OUT 10 1 kΩ R10 R15 4 2 3 4 R1 10 kΩ 1 kΩ AV +12 C27 .1 µ F 1IN 2 C22 10 µ F + R9 1 kΩ R6 5 kΩ REFTI REFBI – 3IN 12 + AV5 R34 49.9 2.1 k Ω W7 J10 3IN 11 REF3V R7 1 kΩ SW2 C33 .1 µ F C34 .1 µ F ANALOG IN C46 .1 µ F AV3 W6 Q(0–7) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 REF3V DV3 DRVDD AVSS D0 AVDD AIN D1 CML D2 PWDN_REF D3 AVSS D4 D5 REFBO REFBI D6 D7 REFTI DRVSS REFTO DVSS AVSS CLK BG AVDD OE DVDD STDBY .1 µ F C45 TLV5580PW C35 .1 µ F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 U6 DRV3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AV5 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Digital +5 V Analog +12 V J6 J3 L6 1 C11 2 1 µF 4.7 µH C12 10 µF + AV +12 V + J2 L7 1 2 AV –12 V C13 1 µF 4.7 µH C14 C21 + 10 µF + 10 µF Analog +5 V J5 DV5 + C17 10 µF L2 1 C3 2 1 µF 4.7 µH C4 10 µF + DV3 + C16 10 µF Digital +3.3 V (DRVDD) L5 1 C9 2 1 µF 4.7 µH C6 10 µF + Digital +3.3 V (DVDD) Analog –12 V J7 C5 2 1 µF C20 10 µF L3 1 4.7 µH C10 10 µF + J1 AV5 + C19 10 µF L1 1 C1 2 1 µF 4.7 µH C2 10 µF + DRV3 + C15 10 µF Analog +3.3 V J4 L4 1 C7 2 1 µF 4.7 µH C8 10 µF + AV3 + C18 10 µF Figure 15. EVM Schematic (Continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Top Overlay Figure 15. EVM Schematic (Continued) 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Top Layer Figure 15. EVM Schematic (Continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Internal Plane 1 Figure 15. EVM Schematic (Continued) 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Internal Plane 2 Figure 15. EVM Schematic (Continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 3350 (mil) TLV5580 EVALUATION MODULE 4200 (mil) Drill Drawing for Through Hole Figure 15. EVM Schematic (Continued) 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Bottom Layer Figure 15. EVM Schematic (Continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Table 3. TLV5580EVM Bill of Material QTY. REFERENCE DESIGNATOR VALUE SIZE DESCRIPTION MANUFACTURER/ PART NUMBER† 7 C1, C11, C13, C3, C5, C7, C9 1 µF 1206 ceramic multilayer capacitor Any 18 C10, C12, C14, C15, C16, C17, C18, C19, C2, C20, C21, C22, C23, C4, C6, C8, C38, C44 10 µF 3216 16 V, 10 µF, tantalum capacitor Any 2 C36, C43 0.01 µF 805 Ceramic multilayer Any 19 C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C37, C39, C40, C41, C42, C45, C46 0.1 µF 805 Ceramic multilayer capacitor Any 7 J1, J2, J3, J4, J5, J6, J7 2 terminal screw connector Lumberg KRMZ2 3 J10, J8, J9 PCM mount, SMA Jack Johnson Components 142-0701-206 1 J11 IDC26 13I × 2.025I square pin header Samtec TSW-113-07-L-D 7 L1, L2, L3, L4, L5, L6, L7 4.7 µH 4.7 µH DO1608C-472-Coil Craft Coil Craft DO1608-472 1 R2 2 R26, R27 12 R1, R11, R14, R40, R41, R42, R43, R44, R45, R46, R47, R48 6 R10, R12, R15, R16, R8, R9 1 R5 20 R13, R17, R18, R19, R20, R21, R22, R23, R24, R25, R29, R30, R31, R32, R33, R35, R36, R37, R38, R39 1 1 2 Screw Con SMA 0 1206 Chip resistor Any 10 1206 Chip resistor Any 10 K 1206 Chip resistor Any 1K 1206 Chip resistor Any 2.1 K 1206 Chip resistor Any 20 1206 Chip resistor Any R3 200 1206 Chip resistor Any R4 3.24 K 1206 Chip resistor Any R28, R34 49.9 1206 Chip resistor Any 1 R6 5K 4 mm SM pot-top adjust Bourns 3214W-5K 1 R7 1K 4 mm SM pot-top adjust Bourns 3214W-1K 2 SW1, SW2 SPDT C&K tiny series–slide switch C&K TS01CLE 4 TP1, TP2, TP3, TP4 TP Test point, single 0.025I pin Samtec TSW-101-07-L-S or equivalent 1 U3 CXD2306Q 1 U2 SN74ALVC00D 14-SOIC (D) 1 U5 SN74LVT574DW 20-SOP (DW) Sony CXD2306Q Quad 2-input positive NAND † Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Texas Instruments SN74ALVC00D Texas Instruments SN74LVT574DW TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 TLV5580 EVALUATION MODULE Table 3. TLV5580EVM Bill of Material (Continued) QTY. REFERENCE DESIGNATOR VALUE SIZE 1 U4 TLE2144CDW 16-SOP(D) 1 U6 TLV5580PW 28-TSSOP (PW) 1 U1 TPS7133 8-SOP(D) 6 W2, W4, W5, W6, W7, W8 2 W1, W3 1 X1 DESCRIPTION Quad op amp MANUFACTURER/ PART NUMBER† Texas Instruments TLE2144CDW/ TLE2144IDW Texas Instruments TLV5580PW Low-dropout voltage regulator Texas Instruments TPS7133QD SPST 2 position jumper, 0.1I spacing Samtec TSW-102-07-L-S or equivalent DPFT 3 position jumper, 0.1I spacing Samtec TSW-103-07-L-S or equivalent Crystal oscillator Epson SG-8002DC series NA † Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000 / C 07/96 NOTES: A. B. C. D. 32 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX 0,10 PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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