THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 D D D D D D D D D Dual Simultaneous Sample and Hold Inputs Differential or Single-Ended Analog Inputs 8-Bit Resolution 40 MSPS Sampling Analog-to-Digital Converter (ADC) Single or Dual Parallel Bus Output Low Power Consumption: 275 mW Typ Using External References Wide Analog Input Bandwidth: 600 MHz Typ 3.3 V Single-Supply Operation 3.3 V TTL /CMOS-Compatible Digital I/O Internal or External Bottom and Top Reference Voltages Adjustable Reference Input Range Power-Down (Standby) Mode 48-Pin Thin Quad Flat Pack (TQFP) Package AVSS Q– Q+ PWDN_REF CML REFT D D D 36 35 34 33 32 31 30 29 28 27 26 25 AVDD I+ I– AVSS AVDD STBY DVSS SELB DVDD AVSS CLK OE 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 1 D D D 2 3 4 5 6 7 8 DRVSS DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 NC NC DRVDD 9 10 11 12 DRVDD NC NC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DRVSS applications D REFB BG AVSS AVDD COUT C OUT PFB PACKAGE (TOP VIEW) features Digital Communications (Baseband Sampling) Cable Modems Set Top Boxes Test Instruments description The THS0842 is a dual 8-bit 40 MSPS high-speed A/D converter. It alternately converts each analog input signal into 8-bit binary-coded digital words up to a maximum sampling rate of 40 MSPS with an 80 MHz clock. All digital inputs and outputs are 3.3 V TTL /CMOS-compatible. Thanks to an innovative single-pipeline architecture implemented in a CMOS process and the 3.3 V supply, the device consumes very little power. In order to provide maximum flexibility, both bottom and top voltage references can be set from user supplied voltages. Alternately, if no external references are available, on-chip references can be used which are also made available externally. The full-scale range is 1 Vpp, depending on the analog supply voltage. If external references are available, the internal references can be powered down independently from the rest of the chip, resulting in an even greater power saving. The device is specifically suited for the baseband sampling of wireless local loop (WLL) communication, cable modems, set top boxes (STBs), and test instruments. AVAILABLE OPTIONS PACKAGED DEVICES TA TQFP-48 – 40°C to 85°C THS0842IPFB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 functional block diagram AVDD DRVDD CLK DVDD COUT Timing Circuitry COUT I+ Sample & Hold I– DA(7–0) MUX 8 BIT ADC 3-State Output Buffers BUS MUX DB(7–0) Q+ Sample & Hold OE Q– CM Configuration Control Circuit STBY Internal Reference Circuit BG AVSS 2 PWDN REFT REF POST OFFICE BOX 655303 REFB CML • DALLAS, TEXAS 75265 SELB DRVSS DVSS THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 ADC pipeline block diagram + ADC – SHA SHA ADC SHA SHA SHA SHA 2 DAC 2 2 2 2 2 2 Correction Logic Output Buffers D0(LSB)–D7(MSB) The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a resolution of 2 bits. Digital correction logic generates its result using the 2-bit result from the first stage, 1 bit from each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction logic ensures no missing codes over the full operating temperature range. circuit diagrams of inputs and outputs ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT DVDD AVDD 0.5 pF REFERENCE INPUT CIRCUIT AVDD Internal Reference Generator REFTO or REFBO D0–D7 OUTPUT CIRCUIT DRVDD D AVDD D_Out OE REFBI or REFTI DRVSS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 Terminal Functions TERMINAL NAME AVDD AVSS I/O DESCRIPTION 27, 37, 41 I Analog supply voltage 28, 36, 40, 46 I Analog ground BG 29 O Band gap reference voltage. A 1-µF capacitor with a 0.1-µF capacitor in parallel should be connected between this terminal and AVSS for external filtering. CLK 47 I Clock input. The input is sampled on each rising edge of CLK. CML 32 O Common mode level. This voltage is equal to (AVDD – AVSS)/2. An external 1-µF capacitor with a 0.1-µF capacitor in parallel should be connected between this terminal and AVSS. COUT 26 O Latch clock for the data outputs COUT 4 NO. 25 O Inverted latch clock for the data outputs DB7 – DB0 4 – 11 O Data outputs. D7 is the MSB. This is the second bus. Data is output from the Q channel when dual bus output mode is selected. Pin SELB selects the output mode. DRVDD DRVSS 1, 13 I Supply voltage for output drivers 12, 24 I Ground for digital output drivers DA7 – DA0 16 – 23 I Data outputs for bus A. D7 is MSB. This is the primary bus. Data from both input channels can be output on this bus or data from the I channel only. Pin SELB selects the output mode. DVDD 45 I Digital supply voltage DVSS 43 I Digital ground I– 39 I Negative input for analog channel 0. I+ 38 I Positive input for analog channel 0. NC 2,3,14,15 OE 48 I Output enable. A high on this terminal will disable the output bus. PWDN_REF 33 I Power down for internal reference voltages. A high on this terminal will disable the internal reference circuit. Q– 35 I Negative input for analog channel 1 Q+ 34 I Positive input for analog channel 1 REFB 30 I/O Reference voltage bottom. The voltage at this terminal defines the bottom reference voltage for the ADC. Sufficient filtering should be applied to this input. A 1-µF capacitor with a 0.1-µF capacitor in parallel should be connected between REFB and AVSS. Additionally, a 0.1-µF capacitor can be connected between REFT and REFB. REFT 31 I/O Reference voltage top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient filtering should be applied to this input. A 1-µF capacitor with a 0.1-µF capacitor in parallel should be connected between REFT and AVSS. Additionally, a 0.1-µF capacitor can be connected between REFT and REFB. SELB 44 I Selects either single bus or data output or dual bus output data output. A low selects dual bus data output. STBY 42 I Standby input. A high level on this terminal will power down the device. No connect. Reserved for future use POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Supply voltage: AVDD to DVDD, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 0.5 V Digital input voltage range to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to DVDD + 0.5 V Analog input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to AVDD + 0.5 V Digital output voltage applied from external source to DGND . . . . . . . . . . . . . . . . . . . – 0.5 V to DVDD + 0.5 V Reference voltage input range to AGND: V(REFT), V(REFB) . . . . . . . . . . . . . . . . . . . . – 0.5 V to AVDD + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Operating free-air temperature range, TA: Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions over operating free-air temperature range power supply AVDD DVDD Supply voltage MIN NOM MAX 3 3.3 3.6 UNIT V DRVDD analog and reference inputs Reference input voltage (top), V(REFT) MIN NOM MAX UNIT (NOM) – 0.2 AVDD – 1 1 (NOM) + 0.2 V 1.2 V AVDD – 2 V(REFT) V Reference input voltage (bottom), V(REFB) 0.8 Reference voltage differential, V(REFT) – V(REFB) Analog input voltage, V(IN) V(REFB) V digital inputs MIN High-level input voltage, VIH 2.0 Low-level input voltage, VIL DGND NOM MAX UNIT DVDD V 0.2xDVDD V Clock period, tc 12.5 ns Pulse duration, clock high, tw(CLKH) 5.25 ns Pulse duration, clock low, tw(CLKL) 5.25 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of internal voltage references, AVDD = DVDD = DRVDD = 3 V, TA = –40°C to 80°C, dual output bus mode (unless otherwise noted) power supply PARAMETER IDD Operating supply current TEST CONDITIONS AVDD DVDD DRVDD PD Power dissipation PD(STBY) Standby power MIN AVDD = DVDD = DRVDD = 3.3 3 3 V, V CL = 15 pF F, VI = 1 MHz, MHz –1 dBFS TYP MAX 73 95 3 3.8 17 22 PWDN_REF = L 320 393 PWDN_REF = H 275 335 11 15 TYP MAX STBY = H, CLK held high or low UNIT mA mW logic inputs PARAMETER IIH High-level input current on CLK† IIL Low-level input current on digital inputs (OE, STDBY, PWDN_REF, CLK) TEST CONDITIONS MIN AVDD = DVDD = DRVDD = CLK = 3.6 V AVDD = DVDD = DRVDD = 3.6 V, Digital inputs at 0 V UNIT 10 µA 10 µA CI Input capacitance 5 pF † IIH leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of 4 KΩ to DGND. logic outputs PARAMETER TEST CONDITIONS VOH High-level output voltage AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA, Digital output forced high VOL Low-level output voltage AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA, Digital output forced low CO Output capacitance IOZH High-impedance state output current to high level IOZL 6 MIN TYP MAX 2.8 V 0.1 5 High-impedance state output current to low level UNIT V pF 10 µA 10 µA 6V AVDD = DVDD = DRVDD = 3 3.6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of internal voltage references, AVDD = DVDD = DRVDD = 3 V, TA = –40°C to 80°C, dual output bus mode (unless otherwise noted) (continued) dc accuracy PARAMETER TEST CONDITIONS Integral nonlinearity (INL), best-fit See Note 1 Differential nonlinearity (DNL) See Note 2 Offset error TA = –40°C to 85°C TA = –40°C to 85°C MIN TYP MAX UNIT –2.2 ± 1.5 2.2 LSB –1 ± 0.7 2 LSB ± 0.1 5 %FS TA = –40°C 40°C to 85°C 85°C, (see Note 3) Gain error ± 7.1 Offset match TA = –40°C to 85°C, (see Note 4) –1 Gain match TA = –40°C to 85°C, (see Note 5) –5 ± 0.1 %FS 1 LSB 1 LSB Missing codes – no missing codes assured NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the best fit line between these two endpoints. 2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no missing codes. 3. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). 4. Offset match is the change in offset error between I and Q channels. 5. Gain match is the change in gain error between I and Q channels. analog input PARAMETER CI TEST CONDITIONS MIN Input capacitance TYP MAX 4 UNIT pF reference input (AVDD = DVDD = DRVDD = 3.6 V) PARAMETER Rref Reference input resistance Iref Reference input current TEST CONDITIONS MIN TYP MAX UNIT Ω 200 5 mA reference outputs PARAMETER V(REFT) V(REFB) VREFB–VREFB Reference top voltage Reference bottom voltage TEST CONDITIONS MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 2 + [(AVDD – 3)/2] AVDD = 3 V Absolute min/max values valid and tested for AVDD = 3 V TYP V 1 + [(AVDD – 3)/2] 0.9 1 UNIT 1.3 V 7 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of internal voltage references, AVDD = DVDD = DRVDD = 3 V, TA = –40°C to 80°C, dual output bus mode (unless otherwise noted) (continued) dynamic performance† PARAMETER TEST CONDITIONS Effective number of bits, ENOB Signal-to-total harmonic distortion + noise, S/(THD+N) MIN TYP fin = 1 MHz fin = 15 MHz 6.6 6.9 6.4 6.8 fin = 20 MHz fin = 1 MHz 6.4 6.8 41.5 43.5 40 42.5 40 42.5 fin = 15 MHz fin = 20 MHz fin = 1 MHz fin = 15 MHz Total harmonic distortion (THD) fin = 20 MHz fin = 1 MHz Spurious free dynamic range (SFDR) fin = 15 MHz fin = 20 MHz Analog input full-power bandwidth, BW See Note 6 Intermodulation distortion f1 = 1 MHz, f2 = 1.02 MHz MAX Bits dB –51 –46 –48.5 –44 –48.5 –44 48 53 47 52.2 46 52 UNIT dB dB 600 MHz 50 dBc I/Q channel crosstalk AVDD = DVDD = DRVDD = 3.3 V –52 dBc † Based on analog input voltage of – 1 dBFS referenced to a 1.3 Vpp full-scale input range. NOTE 6: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which an extra 3 dB attenuation is observed in the reconstructed output signal. timing requirements PARAMETER fclk lk TEST CONDITIONS MIN TYP Maximum clock rate (see Note 7) Minimum clock rate MAX UNIT 80 MHz 10 kHz td(O) th(O) Output delay time (see timing diagram) CL = 10 pF td(pipe) d( i ) Pipeline delay (latency) td(a) tj(a) Aperture delay time tdis ten Disable time, OE rising to Hi-Z 5 ns Enable time, OE falling to valid data 5 ns 7 ns Output hold time from COUT or COUT to data invalid 5.5 5.5 5.5 Q data 6.5 6.5 6.5 3 Aperture jitter 1.5 POST OFFICE BOX 655303 8 • DALLAS, TEXAS 75265 ns ns I data tsu(O) Output setup time from data to COUT or COUT NOTE 7: Conversion rate is 1/2 the clock rate, fclk. 8 9 2 CLK cycles ns ps, rms THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION N N+3 N+4 I N+1 N+2 N+2 N+1 Q N+3 N N+4 tJ(A) td(A) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK td(pipe-Q) td(O) td(pipe-I) td(O) DA(7–0) I–3 Q–3 I–2 Q–2 I–1 Q–1 I1 Q1 I2 Q2 I3 Q3 I4 Q4 I5 Q5 tsu(O) COUT th(O) COUT NOTE A: The relationship between CLK and COUT/COUT is not fixed and depends on the power-on conditions. Data out should be referenced to COUT and COUT. Figure 1. Timing Diagram, Single Bus Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION N N+3 N+4 I N+1 N+2 N+2 N+1 Q N+3 N N+4 tJ(A) td(A) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK td(pipe-Q) td(pipe-I) td(0) td(0) DA(7–0) DB(7–0) I–4 I–3 Q–4 I–2 Q–3 I–1 Q–2 I1 Q–1 I2 I3 Q1 Q2 I4 Q3 I5 Q4 Q5 tsu th DAB(15–0) I1 & Q1 I2 & Q2 I3 & Q3 I4 & Q4 I5 & Q5 DAB(15–0) is the combination of both DA and DB. It illustrates when both buses have valid data for latching. COUT COUT NOTE A: The relationship between CLK and COUT/COUT is not fixed and depends on the power-on conditions. Data out should be referenced to COUT and COUT. Figure 2. Timing Diagram, Dual Bus Output 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 TYPICAL CHARACTERISTICS† POWER CONSUMPTION vs TEMPERATURE EFFECTIVE NUMBER OF BITS vs ANALOG INPUT FREQUENCY 120 7 I – Current – mA ENOB – Effective Number of Bits – Bits ICC Total 100 IAVDD 80 60 40 IDRVDD 20 IDVDD 0 –40 –15 60 10 35 TA – Temperature – °C 6.9 6.8 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6 85 10 15 5 fi – Analog Input Frequency – MHz 0 Figure 3 20 Figure 4 SIGNAL-TO-NOISE RATIO vs TEMPERATURE 50 SNR – Signal-to-Noise Ratio – dB 49 48 47 46 45 44 43 42 41 40 –40 –15 10 35 TA – Temperature – °C 60 85 Figure 5 † Unless otherwise noted AVDD = DVDD = DRVDD = 3 V, fCLK = 80 MHz, Analog Input = –1 dB FS, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 DNL – Differential Nonlinerity – LSB TYPICAL CHARACTERISTICS† DIFFERENTIAL NONLINEARITY 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 128 ADC CODE 0 255 Figure 6 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 128 0 255 ADC CODE Figure 7 FAST FOURIER TRANSFORM 0 I Input Channel AIN = 1.1 MHz Power – dBFS –20 –40 –60 –80 –100 –120 –140 0 2 4 6 8 10 12 14 16 18 f – Frequency – MHz Figure 8 † Unless otherwise noted AVDD = DVDD = DRVDD = 3 V, fCLK = 80 MHz, Analog Input = –1 dB FS, TA = 25°C. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 20 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 TYPICAL CHARACTERISTICS† FAST FOURIER TRANSFORM 0 Q Input Channel AIN = 1.1 MHz –20 Power – dBFS –40 –60 –80 –100 –120 –140 0 2 4 6 10 8 12 14 16 18 14 16 18 20 f – Frequency – MHz Figure 9 FAST FOURIER TRANSFORM 0 I Input Channel AIN = 15.1 MHz Power – dBFS –20 –40 –60 –80 –100 –120 –140 0 2 4 6 8 10 12 20 f – Frequency – MHz Figure 10 FAST FOURIER TRANSFORM 0 Q Input Channel AIN = 15.1 MHz Power – dBFS –20 –40 –60 –80 –100 –120 –140 0 2 4 6 8 10 12 f – Frequency – MHz 14 16 18 20 Figure 11 † Unless otherwise noted AVDD = DVDD = DRVDD = 3 V, fCLK = 80 MHz, Analog Input = –1 dB FS, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 TYPICAL CHARACTERISTICS† FAST FOURIER TRANSFORM 0 I Input Channel AIN = 20 MHz Power – dBFS –20 –40 –60 –80 –100 –120 –140 0 2 4 6 8 10 12 14 16 18 20 14 16 18 20 f – Frequency – MHz Figure 12 FAST FOURIER TRANSFORM 0 Q Input Channel AIN = 20 MHz Power – dBFS –20 –40 –60 –80 –100 –120 –140 0 2 4 6 8 10 12 f – Frequency – MHz Figure 13 † Unless otherwise noted AVDD = DVDD = DRVDD = 3 V, fCLK = 80 MHz, Analog Input = –1 dB FS, TA = 25°C. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 TYPICAL CHARACTERISTICS† ANALOG INPUT BANDWIDTH 4 2 0 Power – dB –2 –4 –6 –8 –10 –12 –14 10 1 100 1000 f – Frequency – MHz Figure 14 TWO-TONE INTERMODULATION DISTORTION 0 f1 = 1 MHz, –7 dBFS f2 = 1.04 MHz, –7 dBFS Power – dB –20 –40 –60 –80 –100 –120 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 f – Frequency – MHz Figure 15 † Unless otherwise noted AVDD = DVDD = DRVDD = 3 V, fCLK = 80 MHz, Analog Input = –1 dB FS, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 TYPICAL CHARACTERISTICS† SNR – Signal-to-Noise Ratio – dB I CHANNEL CROSSTALK 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 2 4 6 8 10 12 f – Frequency – MHz 14 16 18 20 Figure 16 SNR – Signal-to-Noise Ratio – dB Q CHANNEL CROSSTALK 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 2 4 6 8 10 12 f – Frequency – MHz 14 16 18 Figure 17 † Unless otherwise noted AVDD = DVDD = DRVDD = 3 V, fCLK = 80 MHz, Analog Input = –1 dB FS, TA = 25°C. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 20 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION definitions of specifications and terminology integral nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. differential nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test, i.e. (last transition level – first transition level)/(2n –2). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no missing codes. offset and gain error Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). analog input bandwidth The analog input bandwidth is defined as the maximum frequency of a 1-dBFS input sine wave that can be applied to the device for which an extra 3-dB attenuation is observed in the reconstructed output signal. output timing Output timing td(o) is measured from the 1.5-V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital output load is not higher than 10 pF. Output hold time th(o) is measured from the 1.5-V level of the CLK input falling edge to the10%/90% level of the digital output. The digital output load is not less than 2 pF. Aperture delay td(A) is measured from the 1.5-V level of the CLK input to the actual sampling instant. The OE signal is asynchronous. OE timing tdis is measured from the VIH(min) level of OE to the high-impedance state of the output data. The digital output load is not higher than 10 pF. OE timing ten is measured from the VIL(max) level of OE to the instant when the output data reaches VOH(min) or VOL(max) output levels. The digital output load is not higher than 10 pF. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION definitions of specifications and terminology (continued) pipeline delay (latency) The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to know when data is stable on the output pins, the output delay time td(o) (i.e., the delay time through the digital output buffers) needs to be added to the pipeline latency. Note that since the max td(o) is more than 1/2 clock period at 80 MHz, data cannot be reliably clocked in on a rising edge of CLK at this speed. The falling edge should be used. The THS0842 implements a high-speed 40 MSPS converter in a cost effective CMOS process. Powered from 3.3 V, the single pipeline design architecture ensures low power operation and 8-bit accuracy. Signal inputs are differential and the clock signal is single ended. The digital inputs are 3.3 V TTL/CMOS compatible. Internal voltage references are included for both bottom and top voltages. Therefore, the converter forms a self-contained solution. Alternatively, the user may apply externally generated reference voltages. In doing so, both input offset and input range can be modified to suit the application. The analog input signal is captured by a high speed sampling and hold. Multiple stages will generate the output code with a pipeline delay of 6.5 CLK cycles. Correction logic combines the multistage data and aligns the 8-bit output word. All digital logic operates at the rising edge of CLK. analog input THS0842 VS+ VS– + – RS RSW RS RSW CI CI + – VCM VCM Figure 18. Simplified Equivalent Input Circuit A first-order approximation for the equivalent analog input circuit of the THS0842 is shown in Figure 18. The equivalent input capacitance CI is 5 pF typical. The input must charge/discharge this capacitance within the sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides the charging current through the switch resistance RSW (200 Ω) of S1 and quickly settles. In this case the input impedance is low. Alternatively, when the source voltage equals the value previously stored on CI, the hold capacitor requires no input current and the equivalent input impedance is very high. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION analog input (continued) To maintain the frequency performance outlined in the specifications, the total source impedance should be limited to the following equation with fCLK = 80 MHz, CI = 5 pF, RSW = 200 Ω: R S t ƪ ǒ 1 ÷ 2f CLK C I Ǔ ƫ In(256) –R SW So, for applications running at a lower fCLK, the total source resistance can increase proportionally. The analog input of the THS0842 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 20) will deliver the best performance from the converter. A dc voltage source, CML, equal to 1.5 V (typical), is made available to the user to help simplify circuit design when using an ac coupled differential input. This low output impedance voltage source is not designed to be a reference or to be loaded, but makes an excellent dc bias source and stays well within the analog input common mode voltage range over temperature. Defining VREFD = VREFT – VREFB, each single-ended analog input is limited to be between VCML + VREFD/2 and VCML – VREFD/2. For the ac coupled differential input (Figure 23), full scale is achieved when the +I/Q and –I/Q input signals are 0.5 VPP, with –I/Q being 180 degrees out of phase with +I/Q. The converter will be at positive full scale when the +I/Q input is at CML + 0.25 V and the –I/Q input is at CML – 0.25 V (+I/Q + I/Q – = 0.5 V). Conversely, the converter will be at negative full scale when the +I/Q input is equal to CML – 0.25 V and –I/Q is at CML + 0.25 V (I/Q+ + I/Q– = –0.5 V) (see Figure 19). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION analog input (continued) I/Q+ 1.5 + 0.25 V Positive Analog Input 1.5 V I/Q+ 1.5 – 0.25 V I/Q– 1.5 – 0.25 V Negative Analog Input 1.5 V I/Q– 1.5 + 0.25 V +0.5 V Differential Input 1.0 Vp–p 0V –0.5 V Figure 19. Differential Input Waveform The analog input can be dc coupled (Figure 21) as long as the inputs are within the analog input common mode voltage range. The resistors, R, in Figure 21 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from I/Q IN+ to I/Q IN– will help filter any high frequency noise on the inputs, also improving performance. Note, that the chosen value of capacitor C must take into account the highest frequency component of the analog input signal. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION ac coupled input R VIN+ C1 THS0842 R – AIN– + R R C2 R VIN– C1 R – AIN+ + R R C2 CML REFT REFB THS0842 VIN+ C1 AIN+ R C2 R VIN– C1 AIN– C2 CML REFT REFB Figure 20. AC-Coupled Differential Input Circuits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION THS0842 VIN+ AIN+ R C R VIN– AIN– CML REFT REFB Figure 21. DC-Coupled Differential Input Circuit For many applications, ac coupling offers a convenient way for biasing the analog input signal at the proper signal range. Figure 20 shows a typical configuration. To maintain the outlined specifications, the component values need to be carefully selected. The most important issue is the positioning of the 3 dB high-pass corner point f– 3 dB, which is a function of R (RS + RW – Figure 18) and the parallel combination of C1 and C2, called Ceq. This is given by the following equation: f –3 dB +1 ǒ Ǔ ÷ 2π x R x C eq where Ceq is the parallel combination of C1 and C2 and R is the series combination of RS and RW seen in Figure 18. Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01 µF, which is not inductive within the frequency range of interest, maintains low impedance. If the minimum expected input signal frequency is 20 kHz, and R2 equals 1 kΩ and R1 equals 50 Ω, the parallel capacitance of C1 and C2 must be a minimum of 8 nF to avoid attenuating signals close to 20 kHz. analog input, single-ended connection The configuration shown in Figure 23 may be used with a single-ended ac coupled input. If I/Q is a 1 Vpp sinewave, then I/Q IN+ is a 1 Vpp sinewave riding on a positive voltage equal to CML (see Figure 22). The converter will be at positive full scale when I/Q IN+ is at CML+0.5V (I/Q IN+ – I/Q IN– = 0.5 V) and will be at negative full scale when I/Q IN+ is equal to CML – 0.5 V (I/Q IN+ – I/Q IN– = –0.5 V). Sufficient headroom must be provided such that the input voltage never goes above 3.3 V or below AGND. The simplest way is to use the dc bias source output (CML) of the THS0842. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION analog input, single-ended connection (continued) The single ended analog input can be dc coupled (Figure 24) as long as the input is within the analog input common mode voltage range. A capacitor, C, connected from I/Q IN+ to I/Q IN– will help filter any high frequency noise on the inputs, also improving performance. Note, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. 2V Single Ended Input 1.0 Vp–p 1.5 V 1V Figure 22. Single-Ended Input Waveform A single-ended source may give better overall system performance if it is first converted to differential before driving the THS0842. THS0842 VIN C1 R AIN+ R C2 VBIAS + AIN– CML REFT REFB Figure 23. AC-Coupled Input POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION dc coupled input R THS0842 VIN VIN THS0842 R – AIN– AIN+ + R C C R AIN+ AIN– CML CML REFT REFT REFB REFB Figure 24. DC-Coupled Input Circuits For dc-coupled systems, an op-amp can level shift a ground referenced input signal. A circuit like Figure 27 could be used. In this case, the AIN voltage is given by: AIN = –VIN + VCML reference terminals The THS0842 input voltage range is determined by the voltages on terminals REFBI and REFTI. Since the device has an internal voltage reference generator, it must be placed in power down before applying an external voltage to the REFT and REFB pins. Especially at higher sampling rates, it is advantageous to have a wider analog input range. This can be achievable by using external voltage references (e.g., at AVDD = 3.3 V, the full scale range can be extended from 1 Vpp (internal reference) to 1.3 Vpp (external reference) as shown in Table 1). These voltages should not be derived via a voltage divider from a power supply source. Instead, use a bandgap-derived voltage reference to derive both references via an op-amp circuit. Refer to the schematic of the THS0842 evaluation module in this datasheet for an example circuit. When using external references, the full-scale ADC input range and its dc position can be adjusted. The full-scale ADC range is always equal to VREFT – VREFB. The maximum full-scale range is dependent on AVDD as shown in the specification section. Next to the constraint on their difference, there are limitations on the useful range of VREFT and VREFB individually as well, dependent also on AVDD. Table 1 summarizes these limits for 3 cases. Table 1. Min/Max Reference Input Levels 24 AVDD 3V VREFB(min) 0.8 V VREFB(max) 1.2 V VREFT(min) 1.8 V VREFT(max) 2.2 V [VREFT–VREFB]max 1V 3.3 V 0.8 V 1.2 V 2.1 V 2.5 V 1.3 V 3.6 V 0.8 V 1.2 V 2.4 V 2.8 V 1.6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION digital inputs The digital inputs are CLK, STDBY, PWDN_REF, and OE. All these signals, except CLK, have an internal pulldown resistor to connect to digital ground. This provides a default active operation mode using internal references when left unconnected. The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be minimized by proper termination of the signal close to the THS0842. An important cause of performance degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2N) of a signal that needs to be sampled and the maximum amount of aperture error dtmax that is tolerable. The following formula shows the relation: dt max +1B ƪ ƫ ǒ )Ǔ p f 2N 1 As an example, for an 8-bit converter with a 15-MHz input, the jitter needs to be kept <41 pS in order not to have changes in the LSB of the ADC output due to the total aperture error. digital outputs The output of THS0842 is straight binary code. Capacitive loading on the output should be kept as low as possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading causes higher dynamic output currents and can increase noise coupling into the device analog front end. To drive higher loads, use an output buffer is recommended. See Figure 25 through Figure 28 for examples. When clocking output data from the THS0842, it is important to observe its timing relation to CLK. Pipeline ADC delay is 55 clock cycles to which the maximum output propagation delay is added. See Note 6 in the specification section for more details. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION THS0842 SN74ALVCH16841 8 10 1D7 – 1D0 DA7– DA0 COUT 1D8 COUT 1D9 2D7 – 2D0 ASIC or DSP 1Q9 – 1Q0 2Q9 – 2Q0 LE OE Figure 25. Single Bus Connection Example THS0842 SN74ALVCH16841 8 9 1D7 – 1D0 DA7– DA0 COUT 1D8 COUT 2D8 1Q8 – 1Q0 9 8 DB7– DB0 2D7 – 2D0 2Q8 – 2Q0 LE OE Figure 26. Dual Bus Connection Example NOTE: The SN74ALVCH16841 latches are used to buffer the THS8042 and COUT pins. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ASIC or DSP THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 PRINCIPLES OF OPERATION THS0842 FIFO 1D15 SN74LVC827A DA7 1D7 1Q7 8 DA0 1Q15 8 1D0 1Q0 1D8 1Q8 1D9 1Q9 1D8 1D7 TMS320 DSP 16 1Q0 SN74LVC374A 1D7 1Q7 1D0 1Q0 1D0 HF Flag INTR COUT COUT WRTCLK CLK Figure 27. Single Bus FIFO Connection to DSP Example THS0842 FIFO DSP 8 DA7– DA0 16 D7 – D0 1Q15 – 1Q0 8 DB7– DB0 COUT D16 – D9 HF Flag INTR > WRTCLK Figure 28. Dual Bus FIFO Connection to DSP Example layout, decoupling and grounding rules Proper grounding and layout of the PCB on which the THS0842 is populated are essential to achieve the stated performance. It is advisable to use separate analog and digital ground planes that are spliced underneath the device. The THS0842 has digital and analog terminals on opposite sides of the package to make this easier. Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB. It is advisable to do this at one point in close proximity to the THS0842. As for power supplies, separate analog and digital supply terminals are provided on the device (AVDD/DVDD). The supply to the digital output drivers is kept separate also (DRVDD). Lowering the voltage on this supply to 3 V instead of the nominal 3.3 V improves performance because of the lower switching noise caused by the output buffers. Because of the high sampling rate and switched-capacitor architecture, THS0842 generates transients on the supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the THS0842 EVM is recommended. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 THS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT SLAS246 – DECEMBER 1999 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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