ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter Check for Samples: ADC1175-50 FEATURES DESCRIPTION • • • • • The ADC1175-50 is a low power, 50 MSPS analogto-digital converter that digitizes signals to 8 bits while consuming just 125 mW (typ). The ADC1175-50 uses a unique architecture that achieves 6.8 Effective Bits at 25 MHz input and 50 MHz clock frequency. Output formatting is straight binary coding. 1 Internal Track-and-Hold Function Single +5V Operation Internal Reference Bias Resistors Industry Standard Pinout Power-Down Mode (<5 mW) APPLICATIONS • • • • • Digital Still Cameras CCD Imaging Electro-Optics Video Digitization Multimedia KEY SPECIFICATIONS • • • • • • • Resolution 8 Bits Maximum Sampling Frequency 50 MSPS (min) THD 54 dB (typ) DNL 0.7 LSB (typ) ENOB @ fIN = 25 MHz 6.8 Bits (typ) Ensured No Missing Codes Power Consumption (Excluding Reference Current) 125 mW (typ) 190 mW (max) The excellent DC and AC characteristics of this device, together with its low power consumption and +5V single supply operation, make it ideally suited for many video and imaging applications, including use in portable equipment. Furthermore, the ADC1175-50 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC1175-50's reference ladder is available for connections, enabling a wide range of input possibilities. The low input capacitance (7 pF, typical) makes this device easier to drive than conventional flash converters and the power down mode reduces power consumption to less than 5 mW. The ADC1175-50 is offered in 24-pin TSSOP and 24pin WQFN packages and is designed to operate over the extended commercial temperature range of −20°C to +75°C. CONNECTION DIAGRAMS Figure 1. 24-Pin TSSOP - Top View See PW Package Figure 2. 24-Pin WQFN - Bottom View See NHW0024B Package 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (1) Pin No. Symbol 19 (17) VIN 16 (14) VRTS Reference Top Bias with internal pull up resistor. Short this pin to VRT to self-bias the reference ladder. 17 (15) VRT Analog input that is the high (top) side of the reference ladder of the ADC. Voltages on VRT and VRB inputs define the VIN conversion range. Bypass well. See REFERENCE INPUTS for more information. 23 (21) VRB Analog input that is the low (bottom) side of the reference ladder of the ADC. Nominal range is 0.0V to 4.0V, with optimized value of 0.6V. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See REFERENCE INPUTS for more information. 22 (20) VRBS Reference Bottom Bias with internal pull down resistor. Short to VRB to self-bias the reference ladder. Bypass well (unless grounded). See REFERENCE INPUTS for more information. Equivalent Circuit Description Analog signal input. Conversion range is VRT to VRB. DVDD 1 (23) PD CMOS/TTL compatible Digital input that, when high, puts the ADC1175-50 into a power-down mode where total power consumption is typically less than 5 mW. With this pin low, the device is in the normal operating mode. 1 DVSS (1) (WQFN pins in parentheses) Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 3 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS(1) (continued) Pin No. Symbol Equivalent Circuit Description DVDD 12 (10) CLK CMOS/TTL compatible digital clock input. VIN is sampled on the falling edge of CLK input. 12 DVSS DVDD 3 thru 10 (1 thru 8) D0–D7 Dn Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. These pins are in a high impedance mode when the PD pin is low. DVSS 11, 13, 14 (9, 11, 12) DVDD Positive digital supply pin. Connect to a quiet voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10 µF capacitor and a 0.1 µF ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. 2, 24 (22, 24) DVSS The ground return for the digital supply. AVSS and DVSS should be connected together close to the ADC1175-50. 15, 18 (13, 16) AVDD Positive analog supply pin. Connect to a quiet voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10 µF capacitor and a 0.1 µF ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. 20, 21 (18, 19) AVSS The ground return for the analog supply. AVSS and DVSS should be connected together close to the ADC1175-50 package. 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) Supply Voltage (AVDD, DVDD) 6.5V −0.3V to +6.5V Voltage on Any Input or Output Pin Reference Voltage (VRT, VRB) AVSS to VDD −0.5 to (AVDD +0.5V) CLK, PD Voltage Range Digital Output Voltage (VOH, VOL) VSS to VDD Input Current at Any Pin (4) Package Input Current ±25 mA (4) ±50 mA Power Dissipation at TA = 25°C ESD Susceptibility See (6) Human Body Model 2000V Machine Model Soldering Temperature 250V Infrared (10 sec.) 235°C −65°C to +150°C Storage Temperature Short Circuit Duration (Single High Output to Ground) (1) (2) (3) (4) (5) (6) (5) 1 Second All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperature (TJ max) for this device is 150°C. The maximum allowable power dissipation is dictated by TJ max, the junction-to-ambient thermal resistance (θJA) and the ambient temperature (TA), and can be calculated using the formula PD max = (TJ max – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC1175-50 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. OPERATING RATINGS (1) (2) −20°C ≤ TA ≤ +75°C Operating Temperature Range Supply Voltage (AVDD, DVDD) +4.75V to +5.25V AVDD − DVDD <0.5V Ground Difference |DVSS – AVSS| 0V to 100 mV Pin 11 to Pin 13 Voltage <0.5V Upper Reference Voltage (VRT) 1.0V to VDD Lower Reference Voltage (VRB) 0V to 4.0V VRT - VRB 1V to 2.8V VIN Voltage Range VRB to VRT (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified. PACKAGE THERMAL RESISTANCE Package θJA TSSOP 92°C / W WQFN 40°C / W Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 5 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 50 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1) (2). Symbol Parameter Typical (3) Conditions Limits (3) Units (Limits) DC ACCURACY INL Integral Non Linearity Error DNL Differential Non-Linearity VIN = 0.6V to 2.6V VIN = 0.6V to 2.6V ±0.8 ±1.95 LSB (max) +0.7 +1.75 LSB (max) −0.7 −1.0 LSB (min) 8 Bits Resolution for No Missing Codes EOT Top Offset Voltage −12 mV EOB Bottom Offset Voltage +10 mV VIDEO ACCURACY DP Differential Phase Error fIN = 4.43 MHz Modulated Ramp 0.5 deg DG Differential Gain Error fIN = 4.43 MHz Modulated Ramp 1.0 % ANALOG INPUT AND REFERENCE CHARACTERISTIC VIN Input Range CIN VIN Input Capacitance RIN 2.0 VRB VRT V (min) V (max) (CLK LOW) 4 (CLK HIGH) 7 pF RIN Input Resistance >1 MΩ BW Full Power Bandwidth 120 MHz RRT Top Reference Resistor 320 RREF Reference Ladder Resistance RRB Bottom Reference Resistor IREF VIN = 1.5V +0.7 Vrms VRT to VRB 270 pF Ω 200 350 Ω (min) Ω (max) 5.4 mA (min) 10.8 mA (max) Ω 80 VRT = VRTS, VRB = VRBS 7 VRT = VRTS, VRB = AVSS 8 Reference Ladder Current VRT Reference Top Self Bias Voltage VRT Connected to VRTS, VRB Connected to VRBS 2.6 VRB Reference Bottom Self Bias Voltage VRT Connected to VRTS, VRB Connected to VRBS 0.6 6.1 mA (min) 12.3 mA (max) V (min) V (max) 0.55 0.70 V (min) V (max) (1) The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or 500 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75 VDC, the full-scale input voltage must be ≤4.80 VDC to ensure accurate conversions. spacer (2) To ensure accuracy, it is required that AVDD and DVDD be well bypassed. Each VDD pin must be decoupled with separate bypass capacitors. Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). (3) 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 CONVERTER ELECTRICAL CHARACTERISTICS (continued) The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 50 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1)(2). Symbol VRTS – VRBS Self Bias Voltage Delta VRT – VRB Typical (3) Limits (3) Units (Limits) VRT Connected to VRTS, VRB Connected to VRBS 2 1.89 2.20 (V (min) V (max) VRT Connected to VRTS, VRB Connected to AVSS 2.3 Parameter Conditions V 2 1.0 2.8 V (min) V (max) fIN = 4.4 MHz, fCLK = 40 MHz 7.2 6.7 Bits (min) fIN = 19.9 MHz, fCLK = 40 MHz 7.0 6.4 Bits (min) fIN = 1.3 MHz, fCLK = 50 MHz 7.3 Bits fIN = 4.4 MHz, fCLK = 50 MHz 7.2 Bits fIN = 24.9 MHz, fCLK = 50 MHz 6.8 6.1 Bits (min) fIN = 4.4 MHz, fCLK = 40 MHz 45 42 dB (min) fIN = 19.9 MHz, fCLK = 40 MHz 44 40 dB (min) fIN = 1.3 MHz, fCLK = 50 MHz 46 fIN = 4.4 MHz, fCLK = 50 MHz 45 fIN = 24.9 MHz, fCLK = 50 MHz 43 38.4 dB (min) fIN = 4.4 MHz, fCLK = 40 MHz 46 42.5 dB (min) fIN = 19.9 MHz, fCLK = 40 MHz 44 41 dB (min) fIN = 1.3 MHz, fCLK = 50 MHz 48 dB fIN = 4.4 MHz, fCLK = 50 MHz 45 dB fIN = 24.9 MHz, fCLK = 50 MHz 44 fIN = 1.3 MHz 57 dB fIN = 4.4 MHz 56 dB fIN = 24.9 MHz 51 dB fIN = 1.3 MHz −55 dB fIN = 4.4 MHz −54 dB fIN = 24.9 MHz −51 dB Reference Voltage Differential CONVERTER DYNAMIC CHARACTERISTICS ENOB SINAD SNR SFDR THD Effective Number of Bits Signal-to-Noise & Distortion Signal-to-Noise Ratio Spurious Free Dynamic Range Total Harmonic Distortion dB dB 40 dB (min) POWER SUPPLY CHARACTERISTICS IADD Analog Supply Current DVDD = AVDD = 5.25V 13 mA IDDD Digital Supply Current DVDD = AVDD = 5.25V 11 mA IADD + IDDD Total Operating Current DVDD = AVDD = 5.25V, fCLK = 50 MHz 25 DVDD = AVDD = 5.25V, CLK Inactive (low) 14 Power Consumption PD pin low 125 Power Consumption PD pin high <5 mW 36 mA (max) 190 mW (max) mA mW CLK, PD DIGITAL INPUT CHARACTERISTICS VIH Logical High Input Voltage 2.0 V (min) VIL Logical Low Input Voltage 0.8 V (max) IIH Logical High Input Current VIH = DVDD = AVDD = +5.25V ±5 µA (max) IIL Logical Low Input Current VIL = 0V, DVDD = AVDD = +5.25V ±5 µA (max) CIN Digital Input Capacitance 4 pF DIGITAL OUTPUT CHARACTERISTICS IOH Output Current, Logic HIGH DVDD = 4.75V, VOH = 4.0V −1.1 mA (min) IOL Output Current, Logic LOW DVDD = 4.75V, VOL = 0.4V 1.8 mA (min) IOZH, IOZL TRI-STATE Output Current DVDD = 5.25V, PD = DVDD, VOL = DVDD, or VOL = 0V ±20 µA Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 7 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS (continued) The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 50 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (1)(2). Symbol Parameter Conditions Typical (3) Limits (3) Units (Limits) 50 MHz (min) 5 ns (min) AC ELECTRICAL CHARACTERISTICS fC1 Maximum Conversion Rate 55 fC2 Minimum Conversion Rate 1 tOD Output Delay CLK high to data valid Pipeline Delay (Latency) 20 ns (max) 2.5 Clock Cycles 3 ns tDS Sampling (Aperture) Delay tAJ Aperture Jitter 10 ps rms tOH Output Hold Time CLK high to data invalid 10 ns tEN PD Low to Data Valid Loaded as in Figure 16 140 ns 8 CLK low to acquisition of data 14 MHz Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5V, fCLK = 50 MHz, unless otherwise stated. INL Plot DNL Plot Figure 3. Figure 4. INL vs. Temperature DNL vs. Temperature Figure 5. Figure 6. SNR vs. Temp & fIN THD vs. Temp & fIN Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 9 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) AVDD = DVDD = 5V, fCLK = 50 MHz, unless otherwise stated. 10 SINAD & ENOB vs. Temp & fIN SINAD & ENOB vs. Clock Duty Cycle Figure 9. Figure 10. SFDR vs. Temp & fIN tOD vs. Temperature Figure 11. Figure 12. Power Supply Current vs. fCLK Spectral Response Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 SPECIFICATION DEFINITIONS ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input signal is the full power bandwidth. APERTURE JITTER is the time uncertainty of the sampling point (tDS), or the range of variation in the sampling delay. BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to the first code and the negative reference voltage. Bottom Offset is defined as EOB = VZT − VRB, where VZT is the first code transition input voltage. Note that this is different from the normal Zero Scale Error. DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency reconstructed sine wave at two different d.c. levels. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DNL is measured at the rated clock frequency with a ramp input. DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave at two different d.c. levels. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual codes from a line drawn from zero scale (1/2 LSB below the first code transition) through positive full scale (1/2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. INL is measured at rated clock frequency with a ramp input. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins. OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output stage. Data for any given sample is available the Pipeline Delay plus the Output Delay after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. SAMPLING (APERTURE) DELAY, or tDS, is the time required after the falling edge of the clock for the sampling switch to open (in other words, for the Sample/Hold circuit to go from the “sample” mode into the “hold” mode). The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tDS after the clock goes low. SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the output code to transition to full scale and is defined as EOT = VFT − VRT. Where VFT is the full scale transition input voltage. Note that this is different from the normal Full Scale Error. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components to the rms value of the input signal. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 11 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Timing Diagram Figure 15. ADC1175-50 Timing Diagram Figure 16. tEN, tDIS Test Circuit 12 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The ADC1175-50 maintains superior dynamic performance with input frequencies up to 1/2 the clock frequency, achieving 6.8 effective bits with a 50 MHz sampling rate and 25 MHz input frequency. The analog signal at VIN that is within the voltage range set by VRT and VRB are digitized to eight bits at up to 55 MSPS. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones. While the ADC1175-50 is specified for top and bottom reference voltages (VRT and VRB) or 2.6V and 0.6V, respectively, and will give best performance at these values, VRT has a range of 1.0V to the analog supply voltage, AVDD, while VRB has a range of 0V to 4.0V. VRT should always be at least 1.0V more positive than VRB. With VRT voltages above 2.8V, it is necessary to reduce the clock frequency to maintain SINAD performance. VRT should always be between 1.0V and 2.8V more positive than VRB. If VRT and VRTS are connected together and VRB and VRBS are connected together, the nominal values of VRT and VRB are 2.6V and 0.6V, respectively. If VRT and VRTS are connected together and VRB is grounded, the nominal value of VRT is 2.3V. Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital outputs 2.5 clock cycles plus tOD later. The ADC1175-50 will convert as long as the clock signal is present at the CLK pin. The PD pin, when high, puts the device into the Power Down mode. When the PD pin is low, the device is in the normal operating mode. The Power Down pin (PD), when high, puts the ADC1175-50 into a power down mode where power consumption is typically less than 5 mW. When the part is powered down, the digital output pins are in a high impedance TRISTATE. It takes about 140 ns for the part to become active upon coming out of the power down mode. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 13 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION (All Schematic pin numbers refer to the TSSOP.) THE ANALOG INPUT The analog input of the ADC1175-50 is a switch followed by an integrator. That is, a switched capacitor input, appearing as 4 pF when the clock is low, and 7 pF when the clock is high. Switched capacitor inputs produce voltage spikes at the input pin at the ADC sample rate. There should be no attempt to eliminate these spikes, but they should settle out during the sample period (the clock high time). An RC at the ADC analog input pin, as shown in Figure 17, will help. For Nyquist applications, the capacitor should be about 10 times ADC track mode input capacitance and the pole frequency of this RC should be about the ADC sample rate. The LMH6702, and the LMH6609 have been found to be excellent amplifiers for driving the ADC1175-50. Do not drive the input beyond the supply rails. Figure 17 shows an example of an input circuit using the LMH6702. Driving the analog input with input signals up to 2.8 VP-P will result in normal behavior where signals above VRT will result in a code of FFh and input voltages below VRB will result in an output code of zero. Input signals above 2.8 VP-P may result in odd behavior where the output code is not FFh when the input exceeds VRT. +5V Choke 150, 1% 0.1 PF 237, 1% 57.6, 1% 10 PF 237, 1% 2 Analog Input + + 10 PF 3 + 150, 1% 47 6 14 15 18 11 13 AVDD 19 0.1 PF DVDD to AVDD 62 pF LMH6702 16 17 VRTS VRT 10 PF ADC1175-50 23 22 D7 D6 D5 D4 D3 D2 D1 D0 10 9 8 7 6 5 4 3 VRB VRBS 10 PF PD to AVSS AVSS 20 21 DVSS 2 24 1 CLK 12 Choose an op-amp that can drive a dynamic capacitance. Figure 17. Driving the ADC1175-50 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 REFERENCE INPUTS The reference inputs VRT (Reference Top) and VRB (Reference Bottom) are the top and bottom of the reference ladder. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Operating Ratings section (1.0V to AVDD for VRT and 0V to (AVDD − 1.0V) for VRB). Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin. The reference ladder can be self-biased by connecting VRT to VRTS and connecting the VRB to VRBS to provide top and bottom reference voltages of approximately 2.6V and 0.6V, respectively, with VCC = 5.0V. This connection is shown in Figure 17. If VRT and VRTS are tied together, but VRB is tied to analog ground, a top reference voltage of approximately 2.3V is generated. The top and bottom of the ladder should be bypassed with 10 µF tantalum capacitors located close to the reference pins. The reference self-bias circuit of Figure 17 is very simple and performance is adequate for many applications. Better linearity performance can generally be achieved by driving the reference pins with a low impedance source. By forcing a little current into or out of the top and bottom of the ladder, as shown in Figure 18, the top and bottom reference voltages can be trimmed and performance improved over the self-bias method of Figure 17. The resistive divider at the amplifier inputs can be replaced with potentiometers, if desired. The LMC662 amplifier shown was chosen for its low offset voltage and low cost. Note that a negative power supply is needed for these amplifiers if the lower one is required to go slightly negative to force the required reference voltage. If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of Figure 19 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best performance because of the low source impedance of the transistors. Note that the VRTS and VRBS pins are left floating. To minimize noise effects and ensure accurate conversions, the total reference voltage range (VRT − VRB) should be a minimum of 1.0V and a maximum of about 2.8V. The ADC1175-50 is designed to operate with top and bottom references of 2.6V and 0.6V, respectively. However, it will function with reduced performance with a top reference voltage as high as AVDD and a bottom reference voltage as low as ground. If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of Figure 19 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best performance because of the low source impedance of the transistors. Note that the VRTS and VRBS pins are left floating. VRT can be anywhere between VRB + 1.0V and the analog supply voltage, and VRB can be anywhere between ground and 1.0V below VRT. To minimize noise effects and ensure accurate conversions, the total reference voltage range (VRT - VRB) should be a minimum of 1.0V and a maximum of about 2.8V. If VRB is not required to be below about +700mV, the -5V points in Figure 19 can be returned to ground and the negative supply eliminated. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 15 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Self bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational amplifiers. Figure 18. Better Defining the ADC Reference Voltage. Requires driving with a low impedance source, provided by the transistors. Note that pins 16 and 22 are not connected. Figure 19. Driving the Reference to Force Desired Values 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 OUTPUT DATA TIMING The Output Delay (tOD) of the ADC1175-50 can be very close to one half clock cycle. Because of this, the output data transition occurs very near the falling edge of the ADC clock. To avoid clocking errors, you should use the rising edge of the ADC clock to latch the output data of the ADC1175-50 and not use the falling edge. POWER SUPPLY CONSIDERATIONS Many A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 centimeters) of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed as close as possible to the converter's power supply pins. Leadless chip capacitors are preferred because they have low lead inductance. While a single voltage source should be used for the analog and digital supplies of the ADC1175-50, these supply pins should be isolated from each other to prevent any digital noise from being coupled to the analog power pins. We recommended a wide band choke, such as the JW Miller FB20010-3B, be used between the analog and digital supply lines, with a ceramic capacitor close to the analog supply pin. If a resistor is used in place of the choke, a maximum of 10Ω should be used. The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should be the same supply used for the A/D analog supply. As with all high speed converters, the ADC1175-50 should be assumed to have little a.c. power supply rejection, especially when self biasing is used by connecting VRT and VRTS together. No pin should ever have a voltage on it that is in excess of the supply voltage or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits driving the CLK, PD, analog input and reference pins do not come up any faster than does the voltage at the ADC1175-50 power pins. Pins 11 and 13 are both labeled DVDD. Pin 11 is the supply point for the digital core of the ADC, where pin 13 is used only to provide power to the ADC output drivers. As such, pin 11 may be connected to a voltage source that is less than the +5V used for AVDD and DVDD to ease interfacing to low voltage devices. Pin 11 should never exceed the pin 13 potential by more than 0.5V. THE ADC1175-50 CLOCK Although the ADC1175-50 is tested and its performance is ensured with a 50 MHz clock, it typically will function with clock frequencies from 1 MHz to 55 MHz. The clock should be one of low jitter and close to 50% duty cycle. LAYOUT AND GROUNDING Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog and digital ground planes that are connected beneath the ADC1175-50 may be used, but best EMI practices require a single ground plane. However, it is important to keep analog signal lines away from digital signal lines and away from power supply currents. This latter requirement requires the careful separation and placement of power planes. The use of power traces rather than one or more power planes is not recommended as higher frequencies are not well filtered with lumped capacitances. To filter higher frequency noise components it is necessary to have sufficient capacitance between the power and ground planes. If separate analog and digital ground planes are used, the analog and digital grounds may be in the same layer, but should be separated from each other. If separate analog and digital ground layers are used, they should never overlap each other. Capacitive coupling between a typically noisy digital ground plane and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 17 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS and the 74HC(T) families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F family. In general, slower logic families will produce less high frequency noise than do high speed logic families. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. An effective way to control ground noise is by using a single, solid ground plane and splitting the power plane into analog and digital areas and to have power and ground planes in adjacent board layers. There should be no traces within either the power or the ground layers of the board. The analog and digital power planes should reside in the same board layer so that they can not overlap each other. The analog and digital power planes define the analog and digital areas of the board. Mount digital components and run digital lines only in the digital areas of the board. Mount the analog components and run analog lines only in the analog areas of the board. Be sure to treat all digital lines greater that one inch for each nanosecond of rise time as transmission lines. That is, they should be of constant, controlled impedance, be properly terminated at the source end and run from one point to another single point. The back of the WQFN package has a large metal area inside the area bounded by the pins. This metal area is connected to the die substrate (ground). This pad may be left floating if desired. If it is connected to anything, it should be to ground near the connection between analog and digital ground planes. Soldering this metal pad to ground will help keep the die cooler and could yield improved performance because of the lower impedance between die and board grounds. However, a poor layout could compromise performance. Generally, analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies and at high resolution is obtained with a straight signal path. Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side with each other, not even with just a small part of their bodies beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be connected to a very clean point in the ground plane. DYNAMIC PERFORMANCE The ADC1175-50 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the clock source driving the CLK input must be free of jitter. For best a.c. performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 20. Figure 20. Isolating the ADC Clock from Digital Circuitry 18 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal. COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 50 mV below the ground pins or 50 mV above the supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground due to improper termination. A resistor of about 50Ω to 100Ω in series with the offending digital input, located close to the signal source, will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC1175-50. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to charge for each conversion, the more instantaneous digital current is required from DVDD and DGND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74AC541, for example) may be necessary if the data bus to be driven is heavily loaded. Dynamic performance can also be improved by adding 47Ω series resistors at each digital output, reducing the energy coupled back into the converter output pins. Using an inadequate amplifier to drive the analog input. As explained in Applications Information, the ADC input is a switched capacitor one and there are voltage spikes present there. This type if input is more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. The LMH6702 and the LMH6609 have been found to be an excellent device for driving the ADC1175-50. Also remember to use the RC between the driving source and the ADC input, as explained in THE ANALOG INPUT. Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate as a clock source. Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to noise ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input. Suitable filters are shown in Figure 21 and Figure 22. The circuit of Figure 21 has a cutoff of about 5.5 MHz and is suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 22 has a cutoff of about 11 MHz and is suitable for input frequencies of 5 MHz to 10 MHz. These filters should be driven by a generator of 75Ω source impedance and terminated with a 75Ω resistor. Not considering the effect on a driven CMOS digital circuit(s) when the ADC1175-50 is in the power down mode. Because the ADC1175-50 output goes into a high impedance state when in the power down mode, any CMOS device connected to these outputs will have their inputs floating when the ADC is in power down. Should the inputs of the circuit being driven by the ADC digital outputs float to a level near 2.5V, a CMOS device could exhibit relative large supply currents as the input stage toggles rapidly. The solution is to use pull-down resistors at the ADC outputs. The value of these resistors is not critical, as long as they do not cause excessive currents in the outputs of the ADC1175-50. Low pull-down resistor values could result in degraded SNR and SINAD performance of the ADC1175-50. Values between 5 kΩ and 10 kΩ should work well. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 19 ADC1175-50 SNAS027G – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Use with maximum input frequencies of 1 MHz to 5 MHz. Figure 21. A 5.5 MHz Low Pass filter to eliminate harmonics at the signal input Use with maximum input frequencies of 5 MHz to 10 MHz. Figure 22. An 11 MHz Low Pass filter to eliminate harmonics at the signal input 20 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 ADC1175-50 www.ti.com SNAS027G – JANUARY 2000 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision F (April 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175-50 21 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) ADC1175-50CIMTX/NOPB ACTIVE Package Type Package Pins Package Drawing Qty TSSOP PW 24 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU SN Level-1-260C-UNLIM (4/5) -20 to 75 ADC1175-50 CIMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC1175-50CIMTX/NOP B Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC1175-50CIMTX/NOPB TSSOP PW 24 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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