SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 D D D D D Compatible With IEEE 1194.1-1991 (BTL) Standard TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion During Live Insertion/Withdrawal D D B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination Available in Plastic Quad Flatpack 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 GND B2 GND B3 GND B4 GND B5 GND B6 GND B7 GND AO7 AI8 AO8 GND VCC CLKBA/LEBA OMODE0 OMODE1 VCC OEB OEB GND B8 GND AO2 AI3 AO3 AI4 AO4 LOOPBACK AI5 AO5 AI6 AO6 AI7 GND CLKAB/LEAB IMODE1 IMODE0 BG VCC OEA BG GND BIAS VCC B1 AI2 AO1 AI1 GND VCC RC PACKAGE (TOP VIEW) description The SN74FB2033H is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level A port. The common I/O, open-collector B port operates at backplane transceiver logic (BTL) signal levels. The SN74FB2033H is specifically designed to be compatible with IEEE 1194.1-1991 (BTL) standard. The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer, a D-type flip-flop, or a D-type latch. When configured in the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (CLKAB/LEAB or CLKBA/LEBA). In the latch mode, the clock pins serve as active-high transparent latch enables. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 description (continued) Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the output of the selected A-to-B logic element (prior to inversion) is the B-to-A input. The AO port-enable/-disable control is provided by OEA. When OEA is low or when VCC is less than 2.5 V, the AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels). The B port is controlled by OEB and OEB. If OEB is low, or OEB is high, or when VCC is less than 2.5 V, the B port is inactive. If OEB is high and OEB is low, the B port is active. BG VCC and BG GND are the bias-generator reference inputs. The A-to-B and B-to-A logic elements are active regardless of the state of their associated outputs. The logic elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated outputs are in the high-impedance (AO port) or inactive (B port) states. Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing effects on VOH during a low-to-high transition. The other clamps out ringing below the BTL VOL voltage of 0.75 V. Both of these clamps are active only during AC switching and do not affect the BTL outputs during steady-state conditions. BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected. The SN74FB2033H is characterized for operation from 0°C to 70°C. Function Tables FUNCTION TABLE INPUTS OEA 2 OEB OEB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK FUNCTION/MODE L L X X X X X X L X H X X X X X X H L L L X X X AI to B, buffer mode X H L L H X X X AI to B, flip-flop mode AI to B, latch mode X H L H X X X X H L X X X L L L H X H X X L L L H L X X X L H L H X H X X L H L H L X X X H X L H X H X X H X L H L X X X L L H H X H X X L L H H L X X X L H H H X H X X L H H H L X X X H X H H X H X X H X H H H L X X X X L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Isolation B to AO AO, buffer mode B to AO, AO flip-flop flip flop mode B to AO AO, latch mode AI to AO AO, buffer mode AO flip-flop flip flop mode AI to AO, AI to AO AO, latch mode AI to B, B to AO SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 Function Tables (Continued) ENABLE/DISABLE OUTPUTS INPUTS OEA OEB OEB AO B L X X Hi Z H X X Active X L L Inactive (H) X L H Inactive (H) X H L Active X H H Inactive (H) BUFFER INPUT OUTPUT L H H L LATCH INPUTS OUTPUT CLK/LE DATA H L H H L L X Q0 H LOOPBACK LOOPBACK Q† L B port Point P‡ H † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram). SELECT INPUTS MODE1 SELECTED-LOGIC ELEMENT MODE0 L L Buffer L H Flip-flop H X Latch FLIP-FLOP INPUTS CLK/LE DATA OUTPUT L X Q0 ↑ L H ↑ H L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 functional block diagram OEB OEB OMODE1 OMODE0 CLKAB/LEAB 23 24 21 20 47 1D C1 AI1 40 50 P 1D C1 One of Eight Channels IMODE1 IMODE0 CLKBA/LEBA 46 45 19 1D C1 AO1 OEA 51 Q 1D 43 C1 One of Eight Channels LOOPBACK 4 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B1 SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any B output in the disabled or power-off state,VO . . . . . . . . . . . . . . –0.5 V to 3.5 V Voltage range applied to any output in the high state, VO: A port . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Current applied to any single output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Maximum power dissipation at TA = 55°C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions (see Note 1) VCC, BG VCC BIAS VCC MIN NOM MAX UNIT Supply voltage 4.75 5 5.25 V Supply voltage 4.5 5 5.5 V VIH High level input voltage High-level VIL Low level input voltage Low-level IOH High-level output current IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate B port Except B port B port 1.62 2 0.75 1.47 Except B port 0.8 AO port –3 AO port 24 B port 100 Except B port TA Operating free-air temperature NOTE 1: Unused pins must be held high or low to prevent them from floating. POST OFFICE BOX 655303 2.3 • DALLAS, TEXAS 75265 0 V V mA mA 10 ns/V 70 °C 5 SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 electrical characteristics over recommended operating free-air temperature range PARAMETER VIK TEST CONDITIONS MIN TYP† MAX UNIT –1.2 V 2.85 VCC–1.1 3.4 V 0.33 0.5 VCC = 4.75 V, VCC = 4.75 V to 5.25 V, II = –18 mA IOH = –10 µA VCC = 4 4.75 75 V IOH = –3 mA IOH = –32 mA AO port VCC = 4 4.75 75 V IOL = 20 mA IOL = 55 mA B port VCC = 4 4.75 75 V IOL = 100 mA IOL = 4 mA II Except B port Except B port B port‡ VI = 5.25 V VI = 2.7 V 100 IIH VCC = 0, VCC = 5.25 V, Except B port B port‡ VI = 2.1 V VI = 0.5 V 100 IIL VCC = 0 to 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 0 to 5.25 V, VI = 0.75 V VO = 2.1 V –100 VCC = 2.1 V to 5.25 V, VCC = 2.1 V to 5.25 V, VO = 2.7 V VO = 0.5 V VCC = 0 to 2.1 V, VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V VO = 0.5 V to 2.7 V VCC = 5.25 V, VCC = 5.25 V, VO = 0 IO = 0 VOH AO port VOL IOH IOZH B port IOZL IOZPU AO port IOZPD IOS§ A port ICC Ci All outputs on Co AO port Cio¶ B port per P1194 P1194.0 0 AO port A port AO port AI port and control inputs VI = 0.5 V or 2.5 V VO = 0.5 V or 2.5 V 2.5 2 0.8 0.75 1.1 V 0.5 50 –50 –40 µA µA µA 100 µA 50 µA –50 µA 50 µA –50 µA –80 –150 mA 45 70 mA 5 pF 5 pF VCC = 0 to 4.75 V VCC = 4.75 V to 5.25 V 6 6 pF † All typical values are at VCC = 5 V. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. ¶ Parameter is based on characterization data but is not production tested. live-insertion characteristics over recommended operating free-air temperature range (see Note 2) PARAMETER ICC (BIAS VCC) TEST CONDITIONS VCC = 0 to 4.75 V VCC = 4.75 V to 5.25 V VO B port VCC = 0, VCC = 0, VB = 1 V, IO B port VCC = 0 to 5.25 V, VCC = 0 to 2.2 V, VB = 0 to 2 V, V BIAS VCC = 5 V OEB = 0 to 5 V POST OFFICE BOX 655303 10 1.62 VI (BIAS VCC) = 4.75 V to 5.25 V OEB = 0 to 0.8 V MAX 400 BIAS VCC = 4.5 4 5 V to 5 5.5 5V • DALLAS, TEXAS 75265 UNIT µA 2.1 V 100 µA –1 100 NOTE 2: Power-up sequence is as follows: GND, BIAS VCC, VCC. 6 MIN SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 5 V, TA = 25°C MIN MAX 0 150 MIN MAX UNIT 0 150 MHz fclock tw Clock frequency Pulse duration, CLKAB/LEAB or CLKBA/LEBA 3.3 3.3 ns tsu th Setup time, data before CLKAB/LEAB or CLKBA/LEBA↑ 2.7 2.7 ns Hold time, data after CLKAB/LEAB or CLKBA/LEBA↑ 0.7 0.7 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tr Rise time, 1.3 V to 1.8 V, B port tf tr FROM (INPUT) TO (OUTPUT) AI (thru mode) B B (thru mode) AO AI (transparent) (trans arent) B B (transparent) AO OEB B OEB B OEA AO OEA AO CLKAB/LEAB B CLKBA/LEBA AO OMODE B IMODE AO LOOPBACK AO AI AO VCC = 5 V, TA = 25°C MIN TYP MAX MIN 150 150 MAX MHz 2.8 5.1 6.8 2.8 8.1 2.5 4.2 5.7 2.5 6.1 2.2 4.3 6 2.2 6.6 2.6 4.2 5.6 2.6 6 2.8 5.1 6.8 2.8 8.1 2.6 4.2 5.7 2.6 6.1 2.2 4.3 6 2.2 6.6 2.5 4.2 5.6 2.5 6 2.7 5.1 6.8 2.7 8.3 2.4 4.2 5.7 2.4 6.1 2.5 4.8 6.4 2.5 7.7 2.5 4.3 5.9 2.5 6.4 1.6 3.6 5.1 1.6 5.6 2.3 4.3 5.7 2.3 6 1.7 4 5.5 1.7 5.9 1.2 2.9 4.4 1.2 4.7 3.7 6.5 8.3 3.7 9.9 3.4 5.4 7.1 3.4 7.7 1.7 3.8 5.5 1.7 5.9 1.8 3.6 5.1 1.8 5.5 2.9 6.6 8.4 2.9 10 3 5.7 7.5 3 8.3 1.4 4.1 5.8 1.4 6.4 1.9 4.2 5.7 1.9 5.9 2 5.2 7.3 2 8.2 2.6 4.8 6.3 2.6 6.4 1.7 3.9 5.6 1.7 6.1 2.2 4.3 5.7 2.2 5.9 1.8 2.5 3.8 1.7 4 Fall time, 1.8 V to 1.3 V, B port 1.7 2.5 3.8 1.5 4 Rise time, 10% to 90%, AO 2.5 3.4 4.8 2 5 1.5 2.5 3.8 1 5 tf Fall time, 90% to 10%, AO B-port input pulse rejection 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 output-voltage characteristics PARAMETER VOHP† VOHV† TEST CONDITIONS See Figure 1 MAX Minimum output voltage during turnoff of 100 mA into 40 nH B port See Figure 1 1.62 V B port IOL = –50 mA 0.3 V PARAMETER MEASUREMENT INFORMATION 2.1 V 40 nH 9Ω From Output Under Test 30 pF Figure 1. Load Circuit for VOHP, VOHV POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 UNIT B port VOLV Minimum output voltage during high-to-low switch † Parameter is based on characterization data but not tested. 8 MIN Peak output voltage during turnoff of 100 mA into 40 nH V SN74FB2033H 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472B – MAY 1994 – REVISED JUNE 1996 PARAMETER MEASUREMENT INFORMATION 2.1 V 9Ω 7V 500 Ω From Output Under Test S1 Open CL = 50 pF (see Note A) From Output Under Test Test Point 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR B OUTPUTS tw 3V 1.5 V Timing Input 3V 0V Input tsu 1.5 V 1.5 V th 0V 3V Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control 1.5 V 1.5 V 3V Input 1.5 V 0V tPZL 1.5 V tPLZ 0V tPHL 3.5 V tPLH VOH 1.55 V Output 1.55 V Output S1 at 7 V (see Note B) VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A TO B) 1.5 V 1.55 V VOL tPHZ tPZH VOH Output (see Note B) 2.1 V Input VOL + 0.3 V 1.5 V VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A PORT) 1.55 V 1V tPHL tPLH VOHP VOH Output 1.5 V 2.1 V VOHV 1.5 V VOL 1V VOLV VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B TO A) VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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