SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 D Meets or Exceeds ANSI TIA/EIA-644 SN65LVDS2 DBV PACKAGE (TOP VIEW) Standard D Designed for Signaling Rates up to D D D D D D D D 400 Mbps Operates From a 2.4-V to 3.6-V Supply Available in the SOT-23 Package Differential Input Voltage Threshold Less Than 100 mV Propagation Delay Times, 2.5 ns Typical Power Dissipation at 200 MHz Is Typically 60 mW Bus-Pin ESD Protection Exceeds 15 kV Open-Circuit Fail Safe Output is High Impedance With VCC < 1.5 V VCC 1 GND 2 A 3 5 R 4 B logic diagram A 3 5 B R 4 Function Table description The SN65LVDS2 is a single low-voltage differential line receiver in a small-outline transistor package. The inputs comply with the TIA/EIA-644 standard and provide a maximum differential input threshold of 100 mV over an input common-mode voltage range of 0 V to 2.4 V. INPUTS OUTPUT VID = VA – VB R VID ≥ 100 mV H –100 mV < VID < 100 mV ? VID ≤ –100 mV L Open H When used with a low-voltage differential signaling (LVDS) driver (such as the SN65LVDS1) H = high level, L = low level , ? = indeterminate in a point-to-point or multidrop configuration; data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The high-speed switching of LVDS signals requires the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. TI offers you both the SN65LVDS2, which requires this external resistor, or its companion the SN65LVDT2, which eliminates the need by integrating it with the receiver. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make these devices ideal for battery-powered applications. The SN65LVDS2 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 equivalent input and output schematic diagrams VCC VCC 300 kΩ 300 kΩ 5Ω A Input R Output B Input 7V 7V 7V absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Voltage range (A, B, or R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+ 0.5 V Electrostatic discharge: A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . CLass 3, A:15 kV, B:600 V R (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLass 3, A:7 kV, B:500 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C† TA = 85°C POWER RATING DBV 385 mW 3.1 mW/°C 200 mW † This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with no air flow. recommended operating conditions MIN NOM Supply voltage, VCC 2.4 3.3 Magnitude of differential input voltage, VID 0.1 0 Common mode in ut voltage, VIC (see Figure 6) Common–mode input Operating free–air temperature, TA 2 –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 3.6 V 0.6 V 2.4 * ŤVIDŤ 2 VCC–0.8 85 V °C SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE VIC – Common-Mode Input Voltage – V 3 2.5 VCC = 3.6 V 2 VCC = 2.7 V 1.5 VCC = 2.4 V 1 0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 |VID|– Differential Input Voltage – V Figure 1. VIC vs VID and VCC electrical characteristics over recommended operating conditions, VCC = 2.4 to 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS VITH+ VITH– Positive-going differential input voltage threshold VOH VOL High-level output voltage Low-level output voltage IOH = –8 mA IOL = 8 mA ICC Supply current No load, Steady state II Input current (A or B inputs) VI = 0 V VI = 2.4 V or VCC – 0.8 IID Differential input current (IIA – IIB) VIA = 0 V, VIB = 0.1 V VIA = 2.4 V VIB = 2.3 V, Negative-going differential input voltage threshold II(OFF) Power-off input current (A or B inputs) † All typical values are at 25°C and with a 2.7-V supply. MIN TYP† MAX UNIT 100 See Figure 2 and Table 1 VCC = 0 V, mV –100 1.9 2.4 V 0.25 0.4 4 7 ±20 –1.2 VI = 2.4 V V mA µA A ±2 µA ±20 µA receiver switching characteristics over recommended operating conditions, VCC = 2.4 to 2.7 V (unless otherwise noted) MIN TYP† MAX Propagation delay time, low-to-high-level output 1.4 2.6 3.6 ns Propagation delay time, high-to-low-level output Pulse skew (|tpHL – tpLH|)‡ 1.4 2.5 3.6 ns 0.1 0.6 ns 0.8 1.4 ns 1.4 ns PARAMETER tPLH tPHL tsk(p) tr TEST CONDITIONS CL = 10 pF, F See Figure 3 Output signal rise time tf Output signal fall time 0.8 † All typical values are at 25°C and with a 2.7-V. ‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 3 SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 electrical characteristics over recommended operating conditions, VCC = 3 V to 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VITH+ VITH– Positive-going differential input voltage threshold VOH VOL High-level output voltage Low-level output voltage IOH = –8 mA IOL = 8 mA ICC Supply current No load, Steady state II Input current (A or B inputs) VI = 0 V VI = 2.4 V IID Differential input current (IIA – IIB) VIA = 0 V, VIB = 0.1 V VIA = 2.4 V VIB = 2.3 V, ±2 µA VCC = 0 V, 20 µA Negative-going differential input voltage threshold II(OFF) Power-off input current (A or B inputs) † All typical values are at 25°C and with a 3.3-V supply. 100 See Figure 2 and Table 1 mV –100 2.4 3 V 0.25 0.4 5 8 ±20 –1.2 VI = 2.4 V V mA µA receiver switching characteristics over recommended operating conditions, VCC = 3 V to 3.6 V (unless otherwise noted) MIN TYP† MAX Propagation delay time, low-to-high-level output 1.4 2.6 3.1 ns Propagation delay time, high-to-low-level output Pulse skew (|tpHL – tpLH|)‡ 1.4 2.5 3.1 ns 0.1 0.5 ns 0.7 1.1 ns 1.1 ns PARAMETER tPLH tPHL tsk(p) tr TEST CONDITIONS CL = 10 pF, F See Figure 3 Output signal rise time tf Output signal fall time 0.7 † All typical values are at 25°C and with a 3.3-V. ‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION A V V IA IB R VID 2 VIA B VIC VO VIB Figure 2. Receiver Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMONMODE INPUT VOLTAGE (V) VIA 1.25 VIB 1.15 VID 100 VIC 1.2 1.15 1.25 – 100 1.2 2.4 2.3 100 2.35 2.3 2.4 – 100 2.35 0.1 0 100 0.05 0 0.1 – 100 0.05 1.5 0.9 600 1.2 0.9 1.5 – 600 1.2 2.4 1.8 600 2.1 1.8 2.4 – 600 2.1 0.6 0 600 0.3 0 0.6 – 600 0.3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V – 0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf VO With VCC = 3.3 V tr VOH 80% 1.2 V 20% With VCC = 2.7 V VOL tf tr NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 3. Timing Test Circuit and Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 TYPICAL CHARACTERISTICS 3.5 3 2.5 VCC = 3.3 V 2 1.5 VCC = 2.7 V 1 0.5 0 –70 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 VOL – Low-Level Output Voltage – V VOH – High-Level Output Voltage – V 4 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 3 2.5 VCC = 2.7 V 2 1.5 VCC = 3.3 V 1 0.5 0 –60 – 50 – 40 – 30 – 20 – 10 0 0 IOH – High-Level Output Current – mA 10 20 30 2.85 VCC = 2.4 V 2.8 VCC = 3.6 V 2.7 VCC = 3.3 V 2.6 VCC = 3 V 2.55 VCC = 2.7 V 2.45 2.4 –40 –20 0 20 40 60 80 t PLH – Low-to-High Level Propagation Delay Time – ns t PHL – High-to-Low Level Propagation Delay Time – ns 2.9 2.5 60 70 Figure 5 HIGH-TO-LOW LEVEL PROPAGATION DELAY TIMES vs FREE-AIR TEMPERATURE 2.65 50 IOL – Low-Level Output Current – mA Figure 4 2.75 40 LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3 VCC = 2.4 V 2.9 2.8 2.7 VCC = 3.3 V VCC = 3.6 V 2.6 2.5 2.4 VCC = 3 V VCC = 2.7 V 2.3 2.2 –40 –20 TA – Free-Air Temperature – °C 0 20 40 60 80 100 TA – Free-Air Temperature – °C Figure 6 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 10. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 8. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS406 – DECEMBER 1999 MECHANICAL INFORMATION DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,50 0,30 0,95 5 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0°–8° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/E 05/99 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. 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