TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 D D D D D D D D D Low Power Consumption Wide Common-Mode and Differential Voltage Ranges Low Input Bias and Offset Currents Output Short-Circuit Protection Low Total Harmonic Distortion . . . 0.003% Typ High Input Impedance . . . JFET-Input Stage Latch-Up-Free Operation High Slew Rate . . . 13 V/µs Typ Common-Mode Input Voltage Range Includes VCC+ description The TL08x JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. Offset adjustment and external compensation options are available within the TL08x family. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from – 40°C to 85°C. The Q-suffix devices are characterized for operation from – 40°C to 125°C. The M-suffix devices are characterized for operation over the full military temperature range of – 55°C to 125°C. symbols TL081 TL082 (EACH AMPLIFIER) TL084 (EACH AMPLIFIER) OFFSET N1 IN + + IN – – OUT IN + + IN – – OUT OFFSET N2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TL081M U PACKAGE TL082M U PACKAGE (TOP VIEW) (TOP VIEW) NC OFFSET N1 IN– IN+ VCC– 1 10 2 9 3 8 4 7 5 6 NC NC VCC+ OUT OFFSET N2 NC 1OUT 1IN– 1IN+ VCC– TL081, TL081A, TL081B D, JG, P, OR PW PACKAGE (TOP VIEW) OFFSET N1 IN – IN + VCC – 1 8 2 7 3 6 4 5 1OUT 1IN – 1IN + VCC – 6 16 7 15 8 14 9 10 11 12 13 14 2 13 3 12 4 11 5 10 6 9 7 8 6 1 8 2 7 3 6 4 5 VCC + 2OUT 2IN – 2IN + NC 1OUT NC VCC+ NC 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC 2OUT NC 2IN – NC TL084M . . . FK PACKAGE (TOP VIEW) 4OUT 4IN – 4IN + VCC – 3IN + 3IN – 3OUT 1IN – 1OUT NC 4OUT 4IN – 1IN + NC VCC + NC 2IN + NC – No internal connection 2 7 5 POST OFFICE BOX 655303 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2IN – 2OUT NC 3OUT 3IN – 1 8 4 4 TL084, TL084A, TL084B D, J, N, PW, OR W PACKAGE (TOP VIEW) 1OUT 1IN – 1IN + VCC + 2IN + 2IN – 2OUT 3 NC VCC+ 2OUT 2IN– 2IN+ NC VCC – NC 2IN + NC 17 NC VCC + NC OUT NC NC 1IN – NC 1IN + NC NC VCC – NC OFFSET N2 NC 5 9 TL082M . . . FK PACKAGE (TOP VIEW) NC OFFSET N1 NC NC NC TL081M . . . FK PACKAGE (TOP VIEW) NC IN – NC IN + NC 10 2 TL082, TL082A, TL082B D, JG, P, OR PW PACKAGE (TOP VIEW) NC VCC + OUT OFFSET N2 3 2 1 20 19 18 4 1 • DALLAS, TEXAS 75265 4IN + NC VCC – NC 3IN + AVAILABLE OPTIONS PACKAGED DEVICES TA 0°C to 70°C SMALL OUTLINE (D008) SMALL OUTLINE (D014) CHIP CARRIER (FK) CERAMIC DIP (J) CERAMIC DIP (JG) PLASTIC DIP (N) PLASTIC DIP (P) 15 mV 6 mV 3 mV TL081CD TL081ACD TL081BCD — — — — TL081CP TL081ACP TL081BCP TL081CPW — 15 mV 6 mV 3 mV TL082CD TL082ACD TL082BCD — — — — TL082CP TL082ACP TL082BCP TL082CPW — 15 mV 6 mV 3 mV — TL084CD TL084ACD TL084BCD — — — TL084CN TL084ACN TL084BCN — — — — – 40°C to 85°C 6 mV 6 mV 6 mV – 40°C to 125°C 9 mV – 55°C to 125°C 6 mV 6 mV 9 mV TL081ID TL082ID TL084ID TL084ID — FLAT PACK (W) — — — — — — — — — — — — — TL082Y TL084CPW TL081IP TL082IP CHIP FORM (Y) FLAT PACK (U) TSSOP (PW) TL084Y TL084IN — — — — — — — TL081MJG TL082MJG — — — TL081MU TL082MU TL084QD — — TL081MFK TL082MFK TL084MFK TL084MJ The D package is available taped and reeled. Add R suffix to the device type (e.g., TL081CDR). — TL084MW SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 3 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VIOmax AT 25°C TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 schematic (each amplifier) VCC + IN + 64 Ω IN – OUT 128 Ω 64 Ω C1 1080 Ω 1080 Ω VCC – OFFSET N1 OFFSET N2 TL081 Only Component values shown are nominal. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TL082Y chip information These chips, when properly assembled, display characteristics similar to the TL082. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (7) (6) VCC+ (8) (5) 1IN + (3) (2) 1IN – 2OUT (7) + (1) 1OUT – + – 61 (8) (5) (6) 2IN + 2IN – (4) (4) VCC – CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS. (1) (2) (3) PIN (4) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. 61 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TL084Y chip information These chips, when properly assembled, display characteristics similar to the TL084. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS 1IN + (3) (2) (13) (12) (11) (10) (9) 1IN – 2OUT 3IN + 62 (14) (8) (1) (7) + (10) 3IN – (14) (1) 1OUT – (5) + (7) (9) 4OUT VCC+ (4) (6) – + 2IN + 2IN – (8) 3OUT – + – (12) (13) 4IN + 4IN – (11) VCC – (2) (3) (4) (6) CHIP THICKNESS: 15 TYPICAL 105 BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS. PIN (11) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† TL08_C TL08_AC TL08_BC Supply voltage, VCC + (see Note 1) TL08_I TL084Q TL08_M UNIT 18 18 18 18 V Supply voltage VCC – (see Note 1) – 18 – 18 – 18 – 18 V Differential input voltage, VID (see Note 2) ± 30 ± 30 ± 30 ± 30 V V Input voltage, VI (see Notes 1 and 3) Duration of output short circuit (see Note 4) ± 15 ± 15 ± 15 ± 15 unlimited unlimited unlimited unlimited 0 to 70 – 40 to 85 – 40 to 125 – 55 to 125 °C – 65 to 150 – 65 to 150 – 65 to 150 – 65 to 150 °C Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA Storage temperature range, Tstg Case temperature for 60 seconds, TC FK package 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or JG package 300 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D, N, P, or PW package 260 260 °C 260 † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC + and VCC – . 2. Differential voltages are at IN+ with respect to IN –. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR DERATE ABOVE TA TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D (8 pin) 680 mW 5.8 mW/°C 32°C 460 mW 373 mW N/A D (14 pin) 680 mW 7.6 mW/°C 60°C 604 mW 490 mW 186 mW FK 680 mW 11.0 mW/°C 88°C 680 mW 680 mW 273 mW J 680 mW 11.0 mW/° C 88°C 680 mW 680 mW 273 mW JG 680 mW 8.4 mW/°C 69°C 672 mW 546 mW 210 mW N 680 mW 9.2 mW/°C 76°C 680 mW 597 mW N/A P 680 mW 8.0 mW/°C 65°C 640 mW 520 mW N/A PW (8 pin) 525 mW 4.2 mW/°C 25°C 336 mW N/A N/A PW (14 pin) 700 mW 5.6 mW/°C 25°C 448 mW N/A N/A U 675 mW 5.4 mW/°C 25°C 432 mW 351 mW 135 mW W 680 mW 8.0 mW/°C 65°C 640 mW 520 mW 200 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MIN VIO Input offset voltage VO = 0 RS = 50 Ω α VIO Temperature coefficient of input offset voltage VO = 0 RS = 50 Ω IIO Input offset current ‡ VO = 0 IIB Input bias current ‡ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VICR Common-mode input voltage range VOM Maximum M i peak k out ut voltage swing output AVD Large-signal differential voltage amplification B1 Unity-gain bandwidth 25°C TYP MAX 3 15 Full range Full range 18 25°C 5 200 30 400 Full range RL ≥ 10 kΩ 6 25°C ± 11 25°C ± 12 ± 13.5 MIN ± 12 MAX 2 3 100 30 200 100 30 200 ± 13.5 ± 12 MAX 3 6 pA 10 nA 30 200 pA 20 nA 7 ± 11 ± 11 – 12 to 15 ± 12 ± 13.5 ± 12 ± 13.5 V ± 12 ± 10 ± 12 ± 10 ± 12 ± 10 ± 12 200 50 200 50 200 50 200 RL ≥ 2 kΩ 25°C 25 VO = ± 10 V, RL ≥ 2 kΩ Full range 15 V ± 12 ± 10 VO = ± 10 V, µV/°C 100 – 12 to 15 ± 12 mV 5 2 7 ± 12 TYP 18 5 2 UNIT 9 18 5 ± 11 MIN 5 18 – 12 to 15 TL081I TL082I TL084I TYP 7.5 10 – 12 to 15 Full range RL ≥ 2 kΩ MAX 3 2 25°C RL = 10 kΩ TYP 20 Full range VO = 0 MIN TLO81BC TL082BC TL084BC V/mV 25 25 25 25°C 3 3 3 3 25°C 1012 1012 1012 1012 MHz Ω ri Input resistance CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω 25°C 70 86 75 86 75 86 75 86 dB kSVR Supply voltage rejection ratio (∆ VCC± /∆ VIO) VCC = ± 15 V to ± 9 V, VO = 0, RS = 50 Ω 25°C 70 86 80 86 80 86 80 86 dB ICC Supply current (per amplifier) VO = 0, 25°C No load 1.4 2.8 1.4 2.8 1.4 2.8 1.4 2.8 mA VO1/ VO2 Crosstalk attenuation AVD = 100 25°C 120 120 120 120 dB † All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. Full range for TA is 0°C to 70°C for TL08_C, TL08_AC, TL08_BC and – 40°C to 85°C for TL08_I. ‡ Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 17. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. Template Release Date: 7–11–94 TEST CONDITIONS TL081AC TL082AC TL084AC TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS PARAMETER TL081C TL082C TL084C TA† SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 8 electrical characteristics, VCC± = ±15 V (unless otherwise noted) TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 electrical characteristics, VCC ± = ± 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA VIO Input offset voltage VO = 0 0, RS = 50 Ω αVIO Temperature coefficient of input offset voltage VO = 0 RS = 50 Ω IIO Input offset current‡ VO = 0 IIB Input bias current‡ VO = 0 VICR Common-mode input voltage range VOM Maximum M i peak k out ut voltage swing output AVD Large-signal differential voltage amplification B1 ri CMRR kSVR ICC TL081M, TL082M TL084Q, TL084M MIN MIN 25°C TYP MAX 3 6 Full range 18 25°C 5 30 100 RL ≥ 2 kΩ 30 50 25°C ± 11 25°C ± 12 ± 13.5 Full range 5 200 125°C ± 12 to 15 9 15 20 25°C MAX ± 12 ± 11 ± 12 to 15 ± 12 ± 13.5 UNIT mV µV/°C 18 125°C RL ≥ 10 kΩ 3 9 Full range RL = 10 kΩ TYP 100 pA 20 nA 200 pA 50 nA V ± 12 V ± 10 ± 12 ± 10 ± 12 VO = ± 10 V, RL ≥ 2 kΩ 25°C 25 200 25 200 VO = ± 10 V, RL ≥ 2 kΩ Full range 15 V/mV Unity-gain bandwidth 25°C Input resistance 25°C 15 3 1012 3 1012 MHz Ω Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω 25°C 80 86 80 86 dB Supply voltage rejection ratio (∆VCC ± /∆VIO) Supply current (per amplifier) VCC = ± 15 V to ± 9 V, VO = 0, RS = 50 Ω 25°C 80 86 80 86 dB VO = 0, 25°C No load 1.4 2.8 1.4 2.8 mA VO1/ VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB † All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. ‡ Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 17. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as is possible. operating characteristics, VCC± = ± 15 V, TA = 25°C (unless otherwise noted) PARAMETER SR Slew rate at unity gain tr Rise time Overshoot factor TEST CONDITIONS VI = 10 V, RL = 2 kΩ, CL = 100 pF, VI = 10 V, TA = – 55°C to 125°C, RL = 2 kΩ, See Figure 1 CL = 100 pF, mV VI = 20 mV, RL = 2 kΩ kΩ, pF CL = 100 pF, See Figure 1 Equivalent input in ut noise voltage RS = 20 Ω In Equivalent input noise current RS = 20 Ω, f = 1 kHz THD Total harmonic distortion VIrms = 6 V, f = 1 kHz AVD = 1, TYP 8∗ 13 See Figure 1 f = 10 Hz to 10 kHz 0.05 RL ≥ 2 kΩ, UNIT µs 20% 18 nV/√Hz 4 µV 0.01 RS ≤ 1 kΩ, MAX V/µs 5∗ f = 1 kHz Vn MIN pA/√Hz 0.003% ∗On products compliant to MIL-PRF-38535, this parameter is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 electrical characteristics, VCC± = ± 15 V, TA = 25°C (unless otherwise noted) TEST CONDITIONS† PARAMETER VIO Input offset voltage α VIO Temperature coefficient of input offset voltage Input offset current‡ IIO IIB VO = 0, VO = 0, TYP MAX RS = 50 Ω 3 15 RS = 50 Ω 18 VO = 0, VO = 0, Input bias current‡ VICR Common-mode input voltage range VOM AVD Maximum peak output voltage swing RL = 10 kΩ, Large-signal differential voltage amplification VO = ± 10 V, B1 Unity-gain bandwidth ri TL082Y, TL084Y MIN RL ≥ 2 kΩ 5 200 pA 30 400 pA ± 11 – 12 to 15 V ± 12 ± 13.5 V 25 200 V/mV 3 MHz Input resistance Common mode rejection ratio Common-mode VIC = VICRmin,, RS = 50 Ω VO = 0,, kSVR Supply voltage rejection ratio (∆VCC± /∆VIO) VCC = ± 15 V to ± 9 V,, VO = 0, RS = 50 Ω mV µV/°C Ω 1012 CMRR UNIT 70 86 70 86 70 86 70 86 dB dB ICC Supply current (per amplifier) VO = 0, No load 1.4 2.8 mA VO1/ VO2 Crosstalk attenuation AVD = 100 120 dB † All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. ‡ Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 17. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. operating characteristics, VCC± = ± 15 V, TA = 25°C PARAMETER SR Slew rate at unity gain tr Rise time Overshoot factor TEST CONDITIONS VI = 10 V, RL = 2 kΩ, CL = 100 pF, See Figure 1 VI = 20 mV, mV RL = 2 kΩ kΩ, CL = 100 pF, pF See Figure 1 f = 1 kHz Vn Equivalent input noise voltage RS = 20 Ω In Equivalent input noise current RS = 20 Ω, f = 1 kHz THD Total harmonic distortion VIrms = 6 V, f = 1 kHz AVD = 1, 10 TYP 8 13 0.05 4 0.01 RS ≤ 1 kΩ, • DALLAS, TEXAS 75265 RL ≥ 2 kΩ, MAX UNIT V/ µs µs 20% 18 f = 10 Hz to 10 kHz POST OFFICE BOX 655303 MIN 0.003% nV/√Hz µV pA/√Hz TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION 10 kΩ – 1 kΩ VI + OUT CL = 100 pF RL = 2 kΩ + CL = 100 pF RL Figure 1 Figure 2 100 kΩ TL081 IN – IN + + C2 – OUT C1 500 pF N2 N1 100 kΩ N1 OUT + IN – – VI – OUT 1.5 kΩ VCC – Figure 3 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Maximum peak output voltage vs Frequency vs Free-air temperature vs Load resistance vs Supply voltage 5, 6, 7 8 9 10 Large signal differential voltage amplification Large-signal vs Free-air temperature vs Frequency 11 12 Differential voltage amplification vs Frequency with feed-forward compensation 13 Total power dissipation vs Free-air temperature 14 ICC Supply current vs Free-air temperature vs Supply voltage 15 16 IIB Input bias current vs Free-air temperature 17 VOM AVD PD Large-signal pulse response vs Time 18 VO CMRR Output voltage vs Elapsed time 19 Common-mode rejection ratio vs Free-air temperature 20 Vn THD Equivalent input noise voltage vs Frequency 21 Total harmonic distortion vs Frequency 22 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUENCY MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUENCY ± 15 VCC ± = ± 15 V RL = 10 kΩ TA = 25°C See Figure 2 ± 12.5 ± 10 VCC ± = ± 10 V ± 7.5 VCC ± = ± 5 V ±5 ± 2.5 VOM – Maximum Peak Output Voltage – V VOM – Maximum Peak Output Voltage – V ± 15 VCC ± = ± 15 V ± 12.5 ± 10 VCC ± = ± 10 V ± 7.5 ±5 VCC ± = ± 5 V ± 2.5 0 0 100 1k 10 k 100 k 1M 10 M 100 f – Frequency – Hz 1k 10 k Figure 6 POST OFFICE BOX 655303 100 k f – Frequency – Hz Figure 5 12 RL = 2 kΩ TA = 25°C See Figure 2 • DALLAS, TEXAS 75265 1M 10 M TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS† MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUENCY MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE ± 12.5 RL = 10 kΩ VCC ± = ± 15 V RL = 2 kΩ See Figure 2 TA = 25°C ± 10 TA = – 55°C ± 7.5 ±5 TA = 125°C ± 2.5 0 10 k ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ± 15 VOM – Maximum Peak Output Voltage – V VOM – Maximum Peak Output Voltage – V ± 15 40 k 100 k 400 k 1M 4M ± 12.5 RL = 2 kΩ ± 10 ± 7.5 ±5 ± 2.5 VCC ± = ± 15 V See Figure 2 0 – 75 – 50 10 M – 25 75 100 125 ± 15 ± 15 VCC ± = ± 15 V TA = 25°C See Figure 2 VOM – Maximum Peak Output Voltage – V VOM – Maximum Peak Output Voltage – V 50 MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE RL = 10 kΩ TA = 25°C ± 12.5 ± 10 ± 7.5 ±5 ± 2.5 0 0.1 25 Figure 8 Figure 7 ± 12.5 0 TA – Free-Air Temperature – °C f – Frequency – Hz ± 10 ± 7.5 ±5 ± 2.5 0 0.2 0.4 0.7 1 2 4 7 10 0 2 4 6 8 10 12 14 16 | VCC ± | – Supply Voltage – V RL – Load Resistance – kΩ Figure 10 Figure 9 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS† LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE 1000 700 AVD – Large-Signal Differential Voltage Amplification – V/mV 400 200 100 70 40 20 10 7 VCC ± = ± 15 V VO = ± 10 V RL = 2 kΩ 4 2 1 – 75 – 50 – 25 0 25 50 75 100 125 TA – Free-Air Temperature – °C Figure 11 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREQUENCY 106 VCC ± = ± 5 V to ± 15 V RL = 10 kΩ TA = 25°C 104 Differential Voltage Amplification (left scale) 103 0° 45 ° 90 ° 102 Phase Shift (right scale) 101 135 ° 1 1 10 100 1k Phase Shift AVD – Large-Signal Differential Voltage Amplification – V/mV 105 10 k 100 k 1M 180 ° 10 M f – Frequency – Hz Figure 12 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS† DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREQUENCY WITH FEED-FORWARD COMPENSATION TOTAL POWER DISSIPATION vs FREE-AIR TEMPERATURE 250 VCC ± = ± 15 V C2 = 3 pF TA = 25°C See Figure 3 105 104 103 102 10 1 100 1k 10 k 100 k 1M VCC ± = ± 15 V No Signal No Load 225 PD – Total Power Dissipation – mW AVD – Differential Voltage Amplification – V/mV 106 200 175 TL084, TL085 150 125 100 TL082, TL083 75 TL081 50 25 0 – 75 10 M – 50 – 25 f – Frequency With Feed-Forward Compensation – Hz SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE 50 75 100 125 SUPPLY CURRENT vs SUPPLY VOLTAGE 2.0 2.0 VCC ± = ± 15 V No Signal No Load 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 TA = 25°C No Signal No Load 1.8 I CC ± – Supply Current – mA I CC ± – Supply Current – mA 25 Figure 14 Figure 13 0 –75 0 TA – Free-Air Temperature – °C 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 – 50 – 25 0 25 50 75 100 125 0 0 2 TA – Free-Air Temperature – °C 4 6 8 10 12 14 16 | VCC ± | – Supply Voltage – V Figure 16 Figure 15 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS† INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE 6 100 VCC ± = ± 15 V RL = 2 k Ω CL = 100 pF TA = 25°C Input and Output Voltages – V I IB – Input Bias Current – nA V CC ± = ± 15 V 10 1 0.1 4 Output 2 0 –2 Input –4 0.01 – 50 –6 – 25 0 25 50 75 100 125 0 0.5 TA – Free-Air Temperature – °C CMRR – Common-Mode Rejection Ratio – dB 89 VO – Output Voltage – mV 24 20 VCC ± = ± 15 V RL = 2 k Ω CL = 100 pF TA = 25°C See Figure 1 4 0 –4 0 0.2 0.4 2.5 3 0.6 0.8 1.0 1.2 VCC ± = ± 15 V RL = 10 kΩ 88 87 86 85 84 83 – 75 – 50 t – Elapsed Time – µ s – 25 0 25 50 75 100 TA – Free-Air Temperature – °C Figure 20 Figure 19 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 16 3.5 COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE 28 8 2 Figure 18 OUTPUT VOLTAGE vs ELAPSED TIME 12 1.5 t – Time – µ s Figure 17 16 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS† EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 1 VCC ± = ± 15 V AVD = 10 RS = 20 Ω TA = 25°C 40 30 20 10 0.1 0.04 0.01 0.004 0.001 0 10 40 100 400 1 k 4 k 10 k VCC ± = ± 15 V AVD = 1 VI(RMS) = 6 V TA = 25°C 0.4 THD – Total Harmonic Distortion – % Vn – Equilvalent Input Noise Voltage – nV/ Hz 50 40 k 100 k 10 400 1k 4k 10 k 40 k 100 k f – Frequency – Hz f – Frequency – Hz Figure 22 Figure 21 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. APPLICATION INFORMATION RF = 100 kΩ VCC + – Output – TL081 + CF = 3.3 µF Input R1 R2 C3 TL081 + 15 V 3.3 kΩ Output VCC – 1 kΩ – 15 V R1 = R2 = 2(R3) = 1.5 MΩ R3 3.3 kΩ f= C1 9.1 kΩ 1 2π RF CF Figure 23 C2 C1 = C2 = C3 = 110 pF 2 1 = 1 kHz fo = 2π R1 C1 Figure 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 APPLICATION INFORMATION VCC + 1 MΩ – TL084 VCC + Output A + + 1 µF TL084 VCC + – Input – TL084 100 kΩ 100 kΩ 100 µF Output B + 100 kΩ VCC + VCC + 100 kΩ – TL084 Output C + Figure 25. Audio-Distribution Amplifier 6 sin ωt 1N4148 – 15 V 18 pF 18 pF 1 kΩ 18 kΩ (see Note A) VCC + – 1/2 TL082 + 88.4 kΩ VCC+ – 88.4 kΩ 1/2 TL082 VCC – 6 cos ωt + 18 pF VCC – 1 kΩ 15 V 1N4148 88.4 kΩ 18 kΩ (see Note A) NOTE A: These resistor values may be adjusted for a symmetrical output. Figure 26. 100-KHz Quadrature Oscillator 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 APPLICATION INFORMATION 16 kΩ 16 kΩ 220 pF 220 pF 30 kΩ VCC + 43 kΩ 43 kΩ 1/4 TL084 VCC + VCC + 43 kΩ 1/4 TL084 1/4 TL084 + + + 1.5 kΩ + – 1/4 TL084 220 pF VCC + – Input 220 pF 30 kΩ – 43 kΩ 43 kΩ 1.5 kΩ VCC – – 43 kΩ VCC – VCC – Output B VCC – Output A Output A Output B 2 kHz/div Second-Order Bandpass Filter fo = 100 kHz, Q = 30, GAIN = 4 2 kHz/div Cascaded Bandpass Filter fo = 100 kHz, Q = 69, GAIN = 16 Figure 27. Positive-Feedback Bandpass Filter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 20 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 B A MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE 14 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) A MIN 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) B MAX 0.785 (19,94) 0.785 (19,94) 0.910 (23,10) 0.975 (24,77) B MIN 0.755 (19,18) 0.755 (19,18) C MAX 0.300 (7,62) 0.300 (7,62) 0.300 (7,62) 0.300 (7,62) C MIN 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) DIM B 14 8 C 1 7 0.065 (1,65) 0.045 (1,14) 0.100 (2,54) 0.070 (1,78) 0.020 (0,51) MIN 0.930 (23,62) A 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.100 (2,54) 0°–15° 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20) 4040083/D 08/98 NOTES: A. B. C. D. E. 22 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE 0.400 (10,20) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.063 (1,60) 0.015 (0,38) 0.100 (2,54) 0°–15° 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23.37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21.59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0°– 15° 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.) 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0°– 15° 0.010 (0,25) M 0.010 (0,25) NOM 4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX 0,10 PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. 26 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA U (S-GDFP-F10) CERAMIC DUAL FLATPACK 0.250 (6,35) 0.246 (6,10) 0.006 (0,15) 0.004 (0,10) 0.080 (2,03) 0.050 (1,27) 0.045 (1,14) 0.026 (0,66) 0.300 (7,62) 0.350 (8,89) 0.250 (6,35) 1 0.350 (8,89) 0.250 (6,35) 10 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.250 (6,35) 5 6 0.025 (0,64) 0.005 (0,13) 1.000 (25,40) 0.750 (19,05) 4040179 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999 MECHANICAL DATA W (R-GDFP-F14) CERAMIC DUAL FLATPACK Base and Seating Plane 0.260 (6,60) 0.235 (5,97) 0.007 (0,18) 0.004 (0,10) 0.080 (2,03) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.280 (7,11) 0.255 (6,48) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 14 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.390 (9,91) 0.335 (8,51) 0.025 (0,64) 0.015 (0,38) 7 8 1.000 (25,40) 0.735 (18,67) 4040180-2 / B 03/95 NOTES: A. B. C. D. E. 28 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated