P2008A July 2005 rev 1.3 General Purpose EMI Reduction IC Features number of circuit board layers ferrite beads, shielding and other passive components that are traditionally FCC approved method of EMI attenuation. Provides up to 15dB of EMI suppression. Generates a 1X or ½ X low EMI spread spectrum required to pass EMI regulations. clock of the input frequency. The P2008A uses the most efficient and optimized modulation profile approved by the FCC and is Input frequency range: 4MHz to 32MHz. Internal loop filter minimizes external components Spreading ranges from ±0.8% to ±3.2%. SSON# control pin for spread spectrum enable and board space. implemented in a proprietary all digital method. The P2008A modulates the output of a single PLL in and disable options. order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system Low Cycle-to-Cycle jitter. 3.3V Operating Voltage. Ultra-low power CMOS design. Available in 8-pin SOIC and TSSOP Packages. EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering Product Description EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. Applications The P2008A is a versatile spread spectrum frequency modulator designed specifically for digital camera and The P2008A is targeted towards cable, xDSL, fax other digital video and imaging applications. The P2008A modem, set-top box, USB controller, DSC, and other reduces electromagnetic interference (EMI) at the clock embedded systems. source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The P2008A allows significant system cost savings by reducing the VDD Block Diagram DIV2 SR0 SSON# PLL Modulation XIN/CLKIN Crystal Oscillator Frequency Divider XOUT Feedback Divider Phase Detector Loop Filter VCO Output Divider ModOUT VSS Alliance Semiconductor 2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. P2008A July 2005 rev 1.3 Pin Configuration XIN/ CLKIN 1 XOUT 2 DIV2 VSS 8 VDD 7 SR0 3 6 ModOUT 4 5 SSON# P2008A Pin Description Pin# Pin Name Type Description Crystal connection or external reference frequency input. This pin has dual functions. It can be connected either to an external crystal or an external reference clock. Crystal connection. If using an external reference, this pin must be left unconnected. Digital logic input used to select normal output mode or divide-by-two output mode. When this pin is HIGH, the frequency of the output clock is the same as the input clock frequency. When it is tied low, the output frequency is half the input clock frequency. This pin has an internal pull-up resistor. 1 XIN/CLKIN I 2 XOUT O 3 DIV2 I 4 VSS P Ground to entire chip. Connect to system ground. 5 SSON# I Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor. 6 ModOUT O Spread spectrum clock output. 7 SR0 I Digital logic input used to select Spreading Range (Refer Modulation Output and Spreading Range Selection Table.) This pin has an internal pull-up resistor. 8 VDD P Power supply for the entire chip Modulation Output and Spreading Selection (ModOUT = XIN/CLKIN) Output Frequency Range DIV2 = 1 SR0 Modulation Rate 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 0 ± 2.2% ± 1.8% ± 1.2% ± 1.1% ± 1.0% ± 0.9% ± 0.8% 1 ± 3.2% ± 2.5% ± 2.0% ± 1.6% ± 1.4% ± 1.25% ± 0.15% (XIN/CLKIN/20) * 62.5 KHz Modulation Output and Spreading Selection (ModOUT = ½ XIN/CLKIN) Output Frequency Range DIV2 = 0 SR0 Modulation Rate 4MHz 6MHz 8MHz 10MHz 12MHz 14MHz 16MHz 0 ± 2.0% ± 1.8% ± 1.2% ± 1.1% ± 1.0% ± 0.9% ± 0.8% 1 ± 3.2% ± 2.6% ± 2.0% ± 1.6% ± 1.4% ± 1.25% ± 0.15% General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. (XIN/CLKIN/20) * 62.5 KHz 2 of 9 P2008A July 2005 rev 1.3 Spread Spectrum The Modulation Output and Spreading Selection Tables illustrate the two possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency (Note: The center frequency is the frequency of the external reference input on XIN/CLKIN, Pin1). Example: The P2008A is designed for communications, digital video and imaging applications. It is not only optimized for operation in the 4MHz – 32MHz range, but its output frequency can be extended down to one half of the input clock frequency using the divide-by-two feature. This feature extends low frequency as low as to 2MHz. Setting Pin 3 low (DIV2 = 0; Divide-by-two mode) sets the output frequency (ModOUT) to half the frequency of the input clock (XIN/CLKIN). This is a simple way to generate a spread spectrum modulated low frequency clock when only a higher frequency signal is available. If you want the output frequency to be the same as the input, you can either set DIV2=1 or leave it unconnected. Selecting the P2008A’s spread options is a matter of either setting SR0=1 or SR0=0. Setting SR0=0 set as a lower modulation spread, while setting it to 1 introduces a wider spectral spread in the output clock. Refer Modulation output and Spreading Selections Tables. The example given in the figure below shows the device set to the divide-by-two mode (DIV2=0) with a lower spectrum range (SR0=0). The versatility provided by allowing both clock division and spread spectrum on one chip is already proving to be a popular solution among leading system manufacturers. P2008A Application Schematic +3.3V 8.832MHz Crystal 1 XIN/CLKIN 2 XOUT 3 DIV2 4 VSS VDD SR0 8 7 0.1µF Mod OUT SSON# 6 5 P2008A General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. Modulated 4.416MHz is connected to CLK input pin of the system 3 of 9 P2008A July 2005 rev 1.3 Absolute Maximum Ratings Symbol Parameter VDD, VIN TSTG Rating Unit Voltage on any pin with respect to Ground -0.5 to +7.0 V Storage temperature -65 to +125 °C TA Operating temperature -40 to +85 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VIL Input low voltage VSS – 0.3 - 0.8 V VIH Input high voltage 2.0 - VDD + 0.3 V IIL Input low current (pull-up resistors on inputs SR0 and DIV2) - - -35 µA IIH Input high current (pull-down resistor on input SSON#) - - 35 µA IXOL XOUT Output Low Current (@ 0.4V, VDD = 3.3V) - 3 - mA IXOH XOUT Output High Current (@ 2.5V, VDD = 3.3V) - 3 - mA VOL Output low voltage (VDD = 3.3V, IOL = 10mA) - - 0.4 V VOH Output high voltage (VDD = 3.3V, IOH = 10mA) 2.5 - - V ICC Dynamic supply current normal mode (3.3V, and 15pF loading) 6.0 7.0 8.3 mA IDD Static supply current standby mode - 0.6 - mA VDD Operating voltage 3.0 3.3 3.6 V tON Power up time (first locked clock cycle after power up) - 0.18 - mS ZOUT Clock output impedance - 50 - Ω General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. 4 of 9 P2008A July 2005 rev 1.3 AC Electrical Characteristics Symbol fIN Parameter Input frequency DIV2 =0 DIV2 =1 Min Typ Max Unit 4 20 32 MHz 2 4 10 20 16 32 MHz fOUT Output frequency tLH* Output rise time (measured at 0.8V to 2.0V) 0.7 0.9 1.1 nS tHL* Output fall time (measured at 2.0V to 0.8V) 0.6 0.8 1.0 nS tJC Jitter (cycle to cycle) - - 360 pS tD Output duty cycle 45 50 55 % *tLH and tHL are measured into a capacitive load of 15pF General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. 5 of 9 P2008A July 2005 rev 1.3 Package Information 8-Pin SOIC Package H E D A2 A C A1 D θ e L B Dimensions Symbol Inches Min Max Millimeters Min Max A1 0.004 0.010 0.10 0.25 A 0.053 0.069 1.35 1.75 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 0.25 D 0.193 BSC 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H 0.236 BSC 6.00 BSC L 0.016 0.050 0.41 1.27 θ 0° 8° 0° 8° General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. 6 of 9 P2008A July 2005 rev 1.3 8-Pin TSSOP Package H E D A2 A C θ e A1 L B Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.10 A1 0.002 0.006 0.05 0.15 A2 0.033 0.037 0.85 0.95 B 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 D 0.114 0.122 2.90 3.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.028 0.50 0.70 θ 0° 8° 0° 8° General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. 7 of 9 P2008A July 2005 rev 1.3 Ordering Codes Part Number Marking Package type P2008A-08ST P2008A 8 PIN SOIC, TUBE P2008A-08SR P2008A 8-PIN SOIC, TAPE AND REEL P2008A-08TT P2008A 8-PIN TSSOP, TUBE P2008A-08TR P2008A 8-PIN TSSOP, TAPE AND REEL P2008AF-08ST P2008AF 8 PIN SOIC, TUBE, Pb Free P2008AF-08SR P2008AF 8-PIN SOIC, TAPE AND REEL, Pb Free P2008AF-08TT P2008AF 8-PIN TSSOP, TUBE, Pb Free P2008AF-08TR P2008AF 8-PIN TSSOP, TAPE AND REEL, Pb Free P2008AG-08ST P2008AG 8 PIN SOIC, TUBE, Green P2008AG-08SR P2008AG 8-PIN SOIC, TAPE AND REEL, Green P2008AG-08TT P2008AG 8-PIN TSSOP, TUBE, Green P2008AG-08TR P2008AG 8-PIN TSSOP, TAPE AND REEL, Green Qty/reel Temperature Commercial 2,500 Commercial Commercial 2,500 Commercial Commercial 2,500 Commercial Commercial 2,500 Commercial Commercial 2,500 Commercial Commercial 2,500 Commercial Device Ordering Information P 2008A F - 08 XX Package: ST – SOIC, TUBE SR - SOIC, T/R TT – TSSOP, TUBE TR - TSSOP, T/R Pin Count F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN DEVICE NUMBER Flow: P = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (-40°C to 85°C) X = Automotive Temperature Range (-40°C to 125°C) Licensed under U.S Patent Nos 5,488,627 and 5,631,921 General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. 8 of 9 P2008A July 2005 rev 1.3 Alliance Semiconductor Corporation 2575 Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: P2008A Document Version: v1.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. General purpose EMI Reduction IC Notice: The information in this document is subject to change without notice. 9 of 9