TI TPS65021RHARG4

TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
FEATURES
•
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•
•
•
•
•
•
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1.2 A, 97% Efficient Step-Down Converter for
System Voltage (VDCDC1)
1 A, Up to 95% Efficient Step-Down Converter
for Memory Voltage (VDCDC2)
800 mA, 90% Efficient Step-Down Converter
for Processor Core (VDCDC3)
30 mA LDO/Switch for Real Time Clock
(VRTC)
2 × 200 mA General-Purpose LDO
Dynamic Voltage Management for Processor
Core
Preselectable LDO Voltage Using Two Digital
Input Pins
Externally Adjustable Reset Delay Time
Battery Backup Functionality
Separate Enable Pins for Inductive Converters
I2C™ Compatible Serial Interface
85-µA Quiescent Current
Low Ripple PFM Mode
Thermal Shutdown Protection
40-Pin 6 mm x 6 mm QFN Package
DESCRIPTION
The TPS65021 is an integrated Power Management
IC for applications powered by one Li-Ion or
Li-Polymer cell, and which require multiple power
rails. The TPS65021 provides three highly efficient,
step-down converters targeted at providing the core
voltage, peripheral, I/O and memory rails in a
processor based system. All three step-down
converters enter a low-power mode at light load for
maximum efficiency across the widest possible range
of load currents. The TPS65021 also integrates two
general-purpose 200 mA LDO voltage regulators,
which are enabled with an external input pin. Each
LDO operates with an input voltage range between
1.5 V and 6.5 V, allowing them to be supplied from
one of the step-down converters or directly from the
battery. The default output voltage of the LDOs can
be digitally set to 4 different voltage combinations
using the DEFLDO1 and DEFLDO2 pins. The serial
interface can be used for dynamic voltage scaling,
masking interrupts, or for dis/enabling and setting the
LDO output voltages. The interface is compatible with
the Fast/Standard mode I2C specification, allowing
transfers at up to 400 kHz. The TPS65021 is
available in a 40-pin (RHA) QFN package, and
operates over a free-air temperature of -40°C to
85°C.
APPLICATIONS
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PDA
Cellular/Smart Phone
Internet Audio Player
Digital Still Camera
Digital Radio Player
Split Supply DSP and µP Solutions:
OMAP1610, OMAP1710, OMAP330, XScale
Bulverde, Samsung ARM-Based Processors,
etc.
Intel PXA270, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
(2)
TA
PACKAGE (1)
PART NUMBER (2)
–40°C to 85°C
40 pin QFN (RHA)
TPS65021RHA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The RHA package is available in tape and reel. Add the R suffix (TPS65021RHAR) to order quantities of 2500 parts per reel. Add the T
suffix (TPS65021RHAT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VI
VALUE
UNIT
–0.3 to 7
V
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3
2000
mA
Peak Current at all other pins
1000
mA
Input voltage range on all pins except AGND and PGND pins with respect to AGND
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature
–40 to 85
°C
TJ
Maximum junction temperature
125
°C
–65 to 150
°C
260
°C
Tstg Storage temperature
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
DISSIPATION RATINGS
(1)
(2)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
RHA (1) (2)
2.85 W
28 mW/°C
1.57 W
1.4 W
The thermal resistance junction to ambient of the RHA package is 35°C/W measured on a high K board.
The thermal resistance junction to case (exposed pad) of the RHA package is 5°C/W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Input voltage range step-down convertors
(VINDCDC1, VINDCDC2, VINDCDC3)
2.5
6
Output voltage range for VDCDC1 step-down convertor (1)
0.6
VINDCDC1
Output voltage range for VDCDC2 (mem) step-down convertor (1)
0.6
VINDCDC2
Output voltage range for VDCDC3 (core) step-down convertor (1)
0.6
VINDCDC3
VI
Input voltage range for LDOs (VINLDO1, VINLDO2)
1.5
6.5
VO
Output voltage range for LDOs (VLDO1, VLDO2)
1
VINLDO1-2
IO(DCDC2)
Output current at L1
VCC
VO
1200
Inductor at L1 (2)
2.2
CI(DCDC1)
Input Capacitor at VINDCDC1
(2)
CO(DCDC1)
Output Capacitor at VDCDC1
(2)
IO(DCDC2)
Output current at L2
(1)
(2)
2
When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1
See applications section for more information.
10
10
UNIT
V
V
V
V
mA
µH
3.3
µF
µF
22
1000
mA
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
Inductor at L2
(2)
MIN
NOM
2.2
3.3
Input Capacitor at VINDCDC2
(2)
10
CO(DCDC2)
Output Capacitor at VDCDC2
(2)
10
IO(DCDC3)
Output current at L3
CI(DCDC2)
Inductor at L3
MAX
µH
µF
µF
22
800
(2)
2.2
VINDCDC3 (2)
10
(2)
10
CI(DCDC3)
Input Capacitor at
CO(DCDC3)
Output Capacitor at VDCDC3
CI(VCC)
Input Capacitor at VCC
Ci(VINLDO)
Input Capacitor at VINLDO
(2)
(2)
(2)
UNIT
mA
µH
3.3
µF
µF
22
1
µF
1
µF
µF
CO(VLDO1-2)
Output Capacitor at VLDO1, VLDO2
IO(VLDO1-2)
Output current at VLDO1, VLDO2
2.2
CO(VRTC)
Output Capacitor at VRTC
TA
Operating ambient temperature
-40
85
°C
TJ
Operating junction temperature
-40
125
°C
10
Ω
200
(2)
µF
4.7
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering (3)
(3)
mA
1
Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted
accordingly.
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH
High level input voltage
Rpullup at SCLK and SDAT = 4.7 kR,
pulled to VRTC
1.3
VCC
V
VIL
Low level input voltage
Rpullup at SCLK and SDAT = 4.7 kR,
pulled to VRTC
0
0.4
V
IH
Input bias current
0.1
µA
V
0.01
CONTROL SIGNALS : HOT_RESET
VIH
High level input voltage
1.3
VCC
VIL
Low level input voltage
0
0.4
V
IIB
Input bias current
0.01
0.1
µA
tglitch
Deglitch time at HOT_RESET
30
35
ms
6
V
0.3
V
25
CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output)
VOH
High level output voltage
VOL
Low level output voltage
IIL = 5 mA
Duration of low pulse at RESPWRON
External capacitor 1 nF
Resetpwron threshold
VRTC falling
–3%
2.4
3%
V
Resetpwron threshold
VRTC rising
–3%
2.52
3%
V
0
100
ms
3
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(qPFM)
II
I(q)
Operating quiescent
current, PFM
Current into VCC;
PWM
Quiescent current
All 3 DCDC converters enabled,
zero load and no switching, LDOs
enabled
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
85
100
All 3 DCDC converters enabled,
zero load and no switching, LDOs
off
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
78
90
DCDC1 and DCDC2 converters
enabled, zero load and no
switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
DCDC1 converter enabled, zero
load and no switching, LDOs off
µA
57
70
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
43
55
All 3 DCDC converters enabled
and running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
2
3
DCDC1 and DCDC2 converters
enabled and running in PWM,
LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
1.5
2.5
DCDC1 converter enabled and
running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
0.85
2
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
23
33
µA
VCC = 2.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
3.5
5
µA
43
µA
All converters disabled, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
VVSYSIN = 0 V
4
mA
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20
33
µA
3
µA
SUPPLY PINS: VBACKUP, VSYSIN, VRTC
I(q)
Operating quiescent current
VBACKUP = 3 V, VSYSIN = 0 V;
VCC = 2.6 V, current into VBACKUP
I(SD)
Operating quiescent current
VBACKUP < V_VBACKUP, current into
VBACKUP
2
VRTC LDO output voltage
VSYSIN = VBACKUP = 0 V, IO = 0 mA
3
Output current for VRTC
VSYSIN < 2.57 V and VBACKUP < 2.57 V
30
mA
VRTC short-circuit current limit
VRTC = GND; VSYSIN = VBACKUP = 0 V
100
mA
Maximum output current at VRTC for
RESPWRON = 1
VRTC > 2.6 V, VCC = 3 V;
VSYSIN = VBACKUP = 0 V
Output voltage accuracy for VRTC
VSYSIN = VBACKUP = 0 V; Io = 0 mA
-1%
1%
Line regulation for VRTC
VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA
-1%
1%
Load regulation VRTC
IO = 1 mA to 30 mA;
VSYSIN = VBACKUP = 0 V
-3%
1%
Regulation time for VRTC
Load change from 10% to 90%
Input leakage current at VSYSIN
VSYSIN < V_VSYSIN
IO
VO
Ilkg
V
30
mA
µs
10
rDS(on) of VSYSIN switch
2
µA
12.5
Ω
12.5
Ω
Input voltage range at VBACKUP (1)
2.73
3.75
V
Input voltage range at VSYSIN (1)
2.73
3.75
V
rDS(on) of VBACKUP switch
VSYSIN threshold
VSYSIN falling
–3%
2.55
3%
V
VSYSIN threshold
VSYSIN rising
–3%
2.65
3%
V
VBACKUP threshold
VBACKUP falling
–3%
2.55
3%
V
VBACKUP threshold
VBACKUP falling
–3%
2.65
3%
V
SUPPLY PIN: VINLDO
I(q)
I(SD)
(1)
Operating quiescent current
Current per LDO into VINLDO
16
30
µA
Shutdown current
Total current for both LDOs into VINLDO,
VLDO = 0 V
0.1
1
µA
Based on the requirements for the Intel PXA270 processor.
5
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC1 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC1
IO
Maximum output current
I(SD)
Shutdown supply current in VINDCDC1
DCDC1_EN = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC1 = V(GS) = 3.6 V
125
261
mΩ
Ilkg
P-channel leakage current
VINDCDC1 = 6 V
2
µA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC1 = V(GS) = 3.6 V
130
260
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
µA
Forward current limit (P- and N-channel)
2.5 V < VI(MAIN) < 6 V
1.55
1.75
1.95
A
1.3
1.5
1.7
MHz
fS
2.5
Oscillator frequency
3V
–2%
2%
3.3 V
VINDCDC1 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
–2%
2%
3V
VINDCDC1 = 3.3 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
–1%
1%
3.3 V
VINDCDC1 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=0
VINDCDC1 = VDCDC1 +0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=1
VINDCDC1 = VDCDC1 +0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
–1%
1%
Line Regulation
VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Load Regulation
Soft start ramp time
Fixed output voltage
FPWMDCDC1=1
0
%/V
IO = 10 mA to 1200 mA
0.25
%/A
VDCDC1 ramping from 5% to 95% of target
value
750
µs
1
MΩ
DCDC1 discharge = 1
300
Internal resistance from L1 to GND
VDCDC1 discharge resistance
V
mA
VINDCDC1 = 3.3 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
Fixed output voltage
FPWMDCDC1=0
6
6.0
1200
Ω
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC2 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC2
IO
Maximum output current
2.5
6
I(SD)
Shutdown supply current in VINDCDC2
DCDC2_EN = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
140
300
mΩ
Ilkg
P-channel leakage current
VINDCDC2 = 6 V
2
µA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
150
297
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
µA
ILIMF
Forward current limit (P- and N-channel)
2.5 V < VINDCDC2 < 6 V
1.40
1.55
1.70
A
fS
Oscillator frequency
1.3
1.5
1.7
MHz
1000
1.8 V
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.0 A
–2%
2%
2.5 V
VINDCDC2 = 2.8 V to 6 V;
0 mA ≤ IO ≤ 1 A
–2%
2%
1.8 V
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1 A
–2%
2%
2.5 V
VINDCDC2 = 2.8 V to 6 V;
0 mA ≤ IO ≤ 1 A
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC2 FPWMDCDC2=0
VINDCDC2 = VDCDC2 +0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.0 A
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC2; FPWMDCDC2=1
VINDCDC2 = VDCDC2 +0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.0 A
–1%
1%
Line Regulation
VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Load Regulation
Soft start ramp time
Fixed output voltage
FPWMDCDC2=0
Fixed output voltage
FPWMDCDC2=1
0
%/V
IO = 10 mA to 1 mA
0.25
%/A
VDCDC2 ramping from 5% to 95% of target
value
750
µs
1
MΩ
DCDC2 discharge =1
300
Internal resistance from L2 to GND
VDCDC2 discharge resistance
V
mA
Ω
7
TPS65021
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SLVS613 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC3 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC3
2.5
IO
Maximum output current
800
I(SD)
Shutdown supply current in VINDCDC3
DCDC3_EN = GND
0.1
1
µA
rDS(on)
P-channel MOSFET on-resistance
VINDCDC3 = V(GS) = 3.6 V
310
698
mΩ
Ilkg
P-channel leakage current
VINDCDC3 = 6 V
0.1
2
µA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC3 = V(GS) = 3.6 V
220
503
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
µA
Forward current limit (P- and N-channel)
2.5 V < VINDCDC3 < 6 V
1.05
1.34
1.52
A
1.3
1.5
1.7
MHz
fS
Oscillator frequency
Fixed output voltage
FPWMDCDC3=0
–2%
2%
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 800 mA
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC3 FPWMDCDC3=0
VINDCDC3 = VDCDC3 +0.5 V (min 2.5 V) to
6 V; 0 mA ≤ IO ≤ 800 mA
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC3; FPWMDCDC3=1
VINDCDC3 = VDCDC3 +0.5 V (min 2.5 V) to
6 V; 0 mA ≤ IO ≤ 800 mA
–1%
1%
Line Regulation
VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Load Regulation
Soft start ramp time
All VDCDC3
0.0
%/V
IO = 10 mA to 400 mA
0.25
%/A
VDCDC3 ramping from 5% to 95% of target
value
750
µs
1
MΩ
Internal resistance from L3 to GND
VDCDC3 discharge resistance
V
mA
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 800 mA
Fixed output voltage
FPWMDCDC3=1
8
6
DCDC3 discharge =1
300
Ω
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 and VLDO2 LOW DROPOUT REGULATORS
VI
Input voltage range for LDO1, 2
VO
LDO1 output voltage range
VO
LDO2 output voltage range
IO
Maximum output current for LDO1,
LDO2
I(SC)
LDO1 and LDO2 short circuit
current limit
Minimum voltage drop at LDO1,
LDO2
VI = 1.8 V, VO = 1.3 V
1.5
6.5
V
1
3.3
V
1
3.3
V
200
VI = 1.5 V, VO = 1.3 V
mA
120
V(LDO1) = GND, V(LDO2) = GND
400
IO = 50 mA, VINLDO = 1.8 V
120
IO = 50 mA, VINLDO = 1.5 V
65
IO = 200 mA, VINLDO = 1.8 V
150
mA
mV
300
Output voltage accuracy for LDO1,
LDO2
IO = 10 mA
–2%
1%
Line regulation for LDO1, LDO2
VINLDO1,2 = VLDO1,2 + 0.5 V (min.
2.5 V) to 6.5 V, IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2
IO = 0 mA to 50 mA
–1%
1%
Regulation time for LDO1, LDO2
Load change from 10% to 90%
µs
10
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
High level input voltage
1.3
VCC
V
VIL
Low level input voltage
0
0.4
V
0.05
µA
Input bias current
0.001
THERMAL SHUTDOWN
T(SD)
Thermal shutdown
Increasing junction temperature
160
°C
Thermal shudown hysteresis
Decreasing junction temperature
20
°C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO
Internal UVLO
V(UVLO_HYST)
Internal UVLO comparator
hysteresis
VCC falling
–2%
2.35
2%
120
V
mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)
Falling threshold
Hysteresis
Propagation delay
–1%
1
1%
V
40
50
60
mV
10
µs
25 mV overdrive
POWER GOOD
V(PGOODF)
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, decreasing
–12%
–10%
–8%
V(PGOODR)
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, increasing
–7%
–5%
–3%
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SLVS613 – OCTOBER 2005
DEFDCDC2
PWRFAIL
PGND2
VDCDC2
L2
VINDCDC2
PWRFAIL_SNS
VCC
LOWBAT_SNS
AGND1
PIN ASSIGNMENT
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
DEFDCDC3
1
30
SCLK
VDCDC3
2
29
SDAT
3
28
INT
L3
4
27
RESPWRON
VINDCDC3
5
26
TRESPWRON
VINDCDC1
6
25
DCDC1_EN
L1
7
24
DCDC2_EN
PGND1
8
23
DCDC3_EN
VDCDC1
9
22
LDO_EN
10
21
LOWBAT
PGND3
DEFDCDC1
VLDO1
VINLDO
VLDO2
VRTC
AGND2
VBACKUP
VSYSIN
DEFLDO1
DEFLDO2
HOT_RESET
11 12 13 14 15 16 17 18 19 20
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
SWITCHING REGULATOR SECTION
AGND1
40
Analog ground connection. All analog ground pins are connected internally on the chip.
AGND2
17
Analog ground connection. All analog ground pins are connected internally on the chip.
PowerPAD™
–
Connect the power pad to analog ground.
VINDCDC1
6
L1
7
VDCDC1
9
PGND1
8
VINDCDC2
36
L2
35
VDCDC2
33
PGND2
34
VINDCDC3
5
L3
4
VDCDC3
2
PGND3
3
VCC
37
10
I
Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply
as VINDCDC2, VINDCDC3, and VCC.
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
I
VDCDC1 feedback voltage sense input, connect directly to VDCDC1
Power ground for VDCDC1 converter
I
Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply
as VINDCDC1, VINDCDC3, and VCC.
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
I
VDCDC2 feedback voltage sense input, connect directly to VDCDC2
Power ground for VDCDC2 converter
I
Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply
as VINDCDC1, VINDCDC2, and VCC.
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
I
VDCDC3 feedback voltage sense input, connect directly to VDCDC3
Power ground for VDCDC3 converter
I
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters.
This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.
Also supplies serial interface block
TPS65021
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SLVS613 – OCTOBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DEFDCDC1
10
I
Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected to
a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in
a range from 0.6 V to VINDCDC1 V
DEFDCDC2
32
I
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected
to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set
in a range from 0.6 V to VINDCDC2 V
DEFDCDC3
1
I
Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connected
to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set
in a range from 0.6 V to VINDCDC3 V
DCDC1_EN
25
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN
24
I
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN
23
I
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
LDO REGULATOR SECTION
VINLDO
19
I
I Input voltage for LDO1 and LDO2
VLDO1
20
O
Output voltage of LDO1
VLDO2
18
O
Output voltage of LDO2
LDO_EN
22
I
Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs
VBACKUP
15
I
Connect the backup battery to this input pin.
VRTC
16
O
Output voltage of the LDO/switch for the real time clock
VSYSIN
14
I
Input of system voltage for VRTC switch
DEFLD01
12
I
Digital input, used to set default output voltage of LDO1 and LDO2
DEFLD02
13
I
Digital input, used to set default output voltage of LDO1 and LDO2
CONTROL AND I2C SECTION
HOT_RESET
11
I
Push button input used to reboot or wake-up processor via RESPWRON output pin
TRESPWRON
26
I
Connect the timing capacitor to this pin to set the reset delay time: 1 nF → 100 ms
RESPWRON
27
O
Open drain System reset output
PWRFAIL
31
O
Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
LOW_BAT
21
O
Open drain output of LOW_BAT comparator
INT
28
O
Open drain output
SCLK
30
I
Serial interface clock line
SDAT
29
I/O
PWRFAIL_SNS
38
I
Input for the comparator driving the PWRFAIL output
LOWBAT_SNS
39
I
Input for the comparator driving the LOW_BAT output
Serial interface data/address
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SLVS613 – OCTOBER 2005
FUNCTIONAL BLOCK DIAGRAM
VSYSIN
THERMAL
SHUTDOWN
VCC
VBACKUP
BBAT
SWITCH
VRTC
VINDCDC1
DCDC1
L1
VDCDC1
STEP-DOWN
CONVER TER
SCLK
SDAT
Serial Interface
VINDCDC2
DCDC1_EN
DCDC2_EN
DCDC2
DCDC3_EN
LDO_EN
HOT_RESET
DEFDCDC1
PGND1
CONTROL
STEP-DOWN
CONVERTER
L2
VDCDC2
DEFDCDC2
PGND2
RESPWRON
VCC
INT
AGND1
VINDCDC3
LOWBAT_SNS
PWRFAIL_SNS
LOW_BATT
PWRFAIL
TRESPWRON
L3
UVLO
VREF
OSC
DCDC3
VDCDC3
STEP-DOWN
CONVERTER
DEFDCDC3
PGND3
DEFLDO1
VLDO1
DEFLDO2
VLDO1
200-mA LDO
AGND2
VINLDO
VLDO2
VLDO2
200-mA LDO
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TPS65021
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SLVS613 – OCTOBER 2005
TYPICAL CHARACTERISTICS
Graphs were taken using the EVM with the following inductor/output capacitor combinations:
CONVERTER
INDUCTOR
OUTPUT CAPACITOR
OUTPUT CAPACITOR VALUE
VDCDC1
VLCF4020-2R2
C2012X5R0J106M
2 × 10 µF
VDCDC2
VLCF4020-2R2
C2012X5R0J106M
2 × 10 µF
VDCDC3
VLF4012AT-2R2M1R5
C2012X5R0J106M
2 × 10 µF
Table 1. Table of Graphs
FIGURE
η
Efficiency
vs Output current
1, 2, 3, 4, 5, 6, 7
Line transient response
8, 9, 10
Load transient response
11, 12, 13
VDCDC2 PFM operation
14
VDCDC2 low ripple PFM operation
15
VDCDC2 PWM operation
16
Startup VDCDC1, VDCDC2 and VDCDC3
17
Startup LDO1 and LDO2
18
Line transient response
19, 20, 21
Load transient response
22, 23, 24
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
VI = 3.8 V
VI = 4.2 V
VI = 4.2 V
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 5 V
VI = 5 V
o
o
TA = 25 C
VO = 3.3 V
PFM / PWM Mode
0.01
0.1
1
10
100
IO - Output Current - mA
Figure 1.
1k
TA = 25 C
VO = 3.3 V
PWM Mode
10 k
0.01
0.1
1
10
100
1k
10 k
IO - Output Current - mA
Figure 2.
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SLVS613 – OCTOBER 2005
DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
VI = 2.5 V
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 3.8 V
VI = 4.2 V
VI = 4.2 V
VI = 2.5 V
VI = 5 V
VI = 5 V
o
o
TA = 25 C
VO = 1.8 V
PWM Mode
TA = 25 C
VO = 1.8 V
PWM / PFM Mode
0.01
0.1
10
1
100
1k
10 k
0.01
0.1
10
1
100
IO - Output Current - mA
IO - Output Current - mA
Figure 3.
Figure 4.
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
VI = 3 V
1k
10 k
o
TA = 25 C
VO = 1.55 V
PWM Mode
VI = 2.5 V
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 3.8 V
VI = 4.2 V
VI = 3 V
VI = 2.5 V
VI = 5 V
VI = 4.2 V
o
TA = 25 C
VO = 1.55 V
PWM / PFM Mode
0.1
1
10
100
IO - Output Current - mA
Figure 5.
14
1k
VI = 5 V
10 k
0.1
1
10
100
IO - Output Current - mA
Figure 6.
1k
10 k
TPS65021
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SLVS613 – OCTOBER 2005
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
VDCDC1 LINE TRANSIENT RESPONSE
Ch1 = VI
Ch2 = VO
Efficiency - %
VI = 3 V
C1 High
4.74 V
VI = 3.8 V
VI = 2.5 V
C1 Low
3.08 V
VI = 4.2 V
C2 PK-PK
85 mV
VI = 5 V
C2 Mean
3.2957 V
IO = 100 mA
VI = 3.6 V to 4.7 V
VO = 3 V
PWM Mode
o
TA = 25 C
VO = 1.3 V
Low Ripple PFM Mode
0.01
0.1
1
10
IO - Output Current - mA
Figure 7.
Figure 8.
VDCDC2 LINE TRANSIENT RESPONSE
VDCDC3 LINE TRANSIENT RESPONSE
Ch1 = VI
Ch2 = VO
C1 High
4.04 V
Ch1 = VI
Ch2 = VO
C1 High
4.05 V
C1 Low
2.95 V
C1 Low
2.94 V
C2 PK-PK
46.0 mV
C2 PK-PK
49.9 mV
C2 Mean
1.59798 V
C2 Mean
1.79419 V
IO = 100 mA
VI = 3 V to 4 V
VO = 1.8 V
PWM Mode
IO = 100 mA
VI = 3 V to 4 V
VO = 1.6 V
PWM Mode
Figure 9.
Figure 10.
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SLVS613 – OCTOBER 2005
VDCDC1 LOAD TRANSIENT RESPONSE
VDCDC2 LOAD TRANSIENT RESPONSE
Ch2 = VO
Ch4 = IO
Ch2 = VO
Ch4 = IO
C4 High
1.09 A
C4 High
830 mA
C4 Low
120 mA
C4 Low
90 mA
C2 PK-PK
188 mV
C2 PK-PK
80 mV
C2 Mean
3.3051 V
C2 Mean
1.7946 V
IO = 100 mA to 800 mA
VI = 3.8 V
IO = 120 mA to 1080 mA
VI = 3.8 V
VO = 1.8 V
PWM Mode
VO = 3.3 V
PWM Mode
Figure 11.
Figure 12.
VDCDC3 LOAD TRANSIENT RESPONSE
VDCDC2 OUTPUT VOLTAGE RIPPLE
Ch2 = VO
Ch4 = IO
C4 High
730 mA
VI = 3.8 V
VO = 1.8 V
IO = 1 mA
o
TA = 25 C
PFM Mode
C4 Low
80 mA
C2 PK-PK
17.0 mV
C2 PK-PK
80 mV
C2 Mean
1.80522 V
C2 Mean
1.5931 V
IO = 80 mA to 720 mA
VI = 3.8 V
VO = 1.6 V
o
TA = 25 C
PWM Mode
Figure 13.
16
Figure 14.
TPS65021
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SLVS613 – OCTOBER 2005
VDCDC2 OUTPUT VOLTAGE RIPPLE
VO = 1.8 V
VI = 3.8 V
IO = 1 mA
o
TA = 25 C
Low Ripple PFM Mode
VDCDC2 OUTPUT VOLTAGE RIPPLE
VI = 3.8 V
VO = 1.8 V
IO = 1 mA
o
TA = 25 C
PWM Mode
C2 PK-PK
7.7 mV
C2 Mean
1.79955 mV
Figure 15.
Figure 16.
STARTUP VDCDC1, VDCDC2, AND VDCDC3
STARTUP LDO1 AND LDO2
ENABLE
ENABLE
VDCDC1
LDO1
VDCDC2
LDO2
VDCDC3
Figure 17.
Figure 18.
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LDO1 LINE TRANSIENT RESPONSE
Ch1 = VI
Ch2 = VO
IO = 25 mA
VO = 1.1 V
o
TA = 25 C
LDO2 LINE TRANSIENT RESPONSE
C1 High
3.83 V
Ch1 = VI
Ch2 = VO
IO = 25 mA
VO = 3.3 V
o
TA = 25 C
C1 Low
3.29 V
C1 Low
3.99 V
C2 PK-PK
6.2 mV
C2 PK-PK
6.1 mV
C2 Mean
1.09702 V
Ch1 = VI
Ch2 = VO
C2 Mean
3.29828 V
Figure 19.
Figure 20.
VRTC LINE TRANSIENT RESPONSE
LDO1 LOAD TRANSIENT RESPONSE
IO = 10 mA
VO = 3 V
o
TA = 25 C
C1 High
3.82 V
C4 High
48.9 mA
C1 Low
3.28 V
C4 Low
2.1 mA
C2 PK-PK
22.8 mV
C2 PK-PK
42.5 mV
C2 Mean
2.98454 V
C2 Mean
1.09664 V
Ch2 = VO
Ch4 = IO
Figure 21.
18
C1 High
4.51 V
VI = 3.3 V
VO = 1.1 V
o
TA = 25 C
Figure 22.
TPS65021
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SLVS613 – OCTOBER 2005
LDO2 LOAD TRANSIENT RESPONSE
VRTC LOAD TRANSIENT RESPONSE
C4 High
47.8 mA
C4 High
21.4 mA
C4 Low
-2.9 mA
C4 Low
-1.4 mA
C2 PK-PK
40.4 mV
C2 PK-PK
76 mV
C2 Mean
3.29821 V
Ch2 = VO
Ch4 = IO
VI = 4 V
VO = 3.3 V
o
TA = 25 C
Figure 23.
C2 Mean
2.9762 V
Ch2 = VO
Ch4 = IO
VI = 3.8 V
VO = 3 V
o
TA = 25 C
Figure 24.
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TPS65021
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SLVS613 – OCTOBER 2005
DETAILED DESCRIPTION
VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY
The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail. This is the
VCC_BATT rail of the Intel Bulverde processor for example.
In applications using a backup battery, the backup voltage can be either directly connected to the TPS65021
VBACKUP pin if a Li-Ion cell is used, or via a boost converter (e.g. TPS61070) if a single NiMH battery is used.
The voltage applied to the VBACKUP pin is fed through a PMOS switch to the VRTC pin. The TPS65021 asserts
the RESPWRON signal if VRTC drops below 2.4 V. This, together with 375 mV at 30 mA drop out for the PMOS
switch means that the voltage applied at VBACKUP must be greater than 2.775 V for normal system operation.
When the voltage at the VSYSIN pin exceeds 2.65 V, the path from VBACKUP to VRTC is cut, and VRTC is
supplied by a similar PMOS switch from the voltage source connected to the VSYSIN input. Typically this is the
VDCDC1 converter but can be any voltage source within the appropriate range.
In systems where no backup battery is used, the VBACKUP pin is connected to GND. In this case, a low power
LDO is enabled, supplied from VCC and capable of delivering 30 mA to the 3 V output. This LDO is disabled if
the voltage at the VSYSIN input exceeds 2.65 V. VRTC is then supplied from the external source connected to
this pin as previously described
VSYSIN
Vref
V_VSYSIN
priority
#1
VCC
VBACKUP
Vref
V_VBACKUP
priority
#2
V_VSYSIN
V_VBACKUP
EN
VRTC
LDO
priority
#3
VRTC
Vref
A.
V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
B.
RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
RESPWRON
Figure 25.
STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3
The TPS65021 incorporates three synchronous step-down converters operating typically at 1.5 MHz fixed
frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the
converters automatically enter the power save mode (PSM), and operate with pulse frequency modulation (PFM).
The VDCDC1 converter is capable of delivering 1.2 A output current, the VDCDC2 converter is capable of
delivering 1 A and the VDCDC3 converter is capable of delivering up to 800 mA.
The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The
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TPS65021
SLVS613 – OCTOBER 2005
DETAILED DESCRIPTION (continued)
pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The
VDCDC1 converter defaults to 3 V or 3.3 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is
tied to ground, the default is 3 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC1 pin is connected
to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the application
information section for more details.
The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2
is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 2.5 V. When the DEFDCDC2 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.3 V or 1.55 V depending on the DEFDCDC3 configuration pin. If
DEFDCDC3 is tied to ground the default is 1.3 V. If it is tied to VCC, the default is 1.55 V. When the DEFDCDC3
pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The
core voltage can be reprogrammed via the serial interface in the range of 0.8 V to 1.6 V with a programmable
slew rate. The converter is forced into PWM operation whilst any programmed voltage change is underway,
whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to
program the output voltage and slew rate during voltage transitions.
The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs of
which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged via
on-chip 300-Ω resistors when the dc-dc converters are disabled.
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the
adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the
inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel
rectifier and turning on the P-channel switch.
The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a
typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the
VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three
converters can be changed using the CON_CTRL register.
POWER SAVE MODE OPERATION
As the load current decreases, the converters enter the power save mode operation. During PSM, the converters
operate in a burst mode (PFM mode) with a switching frequency between half of the switching frequency and
switching frequency for one burst cycle. However, the frequency between different burst cycles depends on the
actual load current and is typically far less than the switching frequency with a minimum quiescent current to
maintain high efficiency.
In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM
is calculated as follows:
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DETAILED DESCRIPTION (continued)
IPFMDCDC1 enter =
VINDCDC1
24 W
IPFMDCDC2 enter =
VINDCDC2
26 W
IPFMDCDC3 enter =
VINDCDC3
39 W
(1)
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the
output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter
effectively delivers a constant current defined as follows.
VINDCDC1
IPFMDCDC1 leave =
18 W
IPFMDCDC2 leave =
VINDCDC2
20 W
IPFMDCDC3 leave =
VINDCDC3
29 W
(2)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has dropped below the threshold again. If the load current is greater than the delivered current, then the output
voltage falls until it crosses the COMP LOW threshold, set to 2% below nominal VO, or the skip burst exceeds
16×1/switching frequency. Power Save Mode is exited and the converter returns to PWM mode.
These control methods reduce the quiescent current to typically 14 µA per converter, and the switching activity to
a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator
delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The
PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM
mode.
LOW RIPPLE MODE
Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in
PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the converter, the lower
the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage
ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is
used to keep the switching frequency above the audible range in PFM mode down to a low output current.
SOFT START
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft
start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start
time is typically 750 µs if the output voltage ramps from 5% to 95% of the final target value. If the output is
already precharged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170 µs between the converter being enabled and switching activity actually
starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so to
prevent discharging of the output while the internal soft start ramp catches up with the output voltage.
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DETAILED DESCRIPTION (continued)
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS65021 converters offer a low input to output voltage difference while still maintaining operation with the
use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current
and output voltage. It is calculated as:
Vin
min
Vout
min
DS(on) max RL
Iout max r
(3)
with:
Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions)
rDS(on)max = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
Voutmin = nominal output voltage minus 2% tolerance limit
ACTIVE DISCHARGE WHEN DISABLED
When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, EN_x or OVERTEMP
condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually
enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the VDCDC1,
VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω (typical) load which is active as long as the
converters are disabled.
POWER GOOD MONITORING
All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators.
Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%
hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An
interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when
the converters are disabled and the relevant PGOODZ register bits indicate that power is good.
LOW DROPOUT VOLTAGE REGULATORS
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of
300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the
EN_LDO pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and
LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect
external regulators in parallel in systems with a backup battery. The TPS65021 step-down and LDO voltage
regulators automatically power down when the VBAT voltage drops below the UVLO threshold or when the
junction temperature rises above 160°C.
POWER GOOD MONITORING
Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these
comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any
voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the
relevant PGOODZ register bits indicate that power is good.
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DETAILED DESCRIPTION (continued)
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit for the five regulators on the TPS65021 prevents the device from malfunctioning
at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The
UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note
that when any of the dc-dc converters are running, there is an input current at the VCC pin, which is up to 3 mA
when all three converters are running in PWM mode. This current needs to be taken into consideration if an
external RC filter is used at the VCC pin to remove switching noise from the TPS65021 internal analog circuitry
supply.
POWER-UP SEQUENCING
The TPS65021 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by
providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The
relevant control pins are described in Table 2.
Table 2. Control Pins and Status Outputs for DC-DC Converters
PIN NAME
INPUT
OUTPUT
FUNCTION
DEFDCDC3
I
Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to
1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V.
DEFDCDC2
I
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to
1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V.
DEFDCDC1
I
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 3 V,
DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V.
DCDC3_EN
I
Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
DCDC2_EN
I
Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
DCDC1_EN
I
Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
HOT_RESET
I
The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any
TPS65021 settings except the output voltage of VDCDC3. Activating HOT_RESET sets the voltage of
VDCDC3 to its default value defined with the DEFDCDC3 pin. HOT_RESET is internally de-bounced by the
TPS65021.
RESPWRON
O
RESPWRON is held low when power is initially applied to the TPS65021. The VRTC voltage is monitored:
RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the
TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
TRESPWRON
I
Connect a capacitor here to define the RESET time at the RESPWRON pin. 1 nF typically gives 100 ms.
SYSTEM RESET + CONTROL SIGNALS
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron
seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an
external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the
HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
hysteresis.
The DCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when HOT_RESET
is asserted. Other I2C registers are not affected. Generally, the DCDC3 converter is set to its default voltage with
one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout
(UVLO) condition, RESPWRON active, both DCDC3-converter AND DCDC1-converter disabled. In addition, the
voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx is the state before
VDCDC1 was disabled.
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DEFLDO1 and DEFLDO2
These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to
the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of
both LDOs can be changed during operation with the I2C interface as described in the interface description.
Table 3.
DEFLDO2
DEFLDO1
VLDO1
VLDO2
0
0
1.1 V
1.3 V
0
1
1.5 V
1.3 V
1
0
2.6 V
2.8 V
1
1
3.15 V
3.3 V
Interrupt Management and the INT Pin
The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and LDOs. The INT
pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register
is read via the serial interface, any active bits are then blocked from the INT output pin.
Interrupts can be masked using the MASK register; default operation is not to mask any interrupts since this
gives the simple POWER_OK function.
TIMING DIAGRAMS
HOT_RESET
tDEGLITCH
RESPWRON
VO DCDC3
any voltage set
2
with I C interface
tNRESPWRON
default voltage
Figure 26. HOT_RESET Timing
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VCC
1.9 V
0.8 V
2.35 V
1.9 V
1.2 V
2.47 V
UVLO*
2.52 V
VRTC
2.4 V
3V
RESPWRON
tNRESPWRON
ENDCDCx
Ramp
Within
800 ms
VODCDCx
1.8 V
slope depending on load
ENLDO
VOLDOx
1.5 V
*... Internal Signal
VSYSIN = VBACKUP = GND;
VINLDO = VCC
Figure 27. Power-Up and Power-Down Timing
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VCC
RESPWRON
tNRESPWRON
ENDCDC1
ENDCDC2
3.3 V or 3 V
VODCDC1
Ramp Within 800 ms
VODCDC2
Ramp Within
800 ms
2.5 V or 1.8 V
Ramp Within 800 ms
DEFCORE
register
Default Value
Set Higher Output Voltage for DCDC3
GO bit in
CON_CTRL2
Cleared Automatically
Automatically Set
to Default Value
ENDCDC3
VODCDC3
1.3 V or 1.55 V
Ramp Within 800 ms
Programmed Slope Depending
On Load
Slew Rate
1.3 V or 1.55 V
Ramp Within
800 ms
Figure 28. DVS Timing
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65021 has a 7bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
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whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65021 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65021 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65021 device must leave the data line high to enable the master to generate the stop
condition
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 29. Bit Transfer on the Serial Interface
CE
DATA
CLK
S
P
START Condition
STOP Condition
Figure 30. START and STOP Conditions
SCLK
SDAT
A6
A5
A4
A0
R/W
0
Start
Slave Address
ACK
R7
R6
R5
R0
0
ACK
D7
D5
Register Address
Figure 31. Serial i/f WRITE to TPS65021 Device
D0 ACK
0
0
Note: SLAVE = TPS65020
28
D6
Data
Stop
TPS65021
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SLVS613 – OCTOBER 2005
SCLK
SDAT
A6
Start
A0
R/W
ACK
0
0
R0
R7
A6
ACK
A0
R/W
ACK
1
0
0
Register
Address
Slave Address
D0
D7
ACK
Slave
Drives
the Data
Slave Address
Stop
Master
Drives
ACK and Stop
Repeated
Start
Note: SLAVE = TPS65020
Figure 32. Serial i/f READ from TPS65021: Protocol A
SCLK
SDA
A6
A0
R/W
ACK
0
Start
R0
R7
0
A6
ACK
0
R/W
ACK
D7
D0
ACK
0
1
Stop Start
Register
Address
Slave Address
A0
Slave Address
Slave
Drives
the Data
Stop
Master
Drives
ACK and Stop
Note: SLAVE = TPS65020
Figure 33. Serial i/f READ from TPS65021: Protocol B
DATA
t(BUF)
th(STA)
t(LOW)
tf
tr
CLK
th(STA)
t(HIGH)
th(DATA)
STO
STA
tsu(STA)
tsu(STO)
tsu(DATA)
STA
STO
Figure 34. Serial i/f Timing Diagram
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MIN
MAX
UNIT
400
kHz
fMAX
Clock frequency
twH(HIGH)
Clock high time
600
twL(LOW)
Clock low time
1300
tR
DATA and CLK rise time
tF
DATA and CLK fall time
th(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated)
600
ns
th(DATA)
Setup time for repeated START condition
600
ns
th(DATA)
Data input hold time
0
ns
tsu(DATA)
Data input setup time
100
ns
tsu(STO)
STOP condition setup time
600
ns
t(BUF)
Bus free time
1300
ns
ns
ns
300
ns
300
ns
VERSION. Register Address: 00h (read only)
VERSION
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
0
0
1
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
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PGOODZ. Register Address: 01h (read only)
PGOODZ
B7
Bit name and
function
PWRFAILZ
Set by signal
PWRFAIL
Default value
loaded by:
PWRFAILZ
Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B6
B5
B4
B3
B2
B1
LOWBATTZ
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
LOWBATT
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
LOWBATTZ
PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
VDCDC3
PGOOD
LDO2
PGOOD
LDO1
R
R
R
R
R
R
R
B0
R
PWRFAILZ:
0=
indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold.
1=
indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold.
LOWBATTZ:
0=
indicates that the LOWBATT_SNS input voltage is above the 1-V threshold.
1=
indicates that the LOWBATT_SNS input voltage is below the 1-V threshold.
PGOODZ VDCDC1:
0=
indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if
the VDCDC1 converter is disabled.
1=
indicates that the VDCDC1 converter output voltage is below its target regulation voltage
PGOODZ VDCDC2:
0=
indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if
the VDCDC2 converter is disabled.
1=
indicates that the VDCDC2 converter output voltage is below its target regulation voltage
PGOODZ VDCDC3: .
0=
indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if
the VDCDC3 converter is disabled and during a DVM controlled output voltage transition
1=
indicates that the VDCDC3 converter output voltage is below its target regulation voltage
PGOODZ LDO2:
0=
indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is
disabled.
1=
indicates that LDO2 output voltage is below its target regulation voltage
PGOODZ LDO1
0=
indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is
disabled.
1=
indicates that the LDO1 output voltage is below its target regulation voltage
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MASK. Register Address: 02h (read/write)
MASK
Bit name and
function
Default
Default value
loaded by:
Read/Write
Default Value: C0h
B7
B6
B5
B4
B3
B2
B1
MASK
PWRFAILZ
MASK
LOWBATTZ
MASK
VDCDC1
MASK
VDCDC2
MASK
VDCDC3
MASK
LDO2
MASK
LDO1
1
1
0
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B0
0
The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1
masks PGOODZ<n>.
REG_CTRL. Register Address: 03h (read/write)
REG_CTRL
B7
B6
Bit name and
function
Default
1
1
Set by signal
Default Value: FFh
B5
B4
B3
B2
B1
VDCDC1
ENABLE
VDCDC2
ENABLE
VDCDC3
ENABLE
LDO2
ENABLE
LDO1
ENABLE
1
1
1
DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ
Default value
loaded by:
Read/Write
B0
1
1
LDO_ENZ
LDO_ENZ
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
1
The REG_CTRL register can be used to disable and enable all power supplies via the serial interface. Default is
to allow all supplies to be on, providing the relevant enable pin is high. The following tables indicate how the
enable pins and the REG_CTRL register are combined. The REG_CTRL bits are automatically reset to default
when the corresponding enable pin is low.
REG_CTRL<5>
DCDC1
CONVERTER
DCDC2_EN PIN
REG_CTRL<4>
DCDC2
CONVERTER
0
x
disabled
1
0
disabled
0
x
disabled
1
0
1
1
disabled
enabled
1
1
enabled
DCDC3_EN PIN
REG_CTRL<3>
DCDC3
CONVERTER
LDO_EN PIN
REG_CTRL<2>
LDO2
0
x
disabled
0
x
disabled
1
0
disabled
1
0
disabled
1
1
enabled
1
1
enabled
DCDC1_EN PIN
32
LDO_EN PIN
REG_CTRL<1>
LDO1
0
x
disabled
1
0
disabled
1
1
enabled
TPS65021
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SLVS613 – OCTOBER 2005
CON_CTRL. Register Address: 04h (read/write)
Default Value: B1h
CON_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
DCDC2
PHASE1
DCDC2
PHASE0
DCDC3
PHASE1
DCDC3
PHASE0
LOW
RIPPLE
FPWM
DCDC2
FPWM
DCDC1
FPWM
DCDC3
1
0
1
1
0
0
0
1
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Default value
loaded by:
Read/Write
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low
output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to
minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is
taken as the reference and consequently has a fixed zero phase shift.
DCDC2 CONVERTER
DELAYED BY
CON_CTRL<5:4>
00
zero
00
zero
01
1/4 cycle
01
1/4 cycle
10
½ cycle
10
½ cycle
11
3/4 cycle
11
3/4 cycle
CON_CTRL<7:6>
Bit 3
Bit 2
Bit 1
Bit 0
DCDC3 CONVERTER
DELAYED BY
LOW RIPPLE:
0=
Skip mode operation optimized for high efficiency for all converters
1=
Skip mode operation optimized for low output voltage ripple for all converters
FPWM DCDC2:
0=
DCDC2 converter operates in PWM / PFM mode
1=
DCDC2 converter is forced into fixed frequency PWM mode
FPWM DCDC1:
0=
DCDC1 converter operates in PWM / PFM mode
1=
DCDC1 converter is forced into fixed frequency PWM mode
FPWM DCDC3:
0=
DCDC3 converter operates in PWM / PFM mode
1=
DCDC3 converter is forced into fixed frequency PWM mode
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CON_CTRL. Register Address: 05h (read/write)
CON_CTRL2
B7
B6
Bit name and
function
GO
Core adj
allowed
0
1
UVLO +
DONE
UVLO
R/W
R/W
Default
Default value
loaded by:
Read/Write
B5
0
Default Value: 40h
B4
0
B3
B2
B1
B0
DCDC2
discharge
DCDC1
discharge
DCDC3
discharge
0
0
0
UVLO
UVLO
UVLO
R/W
R/W
R/W
0
The CON_CTRL2 register can be used to take control the inductive converters.
Bit 7
Bit 6
Bit 2– 0
34
GO:
0=
no change in the output voltage for the DCDC3 converter
1=
the output voltage of the DCDC3 converter is changed to the value defined in DEFCORE with
the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is
complete. The transition is considered complete in this case when the desired output voltage
code has been reached, not when the VDCDC3 output voltage is actually in regulation at the
desired voltage.
CORE ADJ Allowed:
0=
the output voltage is set with the I2C register
1=
DEFDCDC3 is either connected to GND or VCC or an external voltage divider. When
connected to GND or VCC, VDCDC3 defaults to 1.3 V or 1.55 V respectively at start-up
0=
the output capacitor of the associated converter is not actively discharged when the converter is
disabled
1=
the output capacitor of the associated converter is actively discharged when the converter is
disabled. This decreases the fall time of the output voltage at light load
TPS65021
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SLVS613 – OCTOBER 2005
DEFCORE. Register Address: 06h (read/write
DEFCORE
B7
B6
Default Value: 14h/1Eh
B5
Bit name and
function
Default
0
0
B4
B3
B2
B1
B0
CORE4
CORE3
CORE2
CORE1
CORE0
1
DEFDCDC3
1
DEFDCDC3
0
RESET(1)
RESET(1)
RESET(1)
RESET(1)
RESET(1)
R/W
R/W
R/W
R/W
R/W
0
Default value
loaded by:
Read/Write
RESET(1): DEFCORE is reset to its default value by one of these events:
• undervoltage lockout (UVLO)
• DCDC1 AND DCDC3 disabled
• HOT_RESET pulled low
• RESPWRON active
• VRTC below threshold
CORE4 CORE3
CORE2
CORE1
CORE0
VDCDC3
CORE4
CORE3
CORE2
CORE1
CORE0
VDCDC3
0
0
0
0
0
0.8 V
1
0
0
0
0
1.2 V
0
0
0
0
1
0.825 V
1
0
0
0
1
1.225 V
0
0
0
1
0
0.85 V
1
0
0
1
0
1.25 V
0
0
0
1
1
0.875 V
1
0
0
1
1
1.275 V
0
0
1
0
0
0.9 V
1
0
1
0
0
1.3 V
0
0
1
0
1
0.925 V
1
0
1
0
1
1.325 V
0
0
1
1
0
0.95 V
1
0
1
1
0
1.35 V
0
0
1
1
1
0.975 V
1
0
1
1
1
1.375 V
0
1
0
0
0
1V
1
1
0
0
0
1.4 V
0
1
0
0
1
1.025 V
1
1
0
0
1
1.425 V
0
1
0
1
0
1.05 V
1
1
0
1
0
1.45 V
0
1
0
1
1
1.075 V
1
1
0
1
1
1.475 V
0
1
1
0
0
1.1 V
1
1
1
0
0
1.5 V
0
1
1
0
1
1.125 V
1
1
1
0
1
1.525 V
0
1
1
1
0
1.15 V
1
1
1
1
0
1.55 V
0
1
1
1
1
1.175 V
1
1
1
1
1
1.6 V
DEFSLEW. Register Address: 07h (read/write)
DEFSLEW
B7
B6
Default Value: 06h
B5
B4
B3
Bit name and
function
B2
B1
B0
SLEW2
SLEW1
SLEW0
1
1
0
UVLO
UVLO
UVLO
R/W
R/W
R/W
Default
Default value
loaded by:
Read/Write
SLEW2
SLEW1
SLEW0
VDCDC3 SLEW RATE
0
0
0
0.15 mV/µs
0
0
1
0.3 mV/µs
0
1
0
0.6 mV/µs
0
1
1
1.2 mV/µs
1
0
0
2.4 mV/µs
1
0
1
4.8 mV/µs
1
1
0
9.6 mV/µs
1
1
1
Immediate
35
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
LDO_CTRL. Register Address: 08h (read/write)
LDO_CTRL
B7
B5
B4
LDO2_2
LDO2_1
DEFLDOx
Bit name and
function
Default
Default Value: set with DEFLDO1 and DEFLDO2
B6
Default value
loaded by:
B2
B1
B0
LDO2_0
LDO1_2
LDO1_1
LDO1_0
DEFLDOx
DEFLDOx
DEFLDOx
DEFLDOx
DEFLDOx
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
B3
The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2.
The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3.
LDO1 OUTPUT
VOLTAGE
LDO2_2
LDO2_1
LDO2_0
LDO2 OUTPUT
VOLTAGE
0
1V
0
0
0
1.05 V
1
1.1 V
0
0
1
1.2 V
1
0
1.35 V
0
1
0
1.3 V
1
1
1.5 V
0
1
1
1.8 V
1
0
0
2.2 V
1
0
0
2.5 V
1
0
1
2.6 V
1
0
1
2.8 V
1
1
0
2.85 V
1
1
0
3V
1
1
1
3.15 V
1
1
1
3.3 V
LDO1_2
LDO1_1
LDO1_0
0
0
0
0
0
0
DESIGN PROCEDURE
Inductor Selection for the DC-DC Converters
Each of the converters in the TPS65021 typically use a 3.3 µH output inductor. Larger or smaller inductor values
are used to optimize the performance of the device for specific operation conditions. The selected inductor has to
be rated for its dc resistance and saturation current. The dc resistance of the inductance influences directly the
efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest
efficiency.
For a fast transient response, a 2.2-µH inductor in combination with a 22-µF output capacitor is recommended.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is needed
because during heavy load transient the inductor current rises above the value calculated under Equation 4.
1 Vout
Vin
I Vout L
Lƒ
(4)
I
Lmax
I outmax I
L
2
(5)
with:
f = Switching Frequency (1.5 MHz typical)
L = Inductor Value
∆IL = Peak-to-Peak inductor ripple current
ILMAX = Maximum Inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents
versus a comparable shielded inductor.
36
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS65021 (2 A for the VDCDC1 and VDCDC2 converters, and 1.3 A for the VDCDC3 converter). The core
material from inductor to inductor differs and has an impact on the efficiency especially at high switching
frequencies.
See Table 4 and the typical applications for possible inductors.
Table 4. Tested Inductors
DEVICE
DCDC3 converter
DCDC2 converter
DCDC1 converter
INDUCTOR
VALUE
TYPE
COMPONENT SUPPLIER
3.3 µH
CDRH2D14NP-3R3
Sumida
3.3 µH
LPS3010-332
Coilcraft
3.3 µH
VLF4012AT-3R3M1R3
TDK
2.2 µH
VLF4012AT-2R2M1R5
TDK
3.3 µH
CDRH2D18/HPNP-3R3
Sumida
3.3 µH
VLF4012AT-3R3M1R3
TDK
2.2 µH
VLCF4020-2R2
TDK
3.3 µH
CDRH3D14/HPNP-3R2
Sumida
3.3 µH
CDRH4D28C-3R2
Sumida
3.3 µH
MSS5131-332
Coilcraft
2.2 µH
VLCF4020-2R2
TDK
Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the
TPS65021 allow the use of small ceramic capacitors with a typical value of 10 µF for each converter without
having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low
ESR values have the lowest output voltage ripple and are recommended. See Table 5 for recommended
components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. Just for completeness, the RMS ripple current is calculated as:
V
1 - out
Vin
1
x
IRMSCout = Vout x
L x ¦
2 x Ö3
(6)
At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the
sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
1 - out
Vin
1
DVout = Vout x
x
+ ESR
L x ¦
8 x Cout x ¦
(
)
(7)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output
capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The
typical output voltage ripple is less than 1% of the nominal output voltage.
37
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. Each dc-dc converter requires a 10-µF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the
input for the dc-dc converters. A filter resistor of up to 10R and a 1-µF capacitor is used for decoupling the VCC
pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow via
this resistor into the VCC pin when all converters are running in PWM mode.
Table 5. Possible Capacitors
CAPACITOR VALUE
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
22 µF
22 µF
1206
TDK C3216X5R0J226M
Ceramic
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
22 µF
0805
TDK C2012X5R0J226MT
Ceramic
22µF
0805
Taiyo Yuden JMK212BJ226MG
Ceramic
10 µF
0805
Taiyo Yuden JMK212BJ106M
Ceramic
10 µF
0805
TDK C2012X5R0J106M
Ceramic
Output Voltage Selection
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 6 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is
needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Table 6.
The output voltage of VDCDC3 is set with the I2C interface. If the voltage is changed from the default, using the
DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3
does not change the voltage set with the register.
Table 6.
PIN
LEVEL
DEFAULT OUTPUT VOLTAGE
VCC
3.3 V
DEFDCDC1
DEFDCDC2
DEFDCDC3
GND
3V
VCC
2.5 V
GND
1.8 V
VCC
1.55 V
GND
1.3 V
Using an external resistor divider at DEFDCDCx:
10 R
V(bat)
VCC
1 mF
VDCDC3
L3
VINDCDC3
CI
CO
DCDC3_EN
VO
L
R1
DEFDCDC3
R2
AGND
38
PGND
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input
voltage V(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MR range in order to
maintain a high efficiency at light load.
V(DEFDCDCx) = 0.6 V
V
OUT
V
R1 R2
DEFDCDC3
R2
R1 R2 V
V
OUT
DEFDCDC3
R2
(8)
VRTC Output
The VRTC output is typically connected to the Vcc_Batt pin of a Intel PXA270 processor. During power-up of the
processor, the TPS65021 internally switches from the LDO or the backup battery to the system voltage
connected at the VSYSIN pin (see Figure 25). It is recommended to add a capacitor of 4.7-µF minimum to the
VRTC pin.
LDO1 and LDO2
The LDOs in the TPS65021 are general-purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitor required is 2.2 µF. The LDOs output voltage can be changed to different voltages
between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in
applications powering processors different from PXA270. The supply voltage for the LDOs needs to be
connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and
provides the highest efficiency.
Trespwron
This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.
The timing is generated by charging and discharging the capacitor with a current of 2 µA between a threshold of
0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.
Vcc-Filter
An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and other
analog circuitry. A typical value of 10R and 1 µF is used to filter the switching spikes, generated by the dc-dc
converters. A larger resistor than 10R should not be used because the current into VCC of up to 3 mA causes a
voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off
too early.
39
TPS65021
www.ti.com
SLVS613 – OCTOBER 2005
APPLICATION INFORMATION
TYPICAL CONFIGURATION FOR THE Intel Bulverde PROCESSOR
VCC
10 R
PWRFAIL
VCC
1 mF
10 mF
10 mF
10 mF
nBatt_Fault
LOW_BATT
VINDCDC1
VRTC
Vcc_Batt
3V
4.7 mF
DCDC2_EN
VINDCDC2
SYS_EN
DCDC1_EN
VINDCDC3
VDCDC1
TPS65021
VCC
PWRFAIL_SNS
L1
22 mF
VDCDC2
L2
LOWBAT_SNS
2.2 mH
2.2 mH
Vcc_IO
3 V; 3.3 V
Vcc_LCD
1.8 V; 2.5 V; 3 V; 3.3 V
Vcc_BB
1.8 V; 2.5 V; 3 V; 3.3 V
Vcc_MEM
1.8 V; 2.5 V; 3 V; 3.3 V
Vcc_USIM
1.8 V; 3 V
22 mF
VIN_LDO
1 MR
HOT_RESET
DCDC3_EN
LDO_EN
TRESPWRON
1 nF
LDO1
DEFLDO1
GND
DEFLDO2
LDO2
L3
2.2 mH
DEFDCDC1
VDCDC3
INT
DEFDCDC2
RESPWRON
DEFDCDC3
VBACKUP
3V
Backup
Battery
Vcc_SRAM
1.1 V
Vcc_CORE
Variable 0.85 V to 1.4 V
22 mF
nVcc_Fault
nRESET
SCLK
SCLK
SDAT
SDAT
4.7 kW
4.7 kW
VRTC
40
1.3 V
2.2 mF
VSYSIN
VCC
Vcc_PLL
2.2 mF
GND
VDCDC1
PWR_EN
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS65021RHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS65021RHARG4
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS65021RHAT
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPS65021RHATG4
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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