TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 2.25MHz 2x800mA Dual Step Down Converter In Small 3x3mm QFN Package FEATURES DESCRIPTION • • • • • • The TPS62410 device is a synchronous dual step-down DC-DC converter optimized for battery powered portable applications. It provides two independent output voltage rails powered by 1-cell Li-Ion or 3-cell NiMH/NiCD batteries. The device is also suitable to operate from a standard 3.3V or 5V voltage rail. • • APPLICATIONS • • • • • • Cell Phones, Smart-phones PDAs, Pocket PCs OMAP™ and Low Power DSP Supply Portable Media Players Digital Radio Digital Cameras VIN FB 1 SW1 CIN L1 2.2 μH 10 μF R11 270kΩ DEF_1 L2 MODE/ DATA The TPS62410 operates at 2.25MHz fixed switching frequency and enter the Power Save Mode operation at light load currents to maintain high efficiency over the entire load current range. For low noise applications the devices can be forced into fixed frequency PWM mode by pulling the MODE/DATA pin high. In the shutdown mode, the current consumption is reduced to 1.2µA. The device allows the use of small inductors and capacitors to achieve a small solution size. VOUT1 = 1.5V 100 up to 800mA 90 SW2 2.2 μH 80 ADJ2 GND R22 180kΩ VIN = 3.6 V 70 V OUT2 = 1.8V Cff2 R21 360kΩ 33pF VOUT = 3.3 V VIN = 3.6 V COUT1 = 22 µF R12 180kΩ EN_1 EN_2 With the EasyScale™ serial interface the output voltages can be modified during operation. It therefore supports Dynamic Voltage Scaling for low power DSP and processors. The TPS62410 is available in a 10-pin leadless package (3×3mm QFN) TPS62410 VIN 2.5V – 6V With an input voltage range of 2.5V to 6V, the TPS62410 is ideal to power portable applications like smart phones, PDAs, and other portable equipment. Up to 800mA COUT2 = 22 µF Efficiency - % • • • • High Efficiency—up to 95% VIN Range From 2.5 V to 6 V 2.25 MHz Fixed Frequency Operation Output Current 2 x 800mA Adjustable Output Voltage From 0.6 V to VIN EasyScale™ Optional One Pin Serial Interface for Dynamic Output Voltage Adjustment Power Save Mode at Light Load Currents 180° Out of Phase Operation Output Voltage Accuracy in PWM Mode ±1% Typical 32 µA Quiescent Current for both Converters 100% Duty Cycle for Lowest Dropout Available in a 10-Pin QFN (3×3mm) 60 VIN = 5 V VIN = 5 V 50 40 30 Power Save Mode MODE/DATA = 0 Forced PWM Mode MODE/DATA = 1 20 10 0 0.01 0.1 1 10 IOUT - mA 100 1000 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EasyScale, OMAP, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 ORDERING INFORMATION (1) TA PART NUMBER (1) –40°C to 85°C TPS62410 (1) DEFAULT OUTPUT VOLTAGE (2) OUT1 Adjustable OUT2 OUTPUT CURRENT 800mA 800mA QFN (1) PACKAGE ORDERING PACKAGE MARKING DRC TPS62410DRC CAT For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.3 to 7 V –0.3 to VIN +0.3, ≤7 V Input voltage range on VIN (2) Voltage range on EN, MODE/DATA, DEF_1 500 µA Voltage on SW1, SW2 –0.3 to 7 V Voltage on ADJ2, FB1 –0.3 to VIN +0.3, ≤7 V HBM Human body nodel 2 kV Charge device model 1 kV Maximum Current into MODE/DATA ESD rating (3) Machine model TJ(max) Maximum junction temperature 200 V 150 °C TA Operating ambient temperature range –40 to 85 °C Tstg Storage temperature range –65 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. DISSIPATION RATINGS PACKAGE RθJA POWER RATING FOR TA≤ 25°C DERATING FACTOR ABOVE TA = 25°C DRC 49°C/W 2050mW 21mW/°C RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VIN 2 NOM MAX UNIT Supply voltage 2.5 6 Output voltage range for adjustable voltage 0.6 VIN V TA Operating ambient temperature -40 85 °C TJ Operating junction temperature -40 125 °C Submit Documentation Feedback V TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 ELECTRICAL CHARACTERISTICS VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2µH, COUT = 20µF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range IQ Operating quiescent current ISD Shutdown current VUVLO Undervoltage lockout threshold 6.0 V One converter, IOUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 OR EN2 = 1 2.5 19 29 µA Two converter, IOUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 AND EN2 = 1 32 48 µA IOUT = 0mA, MODE/DATA = GND, for one converter, VOUT 1.575V (1) 23 µA IOUT = 0mA, MODE/DATA = VIN, for one converter, VOUT 1.575V (1) 3.6 mA EN1, EN2 = GND, VIN = 3.6V (2) 1.2 3 EN1, EN2 = GND, VIN ramped from 0V to 3.6V (3) 0.1 1 Falling 1.5 2.35 Rising 2.4 µA V ENABLE EN1, EN2 VIH High-level input voltage, EN1, EN2 1.2 VIN VIL Low-level input voltage, EN1, EN2 0 0.4 V V IIN Input bias current, EN1, EN2 EN1, EN2 = GND or VIN 0.05 1.0 µA DEF_1 = GND or VIN 0.01 1.0 µA DEF_1 INPUT IIN Input biasd current DEF_1 MODE/DATA VIH High-level input voltage, MODE/DATA 1.2 VIN V VIL Low-level input voltage, MODE/DATA 0 0.4 V IIN Input bias current, MODE/DATA MODE/DATA = GND or VIN VOH Acknowledge output voltage high Open drain, via external pullup resistor VOL Acknowledge output voltage low Open drain, sink current 500µA 0.01 0 1.0 µA VIN V 0.4 V INTERFACE TIMING tStart Start time tH_LB High time low bit, logic 0 detection Signal level on MODE/DATA pin is > 1.2V tL_LB Low time low bit, logic 0 detection Signal level on MODE/DATA pin < 0.4V µs 2 2 200 µs 2x 400 µs 2 200 µs 2x 400 µs tH_LB tL_HB Low time high bit, logic 1 detection Signal level on MODE/DATA pin < 0.4V tH_LB High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2V tL_HS TEOS End of Stream tACKN Duration of acknowledge condition VIN 2.5V to 6V (MODE/DATE line pulled low by the device) tvalACK Acknowledge valid time ttimeout Timeout for entering power save mode (1) (2) (3) TEOS MODE/DATA Pin changes from high to low µs 2 400 520 µs 2 µs 520 µs Device is switching with no load on the output, L = 3.3µH, value includes losses of the coil These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage VIN has not powered down. These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid. Submit Documentation Feedback 3 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2µH, COUT = 20µF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 280 620 mΩ 1 µA 200 450 mΩ 6 7.5 µA 1.2 1.38 A POWER SWITCH RDS(ON) P-Channel MOSFET On-resistance, VIN = VGS = 3.6V Converter 1,2 ILK_PMOS P-Channel leakage current VDS = 6.0V RDS(ON) N-Channel MOSFET On-resistance Converter 1,2 VIN = VGS = 3.6V ILK_SW1/SW2 Leakage Current into SW1/SW2 Pin Includes N-Chanel leakage currnet, VIN = open, VSW = 6.0V, EN = GND (4) ILIMF Forward Current Limit PMOS and NMOS TSD Thermal shutdown Increasing junction temperature 150 °C Thermal shudown hysteresis Decreasing junction temperature 20 °C OUT 1/2 800mA 2.5V ≤ VIN≤ 6.0V 1.0 OSCILLATOR fSW Oscillator frequency 2.5V ≤ VIN ≤ 6.0V 2.0 2.25 2.5 MHz OUTPUT VOUT Adjustable output votage range Vref Reference voltage VOUT (PFM) DC output voltage accuracy PFM mode, adjustable and fixed output voltage (5) VOUT DC output voltage load regulation Voltage positioning active, MODE/DATA = GND, device operating in PFM mode, VIN = 2.5V to 5.0V (6) (7) 1.01x VOUT 2.5% MODE/DATA = GND; device operating in PWM Mode VIN = 2.5V to 6.0V (7) –1% 0% 1% VIN = 2.5V to 6.0V, Mode/Data = VIN , Fixed PWM operation, 0mA < IOUT < IOUTMAX (8) –1% 0% 1% PWM operation mode 0.5 switching (9) Start-up time Activation time to start VOUT Ramp UP time Time to ramp from 5% to 95% of VOUT V mV –1.5% tRamp (7) (8) (9) VIN 600 tStart up (4) (5) (6) 4 0.6 %/A 170 µs 750 µs At pins SW1 and SW2 an internal resistor of 1MΩ is connected to GND Output voltage specification does not include tolerance of external voltage programming resistors Configuration L typ 2.2µH, COUT typ 20µF, see parameter measurement information, the output voltage ripple depends on the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance In Power Save Mode, PWM operation is typically entered at IPSM = VIN/32Ω. For VOUT > 2.2V, VIN min = VOUT +0.3V This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 =1) AND the other converter is already enabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/or EN2=1) a value of typ 80 µs for ramp up of internal circuits needs to be added. After tStart the converter starts switching and ramps VOUT. Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 DEVICE INFORMATION PIN ASSIGNMENTS ADJ2 1 MODE/DATA 2 VIN 3 FB1 4 DEF_1 5 D PA r e w Po 10 SW2 9 EN2 8 GND 7 EN1 6 SW1 Top view DRC package TERMINAL FUNCTIONS TERMINAL NAME NO. (QFN) I/O DESCRIPTION ADJ2 1 I Input to adjust output voltage of converter 2. In adjustable version (TPS62410) connect a external resistor divider between VOUT2, this pin and GND to set output voltage between 0.6V and VIN. If EasyScale™ Interface is used for converter 2, this pin must be directly connected to the output. MODE/DATA 2 I This Pin has 2 functions: 1. Operation Mode selection: With low level, Power Save Mode is enabled where the device operates in PFM mode at light loads and enters automatically PWM mode at heavy loads. Pulling this PIN to high forces the device to operate in PWM mode over the whole load range. 2. EasyScale™ Interface function: One wire serial interface to change the output voltage of both converters. The pin has an open drain output to provide an acknowledge condition if requested. The current into the open drain output stage may not exceed 500µA. The interface is active if either EN1 or EN2 is high. VIN 3 I Supply voltage, connect to VBAT, 2.5V to 6V FB1 4 I Direct feedback voltage sense input of converter 1, connect directly to Vout 1. An internal feed forward capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions or when the Interface is used, this pin is connected to an internal resistor divider network. DEF_1 5 I/O This pin defines the output voltage of converter 1. The pin acts in TPS62410 as an analog input for output voltage setting via external resistors. In fixed default output voltage versions this pin is a digital input to select between two fixed default output voltages. In TPS62410 an external resistor network needs to be connected to this pin to adjust the default output voltage. SW1 6 EN1 7 I Enable Input for Converter1, active high GND 8 I GND for both converters, this pin should be connected with the PowerPAD EN2 9 I/O SW2 10 PowerPAD™ Switch Pin of Converter1. Connected to Inductor 1 Enable Input for Converter 2, active high Switch Pin of Converter 2. Connected to Inductor 2 Connect to GND Submit Documentation Feedback 5 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 FUNCTIONAL BLOCK DIAGRAM VIN PMOS Current Limit Comparator Converter 1 VIN FB_VOUT Thermal Shutdown Softstart VREF +1% Skip Comp. EN1 FB_VOUT VREF- 1% Ext. res. network DEF1 Skip Comp. Low VREF Control Stage Error Amp. Internal FB VOUT1 compensated Int. Resistor Network PWM Comp. Cff 25pF SW1 MODE Register RI 1 Sawtooth Generator DEF1_High RI3 RI..N FB1 Gate Driver GND DEF1_Low Average Current Detector Skip Mode Entry Note A NMOS Current Limit Comparator CLK 0° Reference Mode/ DATA Easy Scale Interface ACK MOSFET Open drain Undervoltage Lockout PMOS Current Limit Comparator CLK 180° Converter 2 Int. Resistor Network Load Comparator 2.25MHz Oscillator VIN FB_VOUT VREF +1% Skip Comp. Register FB_VOUT DEF2 Note B Cff 25pF VREF- 1% Skip Comp. Low VREF Error Amp. RI 1 Internal compensated Control Stage Gate Driver PWM Comp. RI..N SW2 MODE FB_VOUT2 ADJ2 Thermal Shutdown Softstart Sawtooth Generator CLK 180° GND Average Current Detector Skip Mode Entry NMOS Current Limit Comparator EN2 Load Comparator GND 6 A. In fixed output voltage version, the PIN DEF_1 is connected to an internal digital input and disconnected from the error amplifier B. To set the output voltage of Converter 2 via EasyScale Interface, ADJ2 pin must be directly connected to VOUT2 Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION TPS62410 VIN 2.5 V - 6 V FB 1 VIN SW1 CIN 10 mF L1 VOUT1 2.2 mH LPS4018 R11 COUT1 2x10 mF GRM21BR61A106K DEF_1 R12 EN_1 L2 VOUT2 SW2 EN_2 2.2 mH LPS4018 MODE/ DATA R21 ADJ2 Cff2 33 pF COUT2 2x10 mF GRM21BR61A106K R22 GND TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE NO. Efficiency VOUT1 = 1.2V 1 Efficiency VOUT1 = 1.5V 2 Efficiency VOUT2 = 1.8V 3 Efficiency VOUT2 = 3.3V 4 Efficiency vs VIN 5, 6 DC Output Accuracy VOUT1 = 1.5V 7 DC Output Accuracy VOUT2 = 3.3V 8 FOSC vs VIN 9 Iq for one converter 10 Iq for both converters, not switching 11 RDSON PMOS vs VIN 12 RDSON NMOS vs VIN 13 Light Load Output Voltage Ripple in Power Save Mode 14 Output Voltage Ripple in Forced PWM Mode 15 Output Voltage Ripple in PWM Mode 16 Forced PWM/ PFM ModeTransition 17 Load Transient Response PFM/PWM 18 Load Transient Response PWM Operation 19 Line Rransient Response 20 Startup Timing One Converter 21 Typical Operation VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V 22 Typical Operation VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V 23 Typical Operation VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V 24 Dynamic Voltage Positioning 25 Submit Documentation Feedback 7 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) FIGURE NO. Soft Start 26 EasyScale Protocol Overview 27 EasyScale Protocol Without Acknowledge 28 EasyScale Protocol Including Acknowledge 29 EasyScale – Bit Coding 30 MODE/DATA PIN: Mode Selection 31 MODE/DATA Pin: Power Save Mode / Interface Communication 32 Typical Application Circuit 1.5V / 2.85V Adjustable Outputs 33,34 Layout Diagram 35 PCB Layout 36 EFFICIENCY VOUT = 1.2V 100 100 VOUT = 1.2 V 90 80 80 70 70 MODE/DATA = Low VIN = 5 V VIN = 3.7 V VIN = 3.3 V VIN = 2.7 V 60 50 40 30 MODE/DATA = High VIN = 5 V VIN = 3.7 V VIN = 3.3 V VIN = 2.7 V Efficiency - % Efficiency - % 90 EFFICIENCY VOUT = 1.5V 50 40 30 20 10 10 0.1 1 10 IOUT - mA 100 0 0.01 1000 0.1 1 MODE/DATA = High VIN = 5 V VIN = 3.7 V VIN = 3.3 V VIN = 2.7 V 10 IOUT - mA 100 Figure 1. Figure 2. EFFICIENCY VOUT2 = 1.8V EFFICIENCY VOUT2 = 3.3V 100 90 MODE/DATA = Low VIN = 5 V VIN = 3.7 V VIN = 3.3 V VIN = 2.7 V 60 20 0 0.01 VOUT = 1.5 V 1000 100 VOUT = 1.8 V 90 VOUT = 3.3 V VIN = 3.6 V 80 80 70 VIN = 2.7 V 60 VIN = 2.7 V VIN = 3.6 V 50 VIN = 3.6 V VIN = 5 V 40 VIN = 5 V 30 20 60 VIN = 5 V 40 Power Save Mode MODE/DATA = 0 Forced PWM Mode MODE/DATA = 1 20 10 0.1 1 10 IOUT - mA 100 1000 0 0.01 Figure 3. 8 VIN = 5 V 50 30 Forced PWM Mode MODE/DATA = 1 Power Save Mode MODE/DATA = 0 10 0 0.01 Efficiency - % Efficiency - % 70 VIN = 3.6 V 0.1 1 10 IOUT - mA Figure 4. Submit Documentation Feedback 100 1000 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 EFFICIENCY vs VIN , VOUT = 1.575V EFFICIENCY vs VIN, VOUT = 3.3V 100 100 MODE/DATA = 0 VOUT = 1.575 V 95 IOUT = 100 mA IOUT = 200 mA 90 90 IOUT = 10 mA 85 80 Efficiency Efficiency MODE/DATA = 0 VOUT = 3.3 V IOUT = 10 mA IOUT = 1 mA 75 70 IOUT = 1 mA 80 70 65 60 60 55 50 2 3 4 5 50 6 3 VIN - V 4 5 6 VIN - V Figure 5. Figure 6. DC OUTPUT ACCURACY VOUT1 = 1.5V DC OUTPUT ACCURACY VOUT2 = 3.3V 3.400 1.575 VOUT = 1.5 V VOUT = 3.3 V MODE/DATA = low, PFM Mode, Voltage Positioning Active 1.550 VIN = 5 V MODE/DATA = low, PFM Mode, Voltage Positioning Active VOUT DC - V VIN = 2.7 V VIN = 3.3 V 1.500 1.475 VIN = 2.7 V VIN = 3.3 V VIN = 3.7 V VIN = 5 V VIN = 3.7 V VOUT DC - V VIN = 5 V 1.525 PWM Mode Operation 3.350 VIN = 3.7 V 3.300 VIN = 3.7 V VIN = 4.2 V VIN = 4.2 V VIN = 5 V MODE/DATA = high, forced PWM Mode 3.250 1.450 MODE/DATA = high, forced PWM Mode 1.425 0.01 0.1 1 10 IOUT - mA 100 1000 3.200 0.01 Figure 7. 0.1 1 10 IOUT - mA 100 1000 Figure 8. Submit Documentation Feedback 9 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 FOSC vs VIN Iq FOR ONE CONVERTER, NOT SWITCHING 24 2.5 2.45 23 2.4 85°C 22 Iddq - mA Fosc - MHz 2.35 2.3 -40°C 2.25 2.2 25°C 21 20 25°C -40°C 2.15 85°C 19 2.1 18 2.05 2 2.5 3 3.5 4 4.5 VIN - V 5 17 2.5 6 5.5 3 3.5 4 4.5 5 5.5 6 5 5.5 6 VIN - V Figure 9. Figure 10. Iq FOR BOTH CONVERTERS, NOT SWITCHING RDSON PMOS vs VIN 0.55 42 0.5 40 0.45 38 RDSon - W Iddq - mA 85°C 36 25°C 34 0.4 85°C 0.35 25°C 0.3 32 0.25 -40°C -40°C 0.2 30 0.15 2.5 28 2.5 3 3.5 4 4.5 5 5.5 6 VIN - V Figure 11. 10 3 3.5 4 4.5 VIN - V Figure 12. Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 LIGHT LOAD OUTPUT VOLTAGE RIPPLE IN POWER SAVE MODE RDSON NMOS vs VIN 0.3 Power Save Mode Mode/Data = low IOUT = 10mA 0.25 RDSon - W 85°C VOUT = 1.8V 20mV/Div 0.2 25°C -40°C Inductor current 100mA/Div 0.15 0.1 0.05 2.5 3 3.5 4 4.5 5 5.5 6 VIN - V Time base - 10 ms/Div Figure 13. Figure 14. OUTPUT VOLTAGE RIPPLE IN FORCED PWM MODE OUTPUT VOLTAGE RIPPLE IN PWM MODE Mode/Data = high, forced PWM MODE operation PWM MODE OPERATION VOUT = 1.8V IOUT = 400mA IOUT = 10mA VOUT ripple 20mV/Div VOUT = 1.8V 20mV/Div Inductor current 100mA/Div Inductor current 200mA/Div Time base - 400 ns/Div Time base - 200 ns/Div Figure 15. Figure 16. Submit Documentation Feedback 11 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 FORCED PWM/PFM MODE TRANSITION Forced PWM Mode MODE/DATA 1V/Div LOAD TRANSIENT RESPONSE PFM/PWM VOUT = 1.575V 50mV/Div MODE/DATA = low Enable Power Save Mode Entering PFM Mode Voltage positioning active Voltage positioning in PFM Mode reduces voltage drop during load step PWM Mode operation IOUT1 = 540mA VOUT 20mV/Div VOUT = 1.8V IOUT = 20mA IOUT 200mA/Div IOUT= 60mA Time base - 20 ms/Div Time base - 100 ms/Div Figure 17. Figure 18. LOAD TRANSIENT RESPONSE PWM OPERATION LINE TRANSIENT RESPONSE MODE/DATA = high PWM Mode operation VOUT = 1.575V 50mV/Div IOUT 200mA/Div VIN 3.6V to 4.6V VIN 1V/Div MODE/DATA = high IOUT1 = 540mA VOUT 1.575 IOUT 200mA VOUT 50mV/Div IOUT= 60mA Time base - 400 ms/Div Time base - 100 ms/Div Figure 19. 12 Figure 20. Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V STARTUP TIMING ONE CONVERTER EN1 / EN2 5V/Div SW1 5V/Div VIN = 3.8V IOUT1 max = 400mA I coil1 200mA/Div VOUT1 500mV/Div SW2 5V/Div SW1 1V/Div Icoil2 200mA/Div Icoil 500mA/Div VIN 3.6V, VOUT1: 1.575V VOUT2: 1.8V I OUT1 = IOUT2 = 200mA Time base - 100 ns/Div Time base - 200 ms/Div Figure 21. Figure 22. TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V SW1 5V/Div SW1 5V/Div I coil1 200mA/Div I coil1 200mA/Div SW2 5V/Div SW2 5V/Div Icoil2 200mA/Div VIN 3.6V, VOUT1 : 1.8V VOUT2 : 3.0V I OUT1 = I OUT2 = 200mA I coil2 200mA/Div VIN 3.6V, VOUT1 : 1.2V VOUT2 : 1.2V I OUT1 = I OUT2 = 200mA Time base - 100 ns/Div Time base - 100 ns/Div Figure 23. Figure 24. VOUT1 CHANGE WITH EASYSCALE DETAILED DESCRIPTION OPERATION The TPS62410 includes two synchronous step-down converters. The converters operate with typically 2.25MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If Power Save Mode is enabled, the converters automatically enter Power Save Mode at light load currents and operate in PFM (Pulse Submit Documentation Feedback 13 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 DETAILED DESCRIPTION (continued) Frequency Modulation). During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit. The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current. Converter 1 In the adjustable output voltage version TPS62410 the converter 1 output voltage can be set via an external resistor network on PIN DEF_1, which operates as an analog input. In this case, the output voltage can be set in the range of 0.6V to VIN V. The FB1 Pin must be directly connected to the converter 1 output voltage VOUT1. It feeds back the output voltage directly to the regulation loop. The output voltage of converter 1 can also be changed by the EasyScale serial Interface. This makes the device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network. Converter 2 In the adjustable output voltage version TPS62410, the converter 2 output voltage is set by an external resistor divider connected to ADJ2 Pin and uses an external feed forward capacitor of 33pF. It is also possible to change the output voltage of converter 2 via the EasyScale Interface. In this case, the ADJ2 Pin must be directly connected to converter 2 output voltage VOUT2. At TPS62410 no external resistor network may be connected. POWER SAVE MODE The Power Save Mode is enabled with Mode/Data Pin set to 0 for both converters. If the load current of a converter decreases, this converter will enter Power Save Mode operation automatically. The transition to Power Save Mode of a converter is independent from the operating condition of the other converter. During Power Save Mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically 1.01xVOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step. In order to optimize the converter efficiency at light load the average inductor current is monitored. The device changes from PWM Mode to Power Save Mode, if in PWM mode the inductor current falls below a certain threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 1 for each converter. Equation 1: Average output current threshold to enter PFM Mode VINDCDC I OUT_PFM_enter + 32 W (1) Equation 2: Average output current threshold to leave PFM Mode VINDCDC I OUT_PFM_leave + 24 W (2) In order to keep the output voltage ripple in Power Save Mode low, the output voltage is monitored with a single threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip comp) of 1.01 x VOUTnominal, the corresponding converter starts switching for a minimum time period of typically 1µs and provides current to the load and the output capacitor. Therefore the output voltage increases and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied by the output capacitor until the output voltage has dropped below the threshold again. 14 Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 DETAILED DESCRIPTION (continued) Hereupon the device starts switching again. The Power Save Mode is exited and PWM Mode entered in case the output current exceeds the current IOUT_PFM_leave, or if the output voltage falls below a second comparator threshold, called skip comparator low (Skip Comp Low) threshold. This skip comparator low threshold is set to –2% below nominal Vout, and enables a fast transition from Power Save Mode to PWM Mode during a load step. In Power Save Mode the quiescent current is reduced typically to 19µA for one converter and 32µA for both converters active. This single skip comparator threshold method in Power Save Mode results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values minimizes the output ripple. The Power Save Mode can be disabled through the MODE/DATA pin set to high. Both converters then operate in fixed PWM mode. Power Save Mode Enable/Disable applies to both converters. Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is activated in Power Save Mode operation. It provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. This improves load transient behavior. At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch. Smooth increased load +1% Fast load transient PFM Mode light load PFM Mode light load VOUT_NOM PWM Mode medium/heavy load PWM Mode medium/heavy load PWM Mode medium/heavy load COMP_LOW threshold –1% Figure 25. Dynamic Voltage Positioning Soft Start The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 26. EN 95% 5% VOUT tStartup tRAMP Figure 26. Soft Start Submit Documentation Feedback 15 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 DETAILED DESCRIPTION (continued) 100% Duty Cycle Low Dropout Operation The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range; i.e., the minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: Vin min + Vout max ) Iout max ǒRDSonmax ) R LǓ (3) With: Ioutmax = maximum output current plus inductor ripple current RDSonmax = maximum P-channel switch RDSon RL = DC resistance of the inductor Voutmax = nominal output voltage plus maximum output voltage tolerance With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency. Under-Voltage Lockout The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the converters. The under-voltage lockout threshold is typically 1.5V, max 2.35V. In case the default register values are overwritten by the Interface, the new values in the registers REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall under the under-voltage lockout threshold, independent of whether the converters are disabled. MODE SELECTION The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for both converters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pin interface to receive serial data from a host to set the output voltage. This is described in the section EasyScale Interface. Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load current range. Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. For additional flexibility it is possible to switch from Power Save Mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. In case the operation mode will be changed from forced PWM mode (MODE/DATA = high) to Power Save Mode Enable (MODE/DATA = 0) the Power Save Mode will be enabled after a delay time of typically ttimeout, which is a maximum of 520µs. The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1. ENABLE The device has for each converter a separate EN pin to start up each converter independently. If EN1, EN2 are set to high, the corresponding converter starts up with soft start as previously described. Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2µA. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry is switched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating. 16 Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 DETAILED DESCRIPTION (continued) DEF_1 PIN FUNCTION The DEF_1 pin is dedicated to converter 1 and works as an analog input for adjustable output voltage setting. Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from 0.6V to VIN. 180° OUT OF PHASE OPERATION In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. It prevents the high side switches of both converters to be turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply. SHORT-CIRCUIT PROTECTION Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the PMOS switch reaches its current limit, it will be turned off and the NMOS turned on. The PMOS only turns on again, once the current in the NMOS decreases below the NMOS current limit. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds typically 150°C the device goes into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. EasyScale™: One Pin Serial Interface for Dynamic Output Voltage Adjustment General EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC converters. The interface is based on a master – slave structure, where the master is typically a µController or Application processor. Figure 27 and Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte consists of five bit for information, two address bits and the RFA bit. RFA bit set to high indicates the Request For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared to other one-pin interfaces is that its bit detection is, to a large extent, independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires therefore no additional pin. Protocol All bits are transmitted MSB first and LSB last. Figure 28 shows the protocol without acknowledge request (bit RFA = 0), Figure 29 with acknowledge (bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the Mode/Data pin needs to be pulled high for at least tStart before the bit transmission starts with the falling edge. In case the Mode/Data line was already at high level (forced PWM Mode selection) no start condition need be applied prior the device address byte. The transmission of each byte needs to be closed with an End Of Stream condition for at least TEOS. Addressable Registers In TPS62410 two registers with a data content of 5 bits can be addressed to change the output voltage of both converters. With 5 bit data content, 32 different values for each register are available. Table 1 shows the addressable registers if DEF_1 pin acts as analog input with external resistors connected. The available output voltages for converter 1 are shown in Table 3, for converter 2 in Table 4. To generate these output voltages, a precise internal resistor divider network is used, which makes external resistors unnecessary and results therefore in an higher output voltage accuracy and less board space. Submit Documentation Feedback 17 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 DETAILED DESCRIPTION (continued) The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the Startup-time tStart (170µs) the interface is ready for data reception. Table 1. Addressable Registers for Adjustable Output Voltage Devices A1 A0 REG_DEF_1_High REGISTER Not available in TPS62410 adjustable version DESCRIPTION 0 1 D4 D3 D2 D1 D0 REG_DEF_1_Low Converter 1 output voltage setting 0 0 TPS62410 see Table 3 REG_DEF_2 Converter 2 output voltage 1 0 TPS62410 see Table 4, connect ADJ2 pin directly to VOUT2 Don’t use 1 1 Bit Decoding The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can be simplified to: High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 30 Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 30 The bit detection starts with a falling edge on the MODED/DATA pin and ends with the next falling edge. Depending on the relation between tLow and tHigh a 0 or 1 is detected. Acknowledge The Acknowledge condition is only applied if: • Acknowledge is requested by a set RFA bit • The transmitted device address matches with the device address of the device • 16 bits were received correctly In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time tACKN, which is max. 520µs. The Acknowledge condition is valid after an internal delay time tvalACK. This means the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master controller keeps the line low during this time. The master device can detect the acknowledge condition with it’s input by releasing the MODE/DATA pin after tvalACK and read back a 0. In case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied, thus the internal MOSFET will not be turned on and the external pullup resistor pulls MODE/DATA pin high after tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends. NOTE: The acknowledge condition may only be requested in case the master device has an open drain output. In case of a push pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the current to 500µA in case of an accidentally requested acknowledge to protect the internal ACKN-MOSFET. MODE Selection Because of the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs to determine when it has to decode the bit stream or to change the operation mode. The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level. The device stays also in forced PWM mode during the whole time of a protocol reception. With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at least ttimeout, the device get’s an internal timeout and Power Save Mode operation is enabled. 18 Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 A protocol which is sent within this time will be ignored, because the falling edge for the Mode change will be first interpreted as start of the first bit. In this case it is recommended to send first the protocol and change at the end of the protocol to Power Save Mode. DATA IN Start Start Device Address DA7 DA6 DA5 DA4 0 1 0 0 DATABYTE DA3 DA2 DA1 1 1 1 DA0 EOS Start RFA 0 A1 A0 D4 D3 D2 D1 D0 EOS DATA OUT ACK Figure 27. Easy Scale Protocol Overview Table 2. Easy Scale Bit Description BYTE BIT NUMBER NAME TRANSMISSION DIRECTION Device Address Byte 7 DA7 IN 0 MSB device address 6 DA6 IN 1 5 DA5 IN 0 4 DA4 IN 0 3 DA3 IN 1 2 DA2 IN 1 1 DA1 IN 1 0 DA0 IN 0 LSB device address 7(MSB) RFA IN Request For Acknowledge, if high, Acknowledge condition will applied by the device 6 A1 Address Bit 1 5 A0 Address Bit 0 4 D4 Data Bit 4 3 D3 Data Bit 3 2 D2 Data Bit 2 1 D1 Data Bit 1 4Ehex Databyte 0(LSB) D0 DESCRIPTION Data Bit 0 ACK OUT Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open drain output, Line needs to be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open drain output stage. In case of a push pull output stage Acknowledge condition may not be requested! tStart DATA IN tStart Address Byte DATA Byte Mode, Static High or Low Mode, Static High or Low DA7 0 DA0 0 TEOS RFA 0 D0 1 TEOS Figure 28. Easy Scale Protocol Without Acknowledge Submit Documentation Feedback 19 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 tStart tStart Address Byte DATA Byte Mode, Static High or Low Mode, Static High or Low DATA IN DA7 0 DA0 0 D0 1 RFA 1 T EOS tvalACK Controller needs to Pullup Data Line via a resistor to detect ACKN DATA OUT ACKN tACKN Acknowledge true, Data Line pulled down by device Acknowledge false, no pull down Figure 29. Easy Scale Protocol Including Acknowledge tLow tHigh Low Bit (Logic 0) tLOW tHigh High Bit (Logic 1) Figure 30. EasyScale – Bit Coding MODE/DATA ttimeout Power Save Mode Forced PWM MODE Power Save Mode Figure 31. MODE/DATA PIN: Mode Selection tStart Address Byte tStart DATA Byte MODE/DATA TEOS TEOS ttimeout Power Save Mode Forced PWM MODE Power Save Mode Figure 32. MODE/DATA Pin: Power Save Mode/Interface Communication 20 Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 Table 3. Selectable Output Voltages for Converter 1, With DEF1 Pin as Analog Input (TPS62410) TPS62410 OUTPUT VOLTAGE [V] REGISTER REG_DEF_1_LOW D4 D3 D2 D1 D0 VOUT1 Adjustable Output With Resistor Network on DEF_1 Pin 0 0 0 0 0 0.825 0 0 0 0 1 2 0.85 0 0 0 1 0 3 0.875 0 0 0 1 1 4 0.9 0 0 1 0 0 5 0.925 0 0 1 0 1 6 0.95 0 0 1 1 0 7 0.975 0 0 1 1 1 8 1.0 0 1 0 0 0 0 0.6V with DEF_1 Pin connected to VOUT1 1 9 1.025 0 1 0 0 1 10 1.050 0 1 0 1 0 11 1.075 0 1 0 1 1 12 1.1 0 1 1 0 0 13 1.125 0 1 1 0 1 14 1.150 0 1 1 1 0 15 1.175 0 1 1 1 1 16 1.2 1 0 0 0 0 17 1.225 1 0 0 0 1 18 1.25 1 0 0 1 0 19 1.275 1 0 0 1 1 20 1.3 1 0 1 0 0 21 1.325 1 0 1 0 1 22 1.350 1 0 1 1 0 23 1.375 1 0 1 1 1 24 1.4 1 1 0 0 0 25 1.425 1 1 0 0 1 26 1.450 1 1 0 1 0 27 1.475 1 1 0 1 1 28 1.5 1 1 1 0 0 29 1.525 1 1 1 0 1 30 1.55 1 1 1 1 0 31 1.575 1 1 1 1 1 Submit Documentation Feedback 21 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 Table 4. Selectable Output Voltages for Converter 2, (ADJ2 Connected to VOUT) OUTPUT VOLTAGE [V] FOR REGISTER REG_DEF_2 D4 D3 D2 D1 D0 VOUT2 Adjustable Output With Resistor Network on ADJ2 0 0 0 0 0 0.85 0 0 0 0 1 2 0.9 0 0 0 1 0 3 0.95 0 0 0 1 1 4 1.0 0 0 1 0 0 5 1.05 0 0 1 0 1 6 1.1 0 0 1 1 0 7 1.15 0 0 1 1 1 8 1.2 0 1 0 0 0 0 0.6V with ADJ2 Pin connected to VOUT2 1 22 9 1.25 0 1 0 0 1 10 1.3 0 1 0 1 0 11 1.35 0 1 0 1 1 12 1.4 0 1 1 0 0 13 1.45 0 1 1 0 1 14 1.5 0 1 1 1 0 15 1.55 0 1 1 1 1 16 1.6 1 0 0 0 0 17 1.7 1 0 0 0 1 18 1.8 1 0 0 1 0 19 1.85 1 0 0 1 1 20 2.0 1 0 1 0 0 21 2.1 1 0 1 0 1 22 2.2 1 0 1 1 0 23 2.3 1 0 1 1 1 24 2.4 1 1 0 0 0 25 2.5 1 1 0 0 1 26 2.6 1 1 0 1 0 27 2.7 1 1 0 1 1 28 2.8 1 1 1 0 0 29 2.85 1 1 1 0 1 30 3.0 1 1 1 1 0 31 3.3 1 1 1 1 1 Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 APPLICATION INFORMATION OUTPUT VOLTAGE SETTING Converter1 Adjustable Default Output Voltage Setting The output voltage can be calculated to: ǒ R 1 ) 11 R 12 V OUT + VREF Ǔ with an internal reference voltage VREF typical 0.6V (4) To keep the operating current to a minimum, it is recommended to select R12 within a range of 180kΩ to 360kΩ. The sum of R12 and R11 should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to choose lower values than 180kΩ for R12. Route the DEF_1 line away from noise sources, such as the inductor or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. An internal feed forward capacitor is connected to this pin, therefore there is no need for an external feed forward capacitor for converter 1. Converter 2 The default output voltage of converter 2 can be set by an external resistor network. For converter 2 the same recommendations apply as for converter 1. In addition to that, a 33pF external feed forward capacitor Cff2 for good load transient response must be used. The output voltage can be calculated to: ǒ R 1 ) 21 R 22 V OUT + VREF Ǔ with an internal reference voltage VREF typical 0.6V (5) Route the ADJ2 line away from noise sources, such as the inductor or the SW2 line. In case the interface is used for converter 2, connect ADJ2 pin directly to VOUT2 TPS62410 VIN 3.3 V – 6 V VIN FB 1 L1 SW1 CIN 10 mF 2.2 mH DEF_1 L2 SW2 3.3 mH MODE/ DATA ADJ2 GND COUT1 = 22 mF R12 180 kW EN_1 EN_2 R11 270 kW VOUT1 = 1.5 V up to 800 mA R21 Cff2 825 kW 33 pF VOUT2 = 2.85 V up to 800 mA COUT2 = 22 mF R22 220 kW Figure 33. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, low PFM Voltage ripple Optimized Submit Documentation Feedback 23 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 APPLICATION INFORMATION (continued) TPS62410 VIN 3.3 V – 6 V FB 1 VIN L1 SW1 CIN 10 mF 2.2 mH DEF_1 COUT1 = 10 mF R12 180 kW EN_1 EN_2 R11 270 kW VOUT1 = 1.5 V up to 800 mA L2 SW2 3.3 mH MODE/ DATA ADJ2 GND R21 Cff2 825 kW 33 pF VOUT2 = 2.85 V up to 800 mA COUT2 = 10 mF R22 220 kW Figure 34. Typical Application Circuit 1.5V/2.85V Adjustable Outputs OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The device is optimized to operate with inductors of 2.2µH to 4.7µH and output capacitors of 10µF to 22µF. For operation with a 2.2µH inductor, a 22µF capacitor is suggested. Inductor Selection The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency. Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is recommended because during heavy load transient the inductor current will rise above the calculated value. DI L + Vout 1 * Vout Vin L I Lmax + I outmax ) ƒ (6) DI L 2 (7) With: f = Switching Frequency (2.25MHz typical) L = Inductor Value ∆IL= Peak to Peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current will occur at maximum Vin. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. It must be considered, that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies. 24 Submit Documentation Feedback TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 APPLICATION INFORMATION (continued) Refer to Table 5 and the typical applications for possible inductors. Table 5. List of Inductors DIMENSIONS [mm3] INDUCTOR TYPE SUPPLIER 2.8x2.6×1.4 VLF3014 TDK 3×3×1.4 LPS3015 Coilcraft 3.9×3.9×1.7 LPS4018 Coilcraft Output Capacitor Selection The advanced fast response voltage mode control scheme of the two converters allows the use of small ceramic capacitors with a typical value of 10µF, without having large output voltage under and overshoots during heavy load transients. Ceramic X7R/X5R capacitors having low ESR values result in lowest output voltage ripple and are therefore recommended. If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. The RMS ripple current is calculated as: 1 * Vout 1 Vin I RMSCout + Vout ƒ L 2 Ǹ3 (8) At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: DVout + Vout 1 * Vout Vin L ƒ ǒ8 1 Cout ƒ Ǔ ) ESR (9) Where the highest output voltage ripple occurs at the highest input voltage Vin. At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Higher output capacitors like 22µF values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM Mode. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 10µF. The input capacitor can be increased without any limit for better input voltage filtering. LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 35. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Submit Documentation Feedback 25 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each converter use a common Power GND node and a different node for the Signal GND to minimize the effects of ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. The output voltage sense lines (FB 1, ADJ2, DEF_1) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW line). If the EasyScale interface is operated with high transmission rates, the MODE/DATA trace must be routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling. TPS62410 VIN 2.5 V – 6 V VIN EN_1 CIN EN_2 MODE/ DATA 10 mF FB 1 L2 Cff2 33 pF COUT2 3.3 mH SW1 SW2 3.3 mH R11 R21 DEF_1 ADJ2 R12 R22 PowerPAD GND Figure 35. Layout Diagram 26 L1 Submit Documentation Feedback COUT2 TPS62410 www.ti.com SLVS737 – FEBRUARY 2007 COUT1 CIN GND Pin connected with Power Pad COUT2 Figure 36. PCB Layout Submit Documentation Feedback 27 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 17-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS62410DRCR DRC 10 MLA 330 12 3.3 3.3 1.1 8 12 PKGORN T2TR-MS P TPS62410DRCT DRC 10 MLA 180 12 3.3 3.3 1.1 8 12 PKGORN T2TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) TPS62410DRCR DRC 10 MLA 346.0 346.0 29.0 TPS62410DRCT DRC 10 MLA 190.0 212.7 31.75 Pack Materials-Page 2 Height (mm) PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power Wireless www.ti.com/lpw Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated