S3843P Semiconductor Current Mode PWM Controller Descriptions The S3843 is fixed Current PWM controller for Off-line and DC-DC converter applications. The internal circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier current sensing comparator, and a high current totempole output for driving a power MOSFET. Protection circuitly includes built in under voltage lockout and current limiting. S3843 have UVLO threshold of 8.4V(on) and 7.6V(off). S3843 can operate within 100% duty cycle. Features • Optimized for off-line and DC to DC converters • Low start up current < 1 mA • Operating range up to 500 KHz • Pulse-by-pulse current limiting • Under Voltage Lock Out with hysteresis • High current totempole output • Short shutdown delay time ; typical 100nsec Ordering Information Type NO. S3843P Marking S3843P Package Code DIP-8 Outline Dimensions unit : mm PIN Connections 1. Output / Compensation 2. Voltage feedback. Input 3. Current sense Input 4. Rt/Ct 5. GND 6. Output 7. Vcc 8. Vref KSI-L007-000 1 S3843P Absolute Maximum Ratings Ta=25°C Characteristic Symbol Ratings Unit Supply Voltage Vcc 30 V Output Current Io 1 A Vi(ana) -0.3 to 6.3 V Isink(EA) 10 mA Pd 1 W Analog Inputs Error Amp. Output Sink current Power Dissipation Electrical Characteristics (Vcc=15V, Rt=10Kohm, Ct=3.3nF, Ta=0℃ to 70℃, Unless otherwise specified) Characteristic Symbol Test Condition Min. Typ. Max. Unit 1. Reference Section Output Voltage Vref Tj=25℃, Io=1mA 4.90 5.00 5.10 V Line Regulation Δ Vref 12V ≤ VCC ≤ 25V - 6 20 mV Load Regulation Δ Vref 1mA ≤ IO ≤ 20mA - 6 25 mV Isc Ta=25°C -30 -100 -180 mA Initial Accuracy FOSC Tj=25℃ 47 52 57 KHz Voltage Stability △f /△V 12V ≤ VCC ≤25V - 0.2 1.0 % Oscillator Voltage VOSC Vpin4, peak to peak - 1.7 - V Discharge Current Idischarge Tj=25°C, Pin4=2V 7.8 8.3 8.8 mA 2.42 2.50 2.58 V - -0.3 -2.0 ㎂ Output Short Current 2. Oscillator Section 3. Error Amp Section Input Voltage V2 VPIN1=2.5V Input Bias Current Ib - Open Loop Voltage Gain AVO1 2V ≤ VO≤ 4V 65 90 - ㏈ Unity Gain Bandwidth GBW Tj=25°C 0.7 1 - MHz VCC=12V to 25V 60 70 - ㏈ 2 6 - mA -0.5 -0.8 - mA PSRR Output Sink Current Output Source Current PSRR1 ISINK ISOURCE VPIN2=2.7V, VPIN1=1.1V VPIN2=2.3V, VPIN1=5V Output High Voltage VOH Vpin2=2.3V, R1=15 ㏀ to GN 5 6 - V Output Low Voltage VOL VPIN2=2.3V, R1=15 ㏀ to PIN8 - 0.7 1.1 V GV - 2.8 3.0 3.2 V/V 0.9 1.0 1.1 V 4. Current Sense Section Gain Maximum Input Signal Vi(MaX) VPIN 1=5V PSRR PSRR2 12V ≤ VCC ≤ 25V - 70 - ㏈ - - -2 -10 ㎂ VPIN 3=0V to 2V - 100 300 nS Input Bias Current Delay to Output I bias Td KSI-L007-000 2 S3843P Electrical Characteristics(continued) (Vcc=15V, Rt=10Kohm, Ct=3.3nF, Ta=0℃ to 70℃, Unless otherwise specified) Characteristic Symbol Test Condition Min. Typ. Max. Unit 5. Output Section Output Low Level1 VOL1 Isink=20mA - 0.1 0.4 V Output Low Level2 VOL2 Isink=200mA - 1.5 2.0 V Output High Level1 VOH1 Isource=20mA 13.0 13.5 - V Output High Level2 VOH2 Isource=200mA 12.0 13.5 - V VOL(UVLO) - VCC=6V, Isink = 1mA - 0.7 1.2 V Rise Time tr Tj=25°C, C1=1nF - 50 150 nS Fall Time tf Tj=25°C, C1=1nF - 50 150 nS 7.8 8.4 9 V 7 7.6 8.2 V 6. Under Voltage Lockout Section Start Threshold Vth - Min. Operating Voltage VtL After turn on 7. PWM Section Maximum Duty Cycle Dmax - 93 97 100 % Minimum Duty Cycle Dmin - - - 0 % Start-Up Current Ist - - 0.5 1 mA Operating Supply Current ICC Vpin2=Vpin3=0V - 11 20 mA ICC=25mA - 35 - V 8.Total Standby Section VCC Zener Voltage VZ NOTE: Adjust Vcc above the start threshold before setting at 15V Block Diagram 7 Vcc 5 GND 35V Vref 5V V ref 8 Set/ Res et UV LO LO G IC In t e r n a l Bi a s PWR Vc 1/2 V r e f Er r or Amp Vfb 2 + - C.S Comp 1/3 PWM LA T CH 7 Output R 6 1V S Com 1 PWR GND 5 C.S 3 T Rt/Ct 4 O s c i l l a t or KSI-L007-000 3 S3843P Information in using IC 1. Under voltage Lockout To prevent erratic output behavior which activating the power switch with extraneous leakage currents, 7 O N/O F F CO MM A ND T O R ES ET O F IC during under voltage lockout. Output(pin6) should be shunted to ground with a bleeder resister. V o n -8.4V V o f f -7.6V The Vcc comparator upper and lower threshold are 8.4V/7.6V. The large hysteresis and low start up Ic c currents makes it ideally suited in off-line converter application where efficient bootstrap start-up < 17mA techniques are required. < 1mA 7.6V V cc 8.4V 2. Oscillator Waveforms and Maximum Duty Cycle The oscillator frequency is programmed by the values LARGE Rt SMALL Ct Vpin4 8 selected for the timing components Rt and Ct. Ct is charged from 5V, Vref, through resistor Rt to Rt INTERNAL CLOCK 4 Ct SMALL Rt LARGE Ct approximately 2.8V and discharged to 1.2V by an internal current sink. During the discharge of Ct, the oscillator generates an Vpin4 internal blanking pulse and the center input NOR gate high. 5 This makes output to be in a low state and control the INTERNAL CLOCK amount of output dead time. 3. Error AMP Configuration 2.50V Error amp output(Pin1) is provided for external loop + 0.5mA compensation and error amp can source or sink up to 0.5mA. The non-inverting input is internally biased at 2.5V and is not pinned out. The converter output voltage is typically Vin Zt 2 Zf - divided down and monitored by the inverting input(pin2). COMP 1 KSI-L007-000 4 S3843P 4. Current Sense Circuit ER R O R A MP 2R Iβ R IV 1 R (V p i n 1 - 2V b e ) CUR R ENT S E NS E C O MP A R A T O R CO MP Ip e a k = R 3R x R s 3 C CUR R E NT S ENS E G ND Rs 5 A normal operating conditions occurs when the power supply output is overloaded or if output voltage to 1.0V Therefore the maximum peak switch current is lpk(max)=1.0V/Rs, and under the normal operating conditions the peak inductor current controlled by the voltage at pin1. 5. Shutdown Techniques 4.7K 8 V 3 4.7K 1 RE F CO MP accomplished by two methods; ISEN SE either raise pin3 above 1V or pull 5.00 S HUT DO W N Shutdown of the S3843 can be pin1 below a voltage two diodes S HUT DO W N drops above ground. Either causes T O CUR R E NT S E NS E R ES I S T O R the output of the PWM method comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which turn off, allowing the SCR to reset. KSI-L007-000 5 S3843P 6. Open Loop Test V REF RT 2N2222 4.7K V cc 100K V REF 5 1 COMP 4.7K I SENSE ADJUST 2 V in 3 I SENSE 4 R T /CT S3843 ERROR 1K AMP ADJUST V cc 6 OUTPUT 7 GND 0.1uF 0.1uF 1K/1W OUTPUT 8 GROUND High peak currents associated with capacitive leads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin5 in a single point ground. The transistor and 5 ㏀ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin 3. 7. Slope Compensation V A fraction of the oscillator ramp can be resistively 0.1u F RE F 8 summed with the current sense signal to provide RT R T /C T 4 CT slope compensation for converters requiring duty cycle over 50%. Note that capacitor C, forms a R1 R2 I SEN SE I SEN SE 3 C filter with R2 to suppress the leading edge switch spikes. R SEN SE KSI-L007-000 6 S3843P Electrical Characteristic Curves OUTPUT DEAD-TIME vs. OSCILLATOR FREQUENCY TIMING RESISTOR vs. OSCILLATOR FREQUENCY 80 V c c =15V Ta = 25o C 50 50 5.0n F 2.0n F R T TIMING RESISTOR (KΩ) %DT PERCENT OUTPUT DEAD-TIME 100 1.0n F 20 Ct =10n F 500pF 10 5.0 200pF 100pF 2.0 1.0 10K 20K 50K 100K 200K 500K 1.0M 500pF 20 200pF 8.0 5.0 2.0 V c c =15V Ta = 25o C 0.8 10K 100K 60 -45 φ -90 o ) -135 AV SATURATION VOLTAGE (V) 0 Ta = 25o C 3 Ta=-55o C 2 SOURCE SAT(Vcc-VOH) 1 SINK SAT(VOL) 0 100 1K 10K 100K 1M 500K 1.0M Vcc=15V -180 10 200K 4 80 0 50K Output Saturation Characteristics PHASE ( VOLTAGE GAIN (dB) Error Amplifier Open-Loop Frequency Response 20 20K 2.0n F 1.0n F C T =10n F f OSC OS CILLATOR FREQUENCY (KHz ) f OSC O S CILLA TO R FREQ UENCY (KHz ) 40 100pF 5.0n F 10M 0.1 0.2 0.3 0.4 0.5 0.7 1 2 3 4 5 7 10 OUTPUT CURRENT SOURCE OR SINK (A) FREQUENCY (Hz) KSI-L007-000 7