@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT CURRENT MODE PWM CONTROL CIRCUITS DESCRIPTION SOP-8 The @vic AV3842A/3843A provide the necessary functions to implement off-line or DC to DC fixed frequency current mode , controlled switching circuits with a minimal external part count FEATURES *Low external part count. *Low start up current ( Typical 0.12mA ) *Automatic feed forward compensation *Pulse-by-Pulse current limiting *Under-voltage lockout with hysteresis *Double pulse Suppression *High current totem pole output to drive MOSFET directly *Internally trimmed band gap reference *500kHz operation DIP-8 BLOCK DIAGRAM 7 Vref 8 5V REF Vcc S/R 5 GND Internal Bias 1/2Vref U.V.L.O Vref Good Logic 1/3Vref VFB 2 COMP 1 CURRENT SENSE COMPARATOR 1V ERROR AMPLIFIER 7 R PWM LATCH S 6 Vcc OUTPUT CURRENT SENSE 3 RT/CT 5 GND 4 OSCILLATOR ABSOLUTE MAXIMUM RATINGS(Ta=25°C) PARAMETER SYMBOL Supply Voltage(Low Impedance Source) Supply Voltage(Icc<30mA) Output Current ( Peak ) Output Energy(capacity Load) Analog Inputs(pin 2,3) Error Amplifier Output Sink Current Power Dissipation VCC Vcc Io Lead Temperature( Soldering 10 Sec ) VI(ANA) ISINK(EA) PD DIP-8 SOP-8 Tlead VALUE 30 Self Limiting +-1 5 -0.3 ~ +6.3 10 at Tamb<=25°C 1.0 at Tamb<=25°C 0.5 300 UNIT V V A µJ V mA W W °C QW-R103-002,B @vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT (continued) PARAMETER SYMBOL Storage Temperature Operating junction temperature Note 1: Ta>25°C, PD derated with 8mW/°C. Tstg Tj VALUE UNIT °C °C -65 ~ +150 +150 ELECTRICAL CHARACTERISTICS (0°C <=Ta<=70°C,VCC=15V,RT=10kΩ,CT=3.3nF,unless otherwise specified) PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VREF ∆VREF ∆VREF Tj=25°C,Io=1mA 12<=VIN<=25V 1<=Io=20mA (Note 2) Line, Load, Temp(note 2) 10Hz<=f<=10kHz,Tj=25°C (note 2) Ta=25°C,1000Hrs(note 2) 4.9 5 6 6 0.2 5.1 20 25 0.4 5.18 V mV mV mV/°C V uV mV mA Vosc ISC 4.82 -30 50 5 -100 25 -180 Oscillator Section Initial Accuracy Voltage Stability Temperature Stability Amplitude f ∆f/∆Vcc Vosc Tj=25°C 12<=Vcc<=25V Tmin<=TA<=Tmax(note 2) Vpin 4 peak to peak 47 52 0.2 5 1.7 57 1 kHz % % V Vpin 1=2.5V 2.42 2.58 -2 2 <=Vo<=4V Tj=25°C (note 2) I2<=Vcc<=25V Vpin 2=2.7V,Vpin 1=1.1V Vpin 2=2.3V,Vpin 1=5V Vpin 2=2.3V, RL=15kΩ to GND Vpin 2=2.7V,Vpin 1=1.1V 60 0.7 60 2 -0.5 5 2.50 -0.3 90 1 70 6 -0.8 6 0.7 V µA dB MHz dB mA mA V V (note 3,4) Vpin 1=5V( note 3) 12<=Vcc<=25V 2.85 0.9 3.15 1.1 Vpin 3=0 to 2V 3 1 70 -2 150 Isink=20mA Isink=200mA Isource=20mA Isource=200mA Tj=25°C,CL=1nF(note 2) Tj=25°C,CL=1nF(note 2) 0.1 1.5 13.5 13.5 50 50 0.4 2.2 150 150 14.5 7.8 8.5 16 8.4 10 17.5 9 11.5 V V 7 7.6 8.2 V Error Amplifier Section Input Voltage Input Bias Current AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current Vout High Vout Low VI(EA) IBIAS Isink Isource VOH VOL 1.1 Current Sense section Gain Maximum Input signal PSRR Input Bias Current Delay to Output GV VI(MAX) IBIAS -10 300 V/V V dB µA ns Output Section Output Low Level VOL Output High Level VOH Rise Time Fall Time tR tF 13 12 V V V V ns ns Under-Voltage Lockout Output Section Start Threshold Min. Operating Voltage VTH(ST) VOPR(min) UTC3842A UTC3843A After Turn On UTC3842A UTC3843A PWM Section QW-R103-002,B @vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT PARAMETER SYMBOL Maximum Duty Cycle Minimum Duty Cycle TEST CONDITIONS D(MAX) D(MIN) MIN TYP MAX UNIT 95 97 100 0 % % 0.12 11 34 0.3 17 mA mA V Total Standby Current Start-up Current IST Operating Supply Current ICC(opr) Vpin 2=Vpin 3=0V Vcc Zener Voltage Vz Icc=25mA note 2:These parameters, although guaranteed ,are not 100% tested in production. note 3:Parameters measured at trip point of latch with Vpin 2=0. note 4:Gain defined as: A= ∆Vpin 1 ∆Vpin 3 ; 0<=Vpin3<=0.8V note 5:Adjust Vcc above the start threshold before setting at 15V. OPEN-LOOP LABORATORY TEST FIXTURE 4.7kΩ Vref 8 2 7 3 6 4 5 A 0.1 µF Isense Adjust 4.7kΩ Error Amp Adjust 1 0.1 µF 100kΩ RT Vcc 1kΩ / 1W OUTPUT 5kΩ CT High peak current associated with capacity loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in single point GND. The transistor and 5kΩ potentio-meter are used to sample the oscillator waveform and apply an adjustable Ramp to Pin 3. UNDER-VOLTAGE LOCKOUT Icc Vcc 7 ON/OFF Command to rest of IC Von=16V Voff=10V <15mA <1mA Voff Von Vcc During Under-Voltage Lockout, the output driver is biased to a high impedance state. Pin 6 should be shunt to GND with a bleeder resistor to prevent activating the power switch with output leakage currents. QW-R103-002,B @vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT ERROR AMPLIFIER CONFIGURATION 2.5V 0.5mA 2 Zi Zf 1 Error amplifier can source or sink up to 0.5mA CURRENT SENSE CIRCUIT Error Amplifier 2R Is R 1 R Current Sense Comparator 3 Rs 1V C 5 Peak current (Is) determined by the formula: Ismax=10V/Rs. A small RC filter be required to suppress switch transients. 8 0.1 µF SLOPE COMPENSATION RT 4 CT 3 R1 R2 C Isense Rsense A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converts requiring duty cycles over 50%.Note that capacitor C, forms a filter with R2 to suppress the leading edge switch spikes. QW-R103-002,B @vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT OSCILLATOR SECTION V4 Large RT Small CT 8 INTERNAL CLOCK RT 4 V4 CT Small RT Large CT 5 Dead time VS CT(RT>5kΩ) 100 INTERNAL CLOCK Timing Resistance Vs Frequency 100 td (µs) CT=1nF RT (kΩ) CT=2.2nF 10 CT=4.7nF CT=10nF 10 CT=22nF 1 CT=47nF CT=100nF 1 0.1 1 10 100 10 2 10 3 10 4 10 5 10 6 Frequency (Hz) CT (nF) SHUTDOWN TECHNIQUES 330Ω 1kΩ Shutdown 3 500Ω Shutdown 1 8 To current Sense resistor Shutdown UTC UC3842A can be accomplished by two methods; either raise pin 3 above 1V or pull Pin 1 below a voltage two diode drops above ground. Either method caused the output of PWM comparator to be high(refer to block diagram).The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed . In one example, an externally latched shut –down may be accomplished by adding an SCR which be reset by cycling Vcc below the lower UVLO threshold. At this point the reference turns off allowing the SCR to reset. QW-R103-002,B @vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT TYPICAL PERFORMANCE CHARACTERISTICS 4 Saturation Voltage (V) Voltage Gain (dB) Vcc=15V Ta=+25°C Ta=-55°C 3 2 80 0 60 -45 40 -90 20 -135 0 -180 PHASE (Degree) 100 1 0 0.01 0.1 1 10 2 10 10 Output Current (Sourse or Sink Current) (A) 3 10 4 10 5 10 6 10 7 Frequency (Hz) Output Saturation Characteristics Error Amplifier Open-Loop Frequency Response Vref Temperature Drift Istart Temperature Drift 5.02 550 Vref (V) 5.01 500 Vcc=15V Io=1mA Vcc=9V 5.00 Istart (mA) 450 4.99 400 4.98 350 4.97 300 4.96 -50 -25 0 25 50 75 100 125 150 250 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) Icc Temperature Drift 15 Icc (mA) 14 Vcc=15V Io=1mA 13 12 11 10 9 -50 -25 0 25 50 75 100 125 150 Temperature (°C) QW-R103-002,B