BB ADS824

®
ADS824
ADS
824
E
10-Bit, 70MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
DESCRIPTION
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The ADS824 is a pipeline, CMOS analog-to-digital converter
that operates from a single +5V power supply. This converter
provides excellent performance with a single-ended input and
can be operated with a differential input for added spurious
performance. This high performance converter includes a 10-bit
quantizer, high bandwidth track/hold, and a high accuracy
internal reference. It also allows for the user to disable the
internal reference and utilize external references. This external
reference option provides excellent gain and offset matching
when used in multi-channel applications or in applications
where full scale range adjustment is required.
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HIGH SNR: 59dB
HIGH SFDR: 70dB
LOW POWER: 315mW
INTERNAL/EXTERNAL REFERENCE
OPTION
SINGLE-ENDED OR DIFFERENTIAL
ANALOG INPUT
PROGRAMMABLE INPUT RANGE:
1Vp-p or 2Vp-p
LOW DNL: 0.3LSB
SINGLE +5V SUPPLY OPERATION
+3V DIGITAL OUTPUT CAPABILITY
POWER DOWN: 20mW
28-LEAD SSOP PACKAGE
The ADS824 is specified at a maximum sampling frequency of
70MHz and a single-ended input range of 1.5V to 3.5V. The
ADS824 is available in a 28-lead SSOP package and is pin
compatible with the 10-bit, 40MHz ADS822 and the 10-bit,
60MHz ADS823.
APPLICATIONS
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●
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The ADS824 employs digital error correction techniques to
provide excellent differential linearity for demanding imaging
applications. Its low distortion and high SNR give the extra
margin needed for medical imaging, communications, video,
and test instrumentation. The ADS824 offers power dissipation of 315mW and also provides a power-down mode, thus
reducing power dissipation to only 20mW.
MEDICAL IMAGING
HDTV VIDEO DIGITIZING
COMMUNICATIONS
TEST EQUIPMENT
+VS
CLK
VDRV
ADS824
Timing
Circuitry
VIN
IN
IN
T/H
10-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•
•
•
D9
Internal
Reference
CM
Optional External
Reference
Int/Ext
PD
OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1997 Burr-Brown Corporation
PDS-1403C
Printed in U.S.A. April, 1999
SPECIFICATIONS
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 70MHz, external reference, unless otherwise noted.
ADS824E
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
SPECIFIED TEMPERATURE RANGE
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Voltage
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
Track-Mode Input Bandwidth
Ambient Air
2Vp-p
1Vp-p
1.5
2
2Vp-p
2
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current(5) (VIN = 5V)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA)
Low Output Voltage, (IOL = 1.6mA)
High Output Voltage, (IOH = 50µA)
High Output Voltage, (IOH = 0.5mA)
Low Output Voltage, (IOL = 50µA)
High Output Voltage, (IOH = 50µA)
3-State Enable Time
3-State Disable Time
Output Capacitance
°C
3
1
1.25 || 5
300
10k
±0.3
±0.3
Guaranteed
±0.5
V
V
V
V
µA
MΩ || pF
MHz
70M
Samples/s
Clk Cyc
±1.0
LSB
LSB
±3.0
LSBs
5
Referred to Full Scale
60
70
68
dBFS(2)
dBFS
–63.4
dBc
59
59
dB
dB
58
58
9.3
0.2
3
1.2
2
5
dB
dB
Bits
LSBs rms
ns
ps rms
ns
ns
Referred to Full Scale
55
Referred to Full Scale
50
Input Grounded
CMOS-Compatible
Rising Edge of Convert Clock
Start Conversion
100
10
+3.5
+1.0
5
µA
µA
V
V
pF
CMOS-Compatible
Straight Offset Binary
VDRV = 5V
+0.1
+0.2
+4.9
+4.8
VDRV = 3V
+0.1
+2.8
OE = L
OE = H
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (Referred to –FS)
at 25°C
Zero Error Drift (Referred to –FS)
Gain Error(6)
at 25°C
Gain Error Drift(6)
Gain Error(7)
at 25°C
Gain Error Drift(7)
Power Supply Rejection of Gain
∆ VS = ±5%
REFT Tolerance
Deviation from Ideal 3.5V
REFB Tolerance
Deviation From Ideal 1.5V
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
®
ADS824
Bits
3.5
3
–3dBFS
UNITS
–40 to +85
2.5
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range(1)
f = 1MHz
f = 10MHz
Two-Tone Intermodulation Distortion(3)
f = 4.5MHz and 5.5MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits(4), f = 1MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
Full-Scale Step Acquisition Time
MAX
10 Guaranteed
2
REFB + 0.8
1.25
20
2
5
40
10
±0.5
12
±1.5
38
±0.75
20
68
±10
±10
3.5
1.5
1.6
±3.0
±2.5
±1.5
±25
±25
VS – 1.25
REFT – 0.8
V
V
V
V
V
V
ns
ns
pF
%FS
ppm/°C
%FS
ppm/°C
%FS
ppm/°C
dB
mV
mV
V
V
kΩ
SPECIFICATIONS (CONT)
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 70MHz, external reference, unless otherwise noted.
ADS824E
PARAMETER
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Output Driver Supply Current (VDRV)
Power Dissipation: VDRV = 5V
VDRV = 3V
VDRV = 5V
VDRV = 3V
Power Down
Thermal Resistance, θJA
28-Lead SSOP
CONDITIONS
MIN
TYP
MAX
UNITS
Operating
Operating
+4.75
+5.0
66
9
330
315
345
335
20
+5.25
V
mA
mA
mW
mW
mW
mW
mW
External Reference
External Reference
Internal Reference
Internal Reference
Operating
375
°C/W
89
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) A 50kΩ pull-down resistor is inserted internally. (6) Includes internal
reference. (7) Excludes internal reference.
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SSOP
GND
1
28
VDRV
Bit 1 (MSB)
2
27
+VS
Bit 2
3
26
GND
Bit 3
4
25
IN
Bit 4
5
24
IN
Bit 5
6
23
CM
Bit 6
7
22
REFT
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
GND
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
OE
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD
CLK
+VS
GND
RSEL
INT/EXT
REFB
ByB
ByT
REFT
CM
IN
IN
GND
+VS
VDRV
ADS824
Bit 7
8
21
ByT
Bit 8
9
20
ByB
Bit 9 10
19
REFB
Bit 10 (LSB) 11
18
INT/EXT
OE 12
17
RSEL
PD 13
16
GND
CLK 14
15
+VS
DESCRIPTION
Ground
Data Bit 1 (D9) (MSB)
Data Bit 2 (D8)
Data Bit 3 (D7)
Data Bit 4 (D6)
Data Bit 5 (D5)
Data Bit 6 (D4)
Data Bit 7 (D3)
Data Bit 8 (D2)
Data Bit 9 (D1)
Data Bit 10 (D0) (LSB)
Output Enable. HI = high impedance state.
LO = normal operation (internal pulldown resistor)
Power Down. HI = power down; LO = normal
Convert Clock Input
+5V Supply
Ground
Input Range Select. HI = 2Vp-p; LO = 1Vp-p
Reference Select. HI = external; LO = internal
Bottom Reference
Bottom Ladder Bypass
Top Ladder Bypass
Top Reference
Common-Mode Voltage Output
Complementary Input (–)
Analog Input (+)
Ground
+5V Supply
Output Logic Driver Supply Voltage
®
3
ADS824
TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+7
N+6
tH
Clock
5 Clock Cycles
t2
Data Out
N–5
N–4
N–3
N–2
N–1
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
N
N+1
N+2
t1
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
13.4
6.4
6.4
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
6.7
6.7
3
3.9
12
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
ADS824E
"
SSOP-28
"
324
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
–40°C to +85°C
"
ADS824E
"
ADS824E
ADS824E/1K
Rails
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of ADS824E/iK” will get a single 1000piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
DEMO BOARD ORDERING INFORMATION
PRODUCT
DEMO BOARD
ADS824E
DEM-ADS824E
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS
+VS ....................................................................................................... +6V
Analog Input ............................................................. –0.3V to (+VS + 0.3V)
Logic Input ............................................................... –0.3V to (+VS + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.
®
ADS824
4
TYPICAL PERFORMANCE CURVES
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 70MHz, external reference, unless otherwise noted.
SPECTRAL PERFORMANCE
(Single-Ended Input, 1Vp-p)
SPECTRAL PERFORMANCE
0
0
fIN = 10MHz
SNR = 55.7dBFS
SFDR = 69.7dBFS
fIN = 10MHz
–20
Amplitude (dB)
Magnitude (dB)
–20
–40
–60
–80
–40
–60
–80
–100
–100
0
8.5
17.5
25.75
35
0
8.25
Frequency (MHz)
SPECTRAL PERFORMANCE
(Differential Input, 2Vp-p)
35
SPECTRAL PERFORMANCE
fIN = 10MHz
SNR = 59dBFS
SFDR = 73dBFS
fIN = 20MHz
–20
Magnitude (dB)
–20
Magnitude (dB)
25.75
0
0
–40
–60
–40
–60
–80
–80
–100
–100
0
8.25
17.5
25.75
0
35
8.25
17.5
25.75
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(Single-Ended Input, 1Vp-p)
SPECTRAL PERFORMANCE
(Differential Input, 2Vp-p)
0
35
0
fIN = 20MHz
SNR = 55dBFS
SFDR = 69dBFS
fIN = 20MHz
SNR = 59dBFS
SFDR = 69dBFS
–20
Magnitude (dB)
–20
Magnitude (dB)
17.5
Frequency (MHz)
–40
–60
–80
–40
–60
–80
–100
–100
0
8.25
17.5
25.75
35
0
Frequency (MHz)
8.25
17.5
25.75
35
Frequency (MHz)
®
5
ADS824
TYPICAL PERFORMANCE CURVES (CONT)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 70MHz, external reference, unless otherwise noted.
TWO-TONE INTERMODULATION DISTORTION
(Differential Input, 2Vp-p)
UNDERSAMPLING
(Differential Input, 2Vp-p)
0
0
fS = 41MHz
fIN = 75MHz
SNR = 58.6dBFS
SFDR = 67dBFS
–20
Magnitude (dB)
Magnitude (dB)
–20
f1 = 9.5MHz at –7dBFS
f2 = 9.9MHz at –7dBFS
IMD (3) = –63.4dBc
–40
–60
–40
–60
–80
–80
–100
–100
0
5.13
10.25
15.38
0
20.5
8.75
17.50
26.25
35
Frequency (MHz)
Frequency (MHz)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
65
65
SINAD (dBFS)
SFDR, SNR (dBFS)
75
SFDR
70
65
SNR
60
fIN = 10MHz
55
fIN = 20MHz
60
50
55
0.1
1
10
–50
100
–25
0
25
50
75
Frequency (MHz)
Temperature (°C)
DYNAMIC PERFORMANCE vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
100
0.35
75
fIN = 10MHz
70
65
DLE (LSB)
SFDR, SNR (dBFS)
SFDR (fIN = 10MHz)
SFDR (fIN = 20MHz)
0.3
0.25
SNR (fIN = 10MHz)
60
SNR (fIN = 20MHz)
0.20
55
–50
–25
0
25
50
75
–50
100
®
ADS824
–25
0
25
50
Temperature (°C)
Temperature (°C)
6
75
100
TYPICAL PERFORMANCE CURVES (CONT)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 70MHz, external reference, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR
POWER DISSIPATION vs TEMPERATURE
1.0
360
VDRV = +5V
fIN = 10MHz
0.5
DLE (LSB)
Power (mW)
350
340
Internal Reference
0
–0.5
330
External Reference
–1.0
320
–50
–25
0
25
50
75
0
100
256
512
768
Temperature (°C)
DIFFERENTIAL LINEARITY ERROR
INTEGRAL LINEARITY ERROR
1.0
2.0
fIN = 20MHz
fIN = 1MHz
0.5
1.0
ILE (LSB)
DLE (LSB)
1024
Output Code
0
–0.5
0
–1.0
–1.0
–2.0
0
256
512
768
1024
0
256
Output Code
512
768
1024
Output Code
SWEPT POWER SFDR
OUTPUT NOISE HISTOGRAM (DC Input)
100
800k
fIN = 10MHz
80
dBFS
60
Counts
SFDR (dB)
600k
dBc
40
400k
200k
20
0
0
–60
–50
–40
–30
–20
–10
N-2
0
N-1
N
N+1
N+2
Output Code
Input Amplitude (dBFS)
®
7
ADS824
APPLICATION INFORMATION
depend on the individual application requirements and system structure. For example, communications applications
often process a band of frequencies that do not include DC,
whereas in imaging applications, the previously restored DC
level must be maintained correctly up to the A/D converter.
Features on the ADS824 such as the input range select
(RSEL pin) or the option for an external reference, provide
the needed flexibility to accommodate a wide range of
applications. In any case, the ADS824 should be configured
such that the application objectives are met while observing
the headroom requirements of the driving amplifier in order
to yield the best overall performance.
THEORY OF OPERATION
The ADS824 is a high-speed, CMOS analog-to-digital converter which employs a pipelined converter architecture
consisting of 9 internal stages. Each stage feeds its data into
the digital error correction logic ensuring excellent differential linearity and no missing codes at the 10-bit level. The
output data becomes valid on the rising clock edge (see
Timing Diagram). The pipeline architecture results in a data
latency of 5 clock cycles.
The analog input of the ADS824 is a differential track and
hold (see Figure 1). The differential topology along with
tightly matched capacitors produce a high level of acperformance while sampling at very high rates.
INPUT CONFIGURATIONS
AC-Coupled, Single-Supply Interface
Figure 2 shows the typical circuit for an ac-coupled analog
input configuration of the ADS824 while all components are
powered from a single +5V supply.
The ADS824 allows its analog inputs to be driven either
single-ended or differentially. The typical configuration for
the ADS824 is for the single-ended mode in which the input
track-and-hold performs a single-ended-to-differential conversion of the analog input signal.
With the RSEL pin connected high, the full-scale input
range is set to 2Vp-p. In this configuration, the top and
bottom references (REFT, REFB) provide an output voltage
of +3.5V and +1.5V, respectively. Two resistors ( 2x 1.0kΩ)
are used to create a common-mode voltage (VCM) of approximately +2.5V to bias the inputs of the driving amplifier
A1. Using the OPA680 on a single +5V supply, its ideal
common-mode point is at +2.5V, which coincides with the
recommended common-mode input level for the ADS824.
This obviates the need of a coupling capacitor between the
amplifier and the converter. Even though the OPA680 has an
ac gain of +2, the dc gain is only +1 due to the blocking
capacitor at resistor RG.
Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level
(+VS/2).
The following application discussion focuses on the singleended configuration. Typically, its implementation is easier
to achieve and the rated specifications for the ADS824 are
characterized using the single-ended mode of operation.
DRIVING THE ANALOG INPUT
The ADS824 achieves excellent ac performance either in the
single-ended or differential mode of operation. The selection
for the optimum interface configuration will
Op Amp
Bias
φ1
VCM
φ1
CH
φ2
CI
IN
IN
φ1
The addition of a small series resistor (RS) between the
output of the op amp and the input of the ADS824 will be
beneficial in almost all interface configurations. This will
decouple the op amp’s output from the capacitive load and
avoid gain peaking, which can result in increased noise. For
best spurious and distortion performance, the resistor value
should be kept below 100Ω. Furthermore, the series resistor,
in combination with the 10pF capacitor, establishes a passive low-pass filter, limiting the bandwidth for the wideband
noise thus, help improving the SNR performance.
φ2
AC-Coupled, Dual Supply Interface
The circuit provided in Figure 3 shows typical connections
for the analog input in case the selected amplifier operates
on dual supplies. This might be necessary to take full
advantage of very low distortion operational amplifiers, like
the OPA642. The advantage is that the driving amplifier can
be operated with a ground referenced bipolar signal swing.
This will keep the distortion performance at its lowest since
the signal range stays within the linear region of the op amp
and sufficient headroom to the supply rails can be maintained. By capacitively coupling the single-ended signal to
the input of the ADS824, its common-mode requirements
can easily be satisfied with two resistors connected between
the top and bottom reference.
OUT
φ1
OUT
φ1
CI
φ2
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-overlapping Clock
φ1
φ2
φ1
FIGURE 1. Simplified Circuit of Input Track-and-Hold with
Timing Diagram.
®
ADS824
8
1.0kΩ
+5V
VCM +2.5V
1.0kΩ
+5V
0.1µF
50Ω
REFB
+1.5V
RS
50Ω
VIN
REFT
+3.5V
RSEL
+VS
IN
OPA680
10pF
+VIN
0V
ADS824
RF
402Ω
–VIN
CM
IN
RG
402Ω
0.1µF
INT/EXT
0.1µF
GND
FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived
From The Internal Top (REFT) and Bottom Reference (REFB).
+5V
1.0kΩ
+5V
RS
24.9Ω
VIN
REFT
+3.5V
0.1µF
RSEL
+VS
IN
OPA642
100pF
–5V
RF
402Ω
ADS824
1.0kΩ
CM
IN
0.1µF
RG
402Ω
REFB
+1.5V
INT/EXT
GND
FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS823 for a 2Vp-p Full-Scale Input Range.
using the +2.5V common-mode voltage available at the
CM pin. One-half of amplifier A1 buffers the REFB pin and
drives the voltage divider R1, R2. Because of the op amp’s
noise gain of +2V/V, assuming RF = RIN, the common-mode
voltage (VCM) has to be re-scaled to +1.25. This results in
the correct DC level of +2.5V for the signal input (IN). Any
DC voltage differences between the IN and IN inputs of the
ADS824 effectively produces an offset, which can be corrected for by adjusting the resistor values of the divider, R1
and R2. The selection criteria for a suitable op amp should
include the supply voltage, input bias current, output voltage
swing, distortion, and noise specification. Note that in this
example, the overall signal phase is inverted. To re-establish
the original signal polarity, it is always possible to interchange the IN and IN connections.
For applications requiring the driving amplifier to provide a
signal amplification, with a gain ≥ 5, consider using decompensated voltage-feedback op amps, like the OPA643, or
current-feedback op amps like the OPA681 and OPA658.
DC-coupled with Level Shift
Several applications may require that the bandwidth of the
signal path include DC, in which case, the signal has to be
DC-coupled to the A/D converter. In order to accomplish
this, the interface circuit has to provide a DC level shift to
the analog input signal. The circuit shown in Figure 4
employs a dual op amp, A1, to drive the input of the
ADS824 and level shift the signal to be compatible with the
selected input range. With the RSEL pin tied to the supply
and the INT/EXT pin to ground, the ADS824 is configured
for a 2Vp-p input range and uses the internal references. The
complementary input (IN) may be appropriately biased
®
9
ADS824
+5V
RF
499Ω
RIN
499Ω
VIN
1/2
OPA2681
+VS
RSEL
RS
50Ω
IN
2Vp-p
10pF
ADS824
NOTE: RF = RIN, G = –1
CM (+2.5V)
IN
+5V
0.1µF
REFB
(+1.5V)
REFT
(+3.5V)
INT/EXT
50Ω
R2
200Ω
0.1µF
1/2
OPA2681
VCM = +1.25V
0.1µF
R1
1kΩ
RF
1kΩ
FIGURE 4. DC-Coupled Interface Circuit with Level Shifting Using Dual Current-Feedback Amplifier OPA2681.
SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION
(Transformer Coupled)
If the application requires a signal conversion from a singleended source to feed the ADS824 differentially, a RF transformer might be a good solution. The selected transformer
must have a center tap in order to apply the common-mode
DC voltage necessary to bias the converter inputs.
AC grounding the center tap will generate the differential
signal swing across the secondary winding. Consider a stepup transformer to take advantage of a signal amplification
without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to
an improved distortion performance.
The differential input configuration may provide a noticeable advantage of achieving good SFDR performance over
a wide range of input frequencies. In this mode, both inputs
of the ADS824 see matched impedances, and the differential
signal swing can be reduced to half of the swing required for
single-ended drive. Figure 5 shows the schematic for the
suggested transformer-coupled interface circuit. The com-
ponent values of the R-C low-pass may be optimized depending on the desired roll-off frequency. The resistor across
the secondary side (RT) should be calculated using the
equation RT = n2 x RG to match the source impedance (RG)
for good power transfer and Voltage Standing Wave Ratio
(VSWR).
REFERENCE OPERATION
Figure 6 depicts the simplified model of the internal reference circuit. The internal blocks are the bandgap voltage
reference, the drivers for the top and bottom reference, and
RSEL
ADS824
50kΩ
+VS
INT/EXT
50kΩ
Bandgap Reference and Logic
VREF
RG
0.1µF 1:n
22Ω
+1
VIN
+1
IN
47pF
RT
ADS824
400Ω
400Ω
400Ω
400Ω
22Ω
IN
CM
RSEL INT/EXT
47pF
REFT
ByT
CM
ByB
REFB
+5V
+
10µF
0.1µF
Bypass Capacitors: 0.1µF || 2.2µF each
FIGURE 5. Transformer Coupled Input.
®
ADS824
10
FIGURE 6. Equivalent Reference Circuit with Recommended
Reference Bypassing.
The common-mode voltage available at the CM-pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a common-mode voltage is given in Figure 7. Here, two external
precision resistors (tolerance 1% or better) are located
between the top and bottom reference pins. The commonmode voltage, CMV, will appear at the midpoint.
the resistive reference ladder. The bandgap reference circuit
includes logic functions that allows setting the analog input
swing of the ADS824 to either a 1Vp-p or 2Vp-p full-scale
range by simply tying the RSEL pin to a Low or High
potential, respectively. While operating the ADS824 in the
external reference mode, the buffer amplifiers for the REFT
and REFB are disconnected from the reference ladder.
As shown, the ADS824 has internal 50kΩ pull-up resistors
at the range select pin (RSEL) and reference select pin
(INT/EXT). Leaving these pins open configures the ADS824
for a 2Vp-p input range and external reference operation.
Setting the ADS824 up for internal reference mode requires
to bringing the INT/EXT pin low.
EXTERNAL REFERENCE OPERATION
For even more design flexibility, the internal reference can
be disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.
The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. The resistor ladder of
the ADS824 is divided into several segments and has two
additional nodes, ByT and ByB, which are brought out for
external bypassing only (Figure 6). To ensure proper operation with any reference configurations, it is necessary to
provide solid bypassing at all reference pins in order to keep
the clock feedthrough to a minimum. All bypassing capacitors should be located as close to their respective pins as
possible.
ADS824
REFT
+3.5V
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high speed,
high resolution A/D converters. Clock jitter leads to aperture
jitter (tA), which adds noise to the signal being converted. The
ADS824 samples the input signal on the rising edge of the
CLK input. Therefore, this edge should have the lowest
possible jitter. The jitter noise contribution to total SNR is
REFB
+1.5V
R2
1.0kΩ
R1
1.0kΩ
0.1µF
The external references can vary as long as the value of the
external top reference REFTEXT stays within the range of
(VS – 1.25V) and (REFB + 0.8V), and the external bottom
reference REFBEXT stays within 1.25V and (REFT – 0.8V).
See Figure 8.
0.1µF
CMV
+2.5V
FIGURE 7. Alternative Circuit to Generate CM Voltage.
+5V
B
A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)
+VS
VIN
A
RSEL
INT/EXT
GND
IN
ADS824
CMV
+2.5VDC
IN
REFT
External Top Reference
REFT = REFB +0.8V to +3.75V
ByT
GND
4 x 0.1µF || 2.2µF
ByB
REFB
External Bottom Reference
REFB = REFT –0.8V to +1.25V
FIGURE 8. Configuration Example for External Reference Operation.
®
11
ADS824
+5V or +3V, the ADS824 produces corresponding logic
levels and can directly interface to the selected logic family.
The output stages are designed to supply sufficient current to
drive a variety of logic families. However, it is recommended to use the ADS824 with +3V logic supply. This will
lower the power dissipation in the output stages due to the
lower output swing and reduce current glitches on the supply
line, which may affect the ac performance of the converter.
In some applications, it might be advantageous to decouple
the VDRV pin with additional capacitors or a pi-filter.
given by the following equation. If this value is near your
system requirements, input clock jitter must be reduced.
Jitter SNR = 20 log
1
rms signal to rms noise
2 π ƒ IN t A
where: ƒIN is input signal frequency
tA is rms clock jitter
Special consideration should be given to clock jitter, particularly in undersampling applications. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of performance. When
digitizing at high sampling rates, the clock should have 50%
duty cycle (tH = tL), along with fast rise and fall times of 2ns
or less.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. The ADS824 should be treated
as an analog component. Whenever possible, the supply pins
should be powered by the analog supply. This will ensure
the most consistent results since digital supply lines often
carry high levels of noise which otherwise would be coupled
into the converter and degrade the achievable performance.
All ground connections on the ADS824 are internally joined
together, obviating the design of split ground planes. The
ground pins (1, 16, 26) should directly connect to an analog
ground plane, which covers the PC board area around the
converter. While designing the layout, it is important to keep
the analog signal traces separated from any digital lines to
prevent noise coupling onto the analog signal path. Because
of its high sampling rate the, ADS824 generates high frequency current transients and noise (clock feedthrough) that
are fed back into the supply and reference lines. This
requires that all supply and reference pins be sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the ADS824. In most cases, 0.1µF ceramic chip
capacitors at each pin are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger bipolar capacitor (1µF to
22µF) should be placed on the PC board in proximity of the
converter circuit.
Digital Outputs
The output data format of the ADS824 is in positive Straight
Offset Binary code, see Tables I and II. This format can
easily be converted into the Binary Two’s Complement code
by inverting the MSB.
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS824 and affect the performance. If
necessary, external buffers or latches close to the converter’s
output pins may be used to minimize the capacitive loading.
They also provide the added benefit of isolating the ADS824
from any digital noise activities on the bus coupling back
high frequency noise.
SINGLE-ENDED INPUT
(IN = CMV)
+FS –1LSB (IN = REFT)
+1/2 Full Scale
Bipolar Zero (IN = CMV)
–1/2 Full Scale
–FS (IN = REFB)
STRAIGHT OFFSET BINARY
(SOB)
11
11
10
01
00
1111
0000
0000
0000
0000
1111
0000
0000
0000
0000
TABLE I. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage
(CMV).
DIFFERENTIAL INPUT
+FS –1LSB (IN = +3V, IN = +2V)
+1/2 Full Scale
Bipolar Zero (IN = IN = CMV)
–1/2 Full Scale
–FS (IN = +2V, IN = +3V)
STRAIGHT OFFSET BINARY
(SOB)
11
11
10
01
00
1111
0000
0000
0000
0000
ADS824
+VS
27
1111
0000
0000
0000
0000
GND
26
+VS
15
0.1µF
GND
16
0.1µF
VDRV
28
0.1µF
10µF
+
TABLE II. Coding Table for Differential Input Configuration
and 2Vp-p Full-Scale Range.
+5V
Digital Output Driver (VDRV)
The ADS824 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. By setting the voltage at VDRV to
FIGURE 9. Recommended Bypassing for the Supply Pins.
®
ADS824
+3/+5V
12