BB DAC716UB

®
DAC716
16-Bit DIGITAL-TO-ANALOG CONVERTER
with Serial Data Interface
FEATURES:
DESCRIPTION
● SERIAL DIGITAL INTERFACE
The DAC716 is a complete monolithic D/A converter
including a +10V temperature compensated voltage
reference, current-to-voltage amplifier, a high-speed
synchronous serial interface, a serial output which
allows cascading multiple converters, and an asynchronous clear function which immediately sets the
output voltage to zero.
The output voltage range is 0 to +10V while operating
from ±12V to ±15V supplies, and the gain and bipolar
offset adjustments are designed so that they can be set
via external potentiometers or external D/A converters. The output amplifier is protected against shortcircuiting to ground.
● VOLTAGE OUTPUT: 0 to +10V
● ±2 LSB INTEGRAL LINEARITY
● PRECISION INTERNAL REFERENCE
● LOW NOISE: 120nV/√Hz Including Reference
● 16-LEAD PLASTIC SKINNY DIP AND PLASTIC
SOIC PACKAGES
The 16-pin DAC716 is available in a plastic 0.3" DIP
and a wide-body plastic SOIC package. The DAC716P,
U, PB, and UB are specified over the –40°C to +85°C
range while the DAC716UK and PK are specified
over the 0°C to +70°C range.
A0
Input Shift Register
A1
SDO
16
SDI
CLK
D/A Latch
CLR
16
16-Bit D/A Converter
Reference
Circuit
VOUT
Offset Adjust
Gain
Adjust
VREF OUT
+10V
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1996 Burr-Brown Corporation
PDS-1324B
Printed in U.S.A. March, 1998
SPECIFICATIONS
At TA = +25°C, +VCC = +15V, –VCC = –15V, unless otherwise noted.
DAC716P, U
PARAMETER
MIN
TYP
DAC716PB, UB
MAX
MIN
TYP
DAC716PK, UK
MAX
MIN
TYP
MAX
UNITS
±2
±2
±2
±2
LSB
LSB
LSB
LSB
Bits
Bits
%
%
% of FSR(2)
% of FSR
%FSR/%VCC
ppm FSR/%VCC
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
TMIN to TMAX
Differential Linearity Error
TMIN to TMAX
Monotonicity
Monotonicity Over Spec Temp Range
Gain Error(3)
TMIN to TMAX
Unipolar Zero Error (3)
TMIN to TMAX
Power Supply Sensitivity of Gain
±4
±8
±4
±8
14
13
REFERENCE VOLTAGE
Voltage
TMIN to TMAX
Output Resistance
Source Current
Short Circuit to ACOM Duration
15
14
15
15
±0.1
±0.25
±0.1
±0.2
±0.003
±30
DYNAMIC PERFORMANCE
Settling Time
(to ±0.003%FSR, 5kW || 500pF Load)(4)
20V Output Step
1LSB Output Step(5)
Output Slew Rate
Total Harmonic Distortion
0dB, 1001Hz, fS = 100kHz
–20dB, 1001Hz, fS = 100kHz
–60dB, 1001Hz, fS = 100kHz
SINAD: 1001Hz, f S = 100kHz
Digital Feedthrough(5)
Digital-to-Analog Glitch Impulse(5)
Output Noise Voltage (includes reference)
ANALOG OUTPUT
Output Voltage Range
+VCC, –VCC = ±11.4V
Output Current
Output Impedance
Short Circuit to ACOM Duration
±2
±4
±2
±4
6
4
10
✻
✻
✻
✻
✻
✻
✻
✻
✻
10
✻
✻
✻
+10.025
+10.040
✻
✻
✻
✻
1
✻
✻
✻
✻
✻
2
V
mA
W
✻
✻
✻
✻
✻
Indefinite
✻
✻
16
✻
✻
µs
µs
V/µs
%
%
%
dB
nV–s
nV–s
nV/√Hz
✻
✻
✻
✻
0.1
Indefinite
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
+10
±5
+10.000
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
0.005
0.03
3.0
87
2
15
120
+9.975
+9.960
✻
✻
✻
✻
✻
✻
V
V
W
mA
INTERFACE
RESOLUTION
DIGITAL INPUTS
Serial Data Input Code
Logic Levels(1)
VIH
Bits
StraightBinary
VIL
+2.0
(VCC –1.4)
✻
✻
✻
✻
0
+0.8
✻
✻
✻
✻
V
V
IIH (VI = +2.7V)
±10
✻
✻
µA
IIL (VI = +0.4V)
±10
✻
✻
µA
✻
✻
V
V
✻
✻
✻
✻
V
V
✻
✻
✻
✻
✻
mA
mA
mW
+70
✻
°C
°C
°C/W
DIGITAL OUTPUT
Serial Data
VOL (ISINK = 1.6mA)
VOH (ISOURCE = 500µA),TMIN to TMAX
POWER SUPPLY REQUIREMENTS
Voltage
+VCC
–VCC
Current (No Load, ±15V Supplies)(6)
+VCC
–VCC
Power Dissipation(7)
TEMPERATURE RANGES
Specification
All Grades
Storage
Thermal Coefficient, θJA
+0.4
+5
✻
✻
+15
–15
+16.5
–16.5
✻
✻
13
22
16
26
625
0
+2.4
+11.4
–11.4
–40
–60
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
+85
+150
✻
✻
✻
75
0
✻
✻
✻ Specifications are the same as the grade to the left.
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for 0 to +10V output, FSR = 10V. (3) Errors externally
adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst-case Straight Binary code changes: 7FFF to 8000 and 8000 to 7FFF. (6) During power supply
turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents.
®
DAC716
2
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
SOIC/DIP
CLK
1
16 CLR
A0
2
15 –VCC
A1
3
14 Gain Adjust
SDI
4
SDO
5
13 Offset Adjust
12 VREF OUT
DCOM
6
11 NC
+VCC
7
10 NC
ACOM
8
9
DAC716
VOUT
ELECTROSTATIC
DISCHARGE SENSITIVITY
PIN
LABEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
A0
A1
SDI
SDO
DCOM
+VCC
ACOM
VOUT
NC
NC
VREF OUT
Offset Adjust
Gain Adjust
–VCC
CLR
DESCRIPTION
Serial Data Clock
Enable for Input Register (Active Low)
Enable for D/A Latch (Active Low)
Serial Data Input
Serial Data Output
Digital Supply Ground
Positive Power Supply
Analog Supply Ground
D/A Output
No Connection
No Connection
Voltage Reference Output
Offset Adjust
Gain Adjust
Negative Power Supply
Clear
ORDERING INFORMATION
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PRODUCT
PACKAGE
DAC716P
DAC716U
DAC716PB
DAC716UB
DAC716PK
DAC716UK
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
DIFFERENTIAL
LINEARITY ERROR
TMIN to TMAX
±8
±8
±4
±4
±2
±2
LSB
LSB
LSB
LSB
LSB
LSB
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
PACKAGE INFORMATION
ABSOLUTE MAXIMUM RATINGS(1)
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
DAC716P
DAC716U
Plastic DIP
Plastic SOIC
180
211
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet,
or Appendix C of Burr-Brown IC Data Book.
+VCC to Common .................................................................... 0V to +17V
–VCC to Common .................................................................... 0V to –17V
+VCC to –VCC ....................................................................................... 34V
ACOM to DCOM ............................................................................... ±0.5V
Digital Inputs to Common ............................................. –1V to (VCC –0.7V)
External Voltage Applied to BPO and Range Resistors ..................... ±VCC
VREF OUT ......................................................... Indefinite Short to Common
VOUT ............................................................... Indefinite Short to Common
SDO ............................................................... Indefinite Short to Common
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DAC716
TIMING SPECIFICATIONS
TRUTH TABLE
TA = –40°C to +85°C, +VCC = +15V, –VCC = –15V.
SYMBOL
PARAMETER
MIN
tCLK
tCL
tCH
tA0S
tA1S
tAOH
tA1H
tDS
tDH
tDSOP
tCP
Data Clock Period
Clock LOW
Clock HIGH
Setup Time for A0
Setup Time for A1
Hold Time for A0
Hold Time for A1
Setup Time for DATA
Hold Time for DATA
Output Propagation Delay
Clear Pulsewidth
100
50
50
50
50
10
10
50
10
140
200
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A0
A1
CLK
CLR
DESCRIPTION
0
1
1→0→1
1
Shift Serial Data into SDI
Load D/A Latch
1
0
1→0→1
1
1
1
1→0→1
1
No Change
0
0
1→0→1
1
Two Wire Operation(1)
X
X
1
1
No Change
X
X
X
0
Reset D/A Latch
NOTES: X = Don’t Care. (1) All digital input changes will appear at the
D/A output.
TIMING DIAGRAMS
Serial Data In
tCLK
tCH
tCL
CLK
tA
0H
tA
0S
A0
tDS
Serial Data Input
MSB First
tDH
D15
SDI
D14
D0
tA
tA
1S
Latch Data
In D/A Latch
1H
A1
tCP
CLR
Serial Data Out
tCLK
tCH
tCL
CLK
tA
0S
tA
A0
0H
tDS
Serial Data Out
SDO
D15
D14
tDSOP
tDSOP
®
DAC716
D0
4
TYPICAL PERFORMANCE CURVES
POWER SUPPLY REJECTION vs
POWER SUPPLY RIPPLE FREQUENCY
LOGIC vs V LEVEL
1k
2.0
–VCC
100
1.0
I Digital Input (µA)
[Change in FSR]/[Change in Supply Voltage]
(ppm of FSR/ %)
At TA = +25°C, VCC = ±15V, unless otherwise noted.
+VCC
10
CLR
0
SDI
–1.0
1
–2.0
–0.85
0.1
10
100
1k
10k
100k
A0, A1
1M
0
0.85 1.7 2.55
3.4 4.25
5.1 5.95
6.8
V Digital Input
Frequency (Hz)
FULL SCALE OUTPUT SWING
SETTLING TIME, +10V TO 0V
∆ Around 0 (µV)
VOUT (V)
10
FPO
2000
+5V
1500
0V
A1
2500
1000
500
0
–500
–1000
–1500
0
–2000
–2500
Time (10µs/div)
Time (1µs/div)
SETTLING TIME, 0V TO +10V
+5V
1500
–0V
A1
2000
1000
100
500
nV/√Hz
∆ Around +10V (µV)
VOUT SPECTRAL NOISE DENSITY
1000
2500
0
–500
10
–1000
–1500
–2000
1
–2500
1
Time (1µs/div)
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
®
5
DAC716
DISCUSSION OF
SPECIFICATIONS
DIGITAL FEEDTHROUGH
When the A/D is not selected, high frequency logic activity
on the digital inputs is coupled through the device and shows
up as output noise. This noise is digital feedthrough.
LINEARITY ERROR
Linearity error is defined as the deviation of the analog
output from a straight line drawn between the end points of
the transfer characteristic.
OPERATION
The DAC716 is a monolithic integrated-circuit 16-bit D/A
converter complete with 16-bit D/A switches and ladder
network, voltage reference, output amplifier and a serial
interface.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from
1LSB of an output change from one adjacent state to the
next. A DLE specification of ±1/2LSB means that the output
step size can range from 1/2LSB to 3/2LSB when the digital
input code changes from one code word to the adjacent code
word. If the DLE is more positive than –1LSB, the D/A is
said to be monotonic.
INTERFACE LOGIC
The DAC716 has double-buffered data latches. The input
data latch holds a 16-bit data word before loading it into the
second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters.
All digital control inputs are active low. Refer to block
diagram of Figure 1.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital input values.
Monotonicity of the K grade is guaranteed over the specification temperature range to 15 bits.
All latches are level-triggered. Data present when the enable
inputs are logic “0” will enter the latch. When the enable
inputs return to logic “1”, the data is latched.
The CLR input resets both the input latch and the D/A latch
to give an output voltage of 0V (code 0000).
SETTLING TIME
Settling time is the total time (including slew time) for the
D/A output to settle to within an error band around its final
value after a change in input. Settling times are specified to
within ±0.003% of Full Scale Range (FSR) for an output
step change of 10V and 1LSB. The 1LSB change is measured at the Major Carry (7FFF to 8000, and 8000 to 7FFF:
Straight Binary codes), the input transition at which worstcase settling time occurs.
LOGIC INPUT COMPATIBILITY
DAC716 digital inputs are TTL compatible (1.4V switching
level) with low leakage, high impedance inputs. Thus the
inputs are suitable for being driven by any type of 5V logic
such as 5V CMOS logic. An equivalent circuit of a digital
input is shown in Figure 2.
Data inputs will float to logic “0” and control inputs will
float to logic “0” if left unconnected. It is recommended that
any unused inputs be connected to DCOM to improve noise
immunity.
TOTAL HARMONIC DISTORTION + NOISE
Total harmonic distortion + noise is defined as the ratio of
the square root of the sum of the squares of the values of the
harmonics and noise to the value of the fundamental frequency. It is expressed in % of the fundamental frequency
amplitude at sampling rate fS.
Digital inputs remain high impedance when power is off.
INPUT CODING
The DAC716 is designed to accept Straight Binary (SB)
input codes. The serial input format is MSB first.
SIGNAL-TO-NOISE
AND DISTORTION RATIO (SINAD)
INTERNAL REFERENCE
DAC716 contains a +10V reference.
SINAD includes all the harmonic and outstanding spurious
components in the definition of output noise power in
addition to quantizing and internal random noise power.
SINAD is expressed in dB at a specified input frequency and
sampling rate, fS.
The reference output may be used to drive external loads,
sourcing up to 2mA. The load current should be constant,
otherwise the gain and unipolar offset of the converter will
vary.
DIGITAL-TO-ANALOG GLITCH IMPULSE
The amount of charge injected into the analog output from
the digital inputs when the inputs change state. It is measured at half scale at the input codes where as many as
possible switches change state—from 8000 to 7FFF.
OUTPUT VOLTAGE SWING
The output amplifier of DAC716 is designed to achieve a
+10V output range. DAC716 will provide a +10V output
swing while operating on ±11.4V or higher voltage supplies.
®
DAC716
6
Gain Adjust
VREF OUT
+VCC
– VCC
14
12
7
15
180Ω
15kΩ
+10V
Reference
10
NC
11
NC
13
Offset
Adjust
9
VOUT
9.75kΩ
+2.5V
5kΩ
–VCC
D/A Switches
CLK
1
A1
3
CLR
16
A0
2
SDI
4
SDO
5
DAC Latch
16
Shift Register
8
6
ACOM
DCOM
FIGURE 1. DAC716 Block Diagram.
+VCC
ESD Protection Circuit
Range of
Gain Adjust
≈ ±0.3%
+ Full Scale
R = 1kΩ: A0, A1, CLK, CLR, SDI
1LSB
R
6.8V
Full Scale
Range
Analog Output
Digital
Input
5pF
–VCC
Gain Adjust
Rotates the Line
FIGURE 2. Equivalent Circuit of Digital Inputs.
Range of
Offset Adjust
GAIN AND OFFSET ADJUSTMENTS
Figure 3 illustrates the relationship of offset and gain adjustments for a unipolar connected D/A converter. Offset should
be adjusted first to avoid interaction of adjustments. See
Table I for calibration values and codes. These adjustments
have a minimum range of ±0.3%.
Offset Adj.
Translates
the Line
≈ ±0.3%
0000H
Zero
8000H
FFFFH
Digital Input
FIGURE 3. Relationship of Offset and Gain Adjustments.
Offset Adjustment
Apply the digital input code, 0000, that produces 0V and adjust
the offset potentiometer or the offset adjust D/A converter for
0V.
Gain Adjustment
Apply the digital input that gives the maximum positive
voltage output. Adjust the gain potentiometer or the gain
adjust D/A converter for this positive full scale voltage.
®
7
DAC716
DAC716 CALIBRATION VALUES
1 LEAST SIGNIFICANT BIT = 152µV
1
16
2
–VCC 15
3
14
–12V to –15V
DIGITAL INPUT CODE
ANALOG OUTPUT (V)
STRAIGHT BINARY
UNIPOLAR 10V RANGE
DESCRIPTION
FFFFH
|
8000H
+9.999695
+ Full Scale –1LSB
4
+5.000000
13
DAC716
Half Scale
5
0000H
0.000000
12
+
1µF
Unipolar Zero
6
DCOM
11
7
+VCC
10
8
ACOM
9
+12V to +15V
TABLE I. Digital Input and Analog Output Voltage Calibration Values.
1µF
+
INSTALLATION
GENERAL CONSIDERATIONS
Due to the high precision of these D/A converters, system
design problems such as grounding and contact resistance
become very important. A 16-bit converter with a 10V fullscale range has a 1LSB value of 152µV. With a load current
of 5mA, series wiring and connector resistance of only
60mΩ will cause a voltage drop of 300µV. To understand
what this means in terms of a system layout, the resistivity
of a typical 1 ounce copper-clad printed circuit board is 1/2
mΩ per square. For a 5mA load, a 0.1 inch wide printed
circuit conductor 0.6 inches long will result in a voltage drop
of 150µV.
FIGURE 4. Power Supply Connections.
The analog output of DAC716 has an LSB size of 152µV
(–96dB). The rms noise floor of the D/A should remain below
this level in the frequency range of interest. The DAC716’s
output noise spectral density (which includes the noise contributed by the internal reference) is shown in the Typical Performance Curves section.
If several DAC716s are used or if the DAC716 shares
supplies with other components, connecting the ACOM and
DCOM lines together at the power supplies only rather than
at each chip, may give better results.
pins are located adjacent to each other to help isolate analog
from digital signals. Analog signals should be routed as far
as possible from digital signals and should cross them at
right angles. A solid analog ground plane around the D/A
package, as well as under it in the vicinity of the analog and
power supply pins, will isolate the D/A from switching
currents. It is recommended that DCOM and ACOM be
connected directly to the ground planes under the package.
LOAD CONNECTIONS
Since the reference point for VOUT and VREF OUT is the
ACOM pin, it is important to connect the D/A converter load
directly to the ACOM pin. Refer to Figure 5.
Wiring to high-resolution D/A converters should be routed
to provide optimum isolation from sources of RFI and EMI.
The key to elimination of RF radiation or pickup is small
loop area. Signal leads and their return conductors should be
kept close together such that they present a small capture
cross-section for any external field. Wire-wrap construction
is not recommended.
Lead and contact resistances are represented by R1 through
R3. As long as the load resistance RL is constant, R1 simply
introduces a gain error and can be removed by gain adjustment of the D/A or system-wide gain calibration. R2 is part
of RL if the output voltage is sensed at ACOM.
POWER SUPPLY AND
REFERENCE CONNECTIONS
Power supply decoupling capacitors should be added as
shown in Figure 4. Best performance occurs using a 1 to
10µF tantalum capacitor at –VCC. Applications with less
critical settling time may be able to use 0.01µF at –VCC
as well as at +V CC. The capacitors should be located
close to the package.
The DAC716 has separate ANALOG COMMON and DIGITAL COMMON pins. The current through DCOM is mostly
switching transients and are up to 1mA peak in amplitude.
The current through ACOM is typically 5µA for all codes.
In some applications it is impractical to return the load to the
ACOM pin of the D/A converter. Sensing the output voltage
at the SYSTEM GROUND point is reasonable, because there
is no change in DAC716 ACOM current, provided that R3 is
a low-resistance ground plane or conductor. In this case you
may wish to connect DCOM to SYSTEM GROUND as well.
GAIN AND OFFSET ADJUST
Connections Using Potentiometers
GAIN and OFFSET adjust pins provide for trim using
external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at
least ±0.3% of Full Scale Range. Refer to Figure 6.
Use separate analog and digital ground planes with a single
interconnection point to minimize ground loops. The analog
®
DAC716
8
DIGITAL INTERFACE
Using D/A Converters
The GAIN ADJUST and OFFSET ADJUST circuits of
DAC716 have been arranged so that these points may be
easily driven by external D/A converters. Refer to
Figure 7. 12-bit D/A converters provide a nominal
OFFSET adjust and GAIN adjust resolution of 25µV and
15µV per LSB step, respectively.
SERIAL INTERFACE
The DAC716 has a serial interface with two data buffers
which can be used for either synchronous or asynchronous
updating of multiple D/A converters. A0 is the enable control
for the Data Input Latch. A1 is the enable for the D/A Latch.
CLK is used to strobe data into the latches enabled by A0 and
A1. A CLR function is also provided and when enabled it sets
both the Data Latch and the D/A Latch to all zeros .
Nominal values of GAIN and OFFSET occur when the D/A
converters outputs are at approximately half scale, 0V.
Multiple DAC716s can be connected to the same CLK and
data lines in two ways. The output of the serial loaded data
latch is available as SDO so that any number of DAC716s
can be cascaded on the same input bit stream as shown in
Figure 8 and 9. This configuration allows all D/A converters
to be updated simultaneously and requires a minimum number of control signal inputs. These configurations do require
16N CLK cycles to load any given D/A converter, where N
is the number of D/A converters.
OUTPUT VOLTAGE RANGE CONNECTIONS
The DAC716 output amplifier is connected internally for
10V output range.
The DAC716 can also be connected in parallel as shown in
Figure 10. This configuration allows any D/A converter in
the system to be updated in a maximum of 16 CLK cycles.
VREF OUT Offset Adjust
DAC716
SDI
A0
A1
VREF
9.75kΩ
5kΩ
CLR
VOUT R1
Bus
Interface
RL
DCOM
Sense
Output
ACOM
R2
R3
Alternate Ground
Sense Connection
To +VCC
0.01µF(1)
0.01µF
System Ground
Analog
Power
Supply
To –VCC
NOTE: (1) Locate close to DAC716 package.
FIGURE 5. System Ground Considerations for High-Resolution D/A Converters.
®
9
DAC716
Internal
+10V Reference
VREF OUT
12
P1
1kΩ
180Ω
R1
100Ω
Gain Adjust
Offset Adjust
15kΩ
14
R2
1MΩ
13
R3
27kΩ
9.75kΩ
+VCC
P2
10kΩ to 100kΩ
–VCC
5kΩ
9
IDAC
0-2mA
8
10V VOUT
For no external adjustments, pins 13 and 14 are not connected.
External resistors R1 - R3 are standard ±1% values. Range of
adjustment at least ±0.3% FSR.
ACOM
FIGURE 6. Manual Offset and Gain Adjust Circuits.
Internal
+10V Reference
VREF OUT
12
R1
392Ω
180Ω
Gain Adjust
14
Offset Adjust
13
15kΩ
9.75kΩ
R2
33kΩ
5kΩ
IDAC
0-2mA
–10 to +10V
9
+10V VOUT
DAC716
For no external adjustments, pins 13 and 14 are not connected.
External resistors R1 - R3 tolerance: ±1%. Range of adjustment at
least ±0.3% FSR.
FIGURE 7. Gain and Offset Adjustment Using D/A Converters.
®
DAC716
10
R3
1MΩ
–10 to +10V
DAC
±10V
DAC
±10V
4
Data
2
Data Latch
3
Up Date
1
CLK
+5V 16
4
2
3
1
+5V 16
4
2
3
1
+5V 16
SDI
A0
DAC716
A1
DAC 1
CLK
CLR
SDO
5
SDI
A0
DAC716
A1
DAC 2
CLK
CLR
SDO
5
SDI
A0
DAC716
A1
DAC 3
CLK
CLR
SDO
5
To other DACs
FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update.
DAC 3
DAC 2
DAC 1
Clock
Data
F E D C B A 9 8 7 6 5 4
3 2 1 0 F E D C B A 9 8 7 6 5 4 3
2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0
Data Latch
Update
FIGURE 8b. Timing Diagram For Figure 8a.
®
11
DAC716
4
Data
2
Data Latch
3
Up Date
1
16
SDI
A0
DAC716
A1
DAC 1
CLK
CLR
SDO
5
+5V
4
2
3
1
16
SDI
A0
DAC716
A1
DAC 2
CLK
CLR
SDO
5
+5V
4
2
3
1
16
SDI
A0
DAC716
A1
DAC 3
CLK
CLR
SDO
5
To other DACs
+5V
FIGURE 9a. Cascaded Serial Bus Connection with Asynchronous Update.
DAC 3
DAC 2
DAC 1
Data Latch
Data
F E D C B A 9 8 7 6 5 4
3 2 1 0 F E D C B A 9 8 7 6 5 4 3
Update
FIGURE 9b. Timing Diagram For Figure 9a.
®
DAC716
12
2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0
Data
Data Latch 1
Up Date
4
SDI
2
A0
DAC716
3
A1
DAC 1
1
CLK
CLK
16
CLR
4
Data Latch 2
SDO
5
SDI
2
A0
DAC716
3
A1
DAC 2
1
CLK
16
4
Data Latch 3
CLR
CLR
SDO
5
SDI
2
A0
DAC716
3
A1
DAC 3
1
CLK
16
CLR
SDO
5
FIGURE 10a. Parallel Bus Connection.
DAC 1
DAC 2
DAC 3
Clock
Data
F E D C B A 9 8 7 6 5 4
3 2 1 0 F E D C B A 9 8 7 6 5 4 3
2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0
Data Latch 1
Data Latch 2
Data Latch 3
Update
FIGURE 10b. Timing Diagram For Figure 10a.
®
13
DAC716