DAC7731
DAC
773
1
SBAS249 – DECEMBER 2001
16-Bit, Voltage Output, Serial Input
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 150mW MAXIMUM
● +10V INTERNAL REFERENCE
● UNIPOLAR OR BIPOLAR OPERATION
● SETTLING TIME: 5µs to ±0.003% FSR
● 16-BIT MONOTINICITY, –40°C TO +85°C
● ±10V, ±5V, OR +10V CONFIGURABLE VOLTAGE
OUTPUT
● RESET TO ZERO OR MID-SCALE
● DOUBLE-BUFFERED DATA INPUT
● DAISY-CHAIN FEATURE FOR MULTIPLE
DAC7731s ON A SINGLE BUS
● SMALL SSOP-24 PACKAGE
The DAC7731 is a 16-bit Digital-to-Analog Converter (DAC)
which provides 16 bits of monotonic performance over the
specified operating temperature range and offers a +10V
internal reference. Designed for automatic test equipment
and industrial process control applications, the DAC7731’s
output swing can be configured in a ±10V, ±5V, or +10V
range. The flexibility of the output configuration allows the
DAC7731 to provide both unipolar and bipolar operation by
pin strapping. The DAC7731 includes a high-speed output
amplifier with a maximum settling time of 5µs to ±0.003%
FSR for a 20V full-scale change and only consumes 100mW
(typical) of power.
APPLICATIONS
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
VDD VSS VCC
REFADJ
The DAC7731 features a standard 3-wire, SPI-compatible
serial interface with double buffering to allow asynchronous
updates of the analog output as well as a serial data output
line for daisy-chaining multiple DAC7731’s. A user programmable reset control forces the DAC output to either min-scale
(0000H) or mid-scale (8000H), overriding both the input and
DAC register values. The DAC7731 is available in a
SSOP-24 package and three performance grades specified
to operate from –40°C to +85°C.
REFOUT REFIN
VREF
ROFFSET
Buffer
REFEN
RFB2
+10V
Reference
RSTSEL
RST
Control
Logic
LDAC
RFB1
SCLK
CS
SJ
SDO
Enable
SDI
AGND
Input
Register
DAC
Register
DAC
VOUT
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ........................................................................... –0.3V to +32V
VCC to AGND ...................................................................... –0.3V to +16V
VSS to AGND ...................................................................... –16V to +0.3V
AGND to DGND ................................................................... –0.3V to 0.3V
REFIN to AGND .............................................................. 0V to VCC – 1.4V
VDD to DGND ........................................................................ –0.3V to +6V
Digital Input Voltage to DGND ................................. –0.3V to VDD + 0.3V
Digital Output Voltage to DGND .............................. –0.3V to VDD + 0.3V
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Junction Temperature (TJ Max) .................................................... +150°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
DAC7731E
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA, QUANTITY
DAC7731E
DAC7731E/1K
Rails, 60
Tape and Reel,1000
DAC7731EB
DAC7731EB/1K
Rails, 60
Tape and Reel, 1000
DAC7731EC
DAC7731EC/1K
Rails, 60
Tape and Reel, 1000
SSOP-24
DB
–40°C to +85°C
DAC7731E
"
"
"
"
"
DAC7731EB
SSOP-24
DB
–40°C to +85°C
DAC7731EB
"
"
"
"
"
DAC7731EC
SSOP-24
DB
–40°C to +85°C
DAC7731EC
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Models with a slash (/) are available only in Tape and
Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7731EC/1K” will get a single 1000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal refi⁄ence enabled, unless otherwise noted.
DAC7731E
PARAMETER
CONDITIONS
MIN
TYP
ACCURACY
Linearity Error (INL)
Gain Error Drift
PSRR (VCC or VSS)
ANALOG OUTPUT(1)
Voltage Output(2)
Output Current
Output Impeadance
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
14
MIN
TYP
+11.4/–4.75
+11.4/–11.4
+11.4/–6.4
0 to 10
±10
±5
±0.4
±0.25
±10
✻
200
±25
4.75
VCC – 1.4
✻
✻
±0.25
±0.1
0
10
✻
+2
✻
±7
✻
✻
V
V
V
mA
Ω
pF
mA
✻
✻
✻
±10
✻
1
✻
✻
✻
✻
✻
✻
✻
✻
10.025
✻
✻
✻
✻
✻
✻
±7
✻
✻
✻
✻
✻
✻
✻
✻
50
–2
LSB
LSB
LSB
Bits
% of FSR
ppm/°C
% of FSR
% of FSR
ppm/°C
ppm/V
±0.15
✻
✻
10
±3
±2
±1
✻
✻
✻
✻
✻
9.975
UNITS
✻
✻
✻
✻
10.04
MAX
16
✻
10
400
±15
TYP
✻
0.1
200
±15
Indefinite
9.96
MIN
✻
±15
50
AGND
MAX
15
With Internal REF
With External REF
With Internal REF
At Full-Scale
±5
DAC7731EC
±4
±3
±2
±0.1
±2
REFERENCE
Reference Output
REFOUT Impedance
REFOUT Voltage Drift
REFOUT Voltage Adjustment(3)
REFIN Input Range(4)
REFIN Input Current
REFADJ Input Range
Absolute Max Value that
can be applied is VCC
REFADJ Input Impedance
VREF Output Current
VREF Impedance
2
MAX
±6
±5
±4
TA = 25°C
Differential Linearity Error (DNL)
Monotonicity
Offset Error
Offset Error Drift
Gain Error
DAC7731EB
✻
✻
✻
✻
V
Ω
ppm/°C
mV
V
nA
V
kΩ
mA
Ω
DAC7731
www.ti.com
SBAS249
ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted.
DAC7731E
PARAMETER
CONDITIONS
DYNAMIC PERFORMANCE
Settling Time to ±0.003%
MIN
20V Output Step
RL = 5kΩ, CL = 200pF,
with external REFOUT
to REFIN filter(5)
Digital Feedthrough
Output Noise Voltage
DIGITAL OUTPUT
VOH
VOL
POWER SUPPLY
VDD
VCC
VSS
|IH| < 10µA
|IL| < 10µA
0.7 • VDD
IOH = –0.8mA
IOL = 1.6mA
3.6
5
+4.75
+11.4
–15.75
–15.75
–4
DAC7731EC
TYP
MAX
✻
✻
MIN
✻
✻
100
4
–2.5
85
100
–40
MAX
UNITS
✻
✻
µs
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
6
✻
150
✻
+85
✻
V
V
✻
V
V
✻
✻
+5.25
+15.75
–11.4
–4.75
nV-s
nV/√Hz
✻
✻
✻
+5.0
TYP
✻
✻
✻
0.4
Unloaded
Unloaded
No Load, Ext. Reference
No Load, Int. Reference
TEMPERATURE RANGE
Specified Performance
3
MIN
0.3 • VDD
Bipolar Operation
Unipolar Opeation
IDD
ICC
ISS
Power
MAX
2
100
at 10kHz
DIGITAL INPUT
VIH
VIL
DAC7731EB
TYP
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
µA
mA
mA
mW
mW
✻
°C
✻
✻ Specifications same as grade to the left.
NOTES: (1) With minimum VCC/VSS requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output voltage
configurations. (3) See Figure 11 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REF IN must be equal to the greater
of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100kΩ, 1.0µF (see Figure 14).
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
SSOP
VCC
1
24 VSS
REFOUT
2
23 REFEN
REFIN
3
22 RSTSEL
REFADJ
4
21 SCLK
VREF
5
20 CS
ROFFSET
6
19 SDO
DAC7731
PIN
NAME
1
2
3
4
VCC
REFOUT
REFIN
REFADJ
5
VREF
6
7
8
ROFFSET
AGND
RFB2
9
RFB1
10
11
12
13
14
15
16
SJ
VOUT
VDD
DGND
TEST
NC
RST
AGND
7
18 SDI
RFB2
8
17 LDAC
RFB1
9
16 RST
SJ
10
15 NC
17
LDAC
VOUT
11
14 TEST
18
SDI
VDD
12
13 DGND
19
20
21
22
SDO
CS
SCLK
RSTSEL
23
REFEN
24
VSS
NOTE: (1) RST, LDAC, SDI, CS and SCK are Schmitt-triggered inputs.
DAC7731
SBAS249
www.ti.com
DESCRIPTION
Positive Analog Power Supply
Internal Reference Output
Reference Input
Internal Reference Trim. (Acts as a gain adjustment
input when the internal reference is used.)
Buffered Output from REFIN, can be used to drive
external devices. Internally, this pin directly drives the
DAC's circuitry.
Offsetting Resistor
Analog ground
Feedback Resistor 2, used to configure DAC output
range.
Feedback Resistor 1, used to configure DAC output
range.
Summing Junction of the Output Amplifier
DAC Voltage Output
Digital Power Supply
Digital Ground
Reserved, Connect to DGND
No Connection
VOUT reset; active LOW, depending on the state of
RSTSEL, the DAC register is either reset to midscale or min-scale.
DAC register load control, rising dege triggered. Data
is loaded from the input register to the DAC register.
Serial Data Input. Data is latched into the input
register on the rising edge of SCLK.
Serial Data Output, delayed 16 SCLK clock cycles.
Chip Select, Active LOW
Serial Clock Input
Reset Select; determines the action of RST. If HIGH,
RST will reset the DAC register to mid-scale. If LOW,
RST will reset the DAC register to min-scale.
Enables internal +10V reference (REFOUT), active
LOW.
Negative Analog Power Supply
3
TIMING CHARACTERISTICS
VCC = +15V, VSS = –15V, VDD = 5V; RL = 2kΩ to AGND; CL = 200pF to AGND; all specifications –40°C to +85°C, unless otherwise noted.
DAC7731
PARAMETER
tWH
tWL
tSDI
tHDI
tSCS
tHSC
tDDO
tHDO
tDDOZ
tWCSH
tWLDL
tWLDH
tSLD
tDLD
tSCLK
tSRS
tHRS
tWRL
tS
DESCRIPTION
MIN
SCLK HIGH Time
SCLK LOW Time
Setup Time: Data in valid before rising SCLK
Hold Time: Data in valid after rising SCLK
Setup Time: CS falling edge before first rising SCLK
Hold Time: CS rising edge after 16th rising SCLK
Delay Time: CS Falling Edge to Data Out valid, CL = 20pF on SDO
Hold Time: Data Out valid after SCLK rising edge, CL 20pF on SDO
Delay Time: CS rising edge to SDO = High Impedance
CS HIGH Time
LDAC LOW Time
LDAC HIGH Time
Setup Time: 16th Rising SCLK Before LDAC Rising Edge
Delay Time: LDAC rising edge to first SCLK rising edge of next
transfer cycle.
Setup Time: CS High before falling SCLK edge following 16th
rising SCLK edge
Setup Time: RSTSEL Valid Before RST LOW
Hold Time: RSTSEL valid after RST HIGH
RST LOW Time
DAC VOUT Settling Time
TYP
MAX
25
25
5
20
15
0
50
50
UNITS
50
20
20
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
0
20
30
ns
ns
ns
µs
70
5
INTERFACE TIMING
tSCS
tHCS
tWCSH
CS
tWH
1
SCLK
16
tWL
tHDI
tSDI
B15
SDI
2
B14
tDDO
B13
tSCLK
B0
Word B
tHDO
SDO
C15
A15
A14
C13
C12
B13
B12
Word C
tDDOZ
A13
C14
A0
B15
B14
tDLD
Word B
tWLDL
Word A
tWLDH
LDAC
tSLD
tS
VOUT
±0.003% of FSR
Error Bands
RESET TIMING
tSRS
RSTSEL
tHRS
tWRL
RST
tS
+FS
VOUT
(RSTSEL = LOW)
Min-Scale
–FS
+FS
VOUT
(RSTSEL = HIGH)
Mid-Scale
–FS
4
DAC7731
www.ti.com
SBAS249
TYPICAL CHARACTERISTICS
INL (LSB)
6
4
2
0
–2
–4
–6
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
Bipolar Configuration: VOUT = –10V to +10V
TA = 85°C, Internal Reference Enabled
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
6
4
2
0
–2
–4
–6
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
Bipolar Configuration: VOUT = –10V to +10V
TA = 25°C, Internal Reference Enabled
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DNL (LSB)
DNL (LSB)
INL (LSB)
TA = +25°C (unless otherwise noted).
DNL (LSB)
6
4
2
0
–2
–4
–6
Digital Input Code
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
1.00
Bipolar Configuration: VOUT = –10V to +10V
TA = –40°C, Internal Reference Enabled
0.25
–0.25
–0.50
–0.75
–1.00
–40
4.4
–0.010
4.3
Ext. Ref, Unipolar Mode: VOUT = 0 to +10V
–0.020
–15
10
35
60
85
Temperature (°C)
GAIN ERROR vs TEMPERATURE
0.000
VOUT = 0 to +10V
0.00
Digital Input Code
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE
Bipolar Configuration: VOUT = –10V to +10V
Internal Reference Enabled, TA = 25°C
4.2
–0.030
Ext. Ref, Bipolar Mode: VOUT = –10 to +10V
–0.040
ICC (mA)
Error (%)
VOUT = –10 to +10V
0.50
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
–0.050
OFFSET ERROR vs TEMPERATURE
0.75
Error (mV)
INL (LSB)
Digital Input Code
Int. Ref, Unipolar Mode: VOUT = 0 to +10V
–0.060
–0.070
4.1
4.0
3.9
–0.080
–0.090
Int. Ref, Bipolar Mode: VOUT = –10 to +10V
3.8
Load = 200pF, 2kΩ
–0.100
–40
–15
10
35
60
3.7
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
85
Temperature (°C)
Digital Input Code
DAC7731
SBAS249
www.ti.com
5
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE
3.4
3.3
VSS SUPPLY CURRENT vs DIGITAL INPUT CODE
–1.50
Bipolar Configuration: VOUT = –10V to +10V
External Reference, REFEN = 5V, TA = 25°C
–1.75
3.1
ISS (mA)
ICC (mA)
3.2
3.0
–2.00
–2.25
2.9
–2.50
Bipolar Configuration: VOUT = –10V to +10V
TA = 25°C
2.8
–2.75
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
2.7
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
SUPPLY CURRENT vs TEMPERATURE
7
6
5
TA = 25°C, Transition
Shown for a Single
Input (Applies to CS,
SCLK,DIN and LDAC
inputs)
1600
1400
4
1200
3
IDD (µA)
ICC, ISS (mA)
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
1800
Load Current Excluded
VCC = +15V, VSS = –15V
Bipolar VOUT Configuration: –10V to +10V
ICC
2
1
1000
800
600
0
400
–1
ISS
200
–2
0
–3
–40
–15
10
35
60
0.0
85
0.5
1.0
1.5
90
HISTOGRAM OF VCC CURRENT CONSUMPTION
Bipolar Output Configuration
Internal Reference Enabled
Code = 5555H
90
80
70
70
60
60
50
40
20
20
10
10
0
0
4.000
4.500
5.000
4.5
5.0
Bipolar Output Configuration
Internal Reference Enabled
Code = 5555H
–3.50
–3.00
–2.50
–2.00
–1.50
ISS (mA)
ICC (mA)
6
4.0
40
30
3.500
3.5
50
30
3.000
3.0
HISTOGRAM OF VSS CURRENT CONSUMPTION
100
Frequency
Frequency
80
2.5
VLOGIC (V)
Temperature (°C)
100
2.0
DAC7731
www.ti.com
SBAS249
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at VOUT)
10
–20
–10
–20
–30
–40
VSS
–50
VCC
–60
Bipolar Configuration: ±10V VOUT, Code FFFFH
–VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p
0
PSRR (dB)
–10
PSRR (dB)
10
Bipolar Configuration: ±10V VOUT
Code 8000H
–VSS, VCC = 15V + 1Vp-p
VDD = 5V + 0.5Vp-p
0
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at VOUT)
VSS
–30
VCC
–40
–50
VDD
–60
–70
–70
–80
0.1K
VDD
1K
10K
100K
1M
–80
0.01K
10M
0.1K
1K
Frequency (Hz)
10.015
15V
10.010
0V
10.005
REFOUT (V)
REFOUT (2V/div)
VCC (5V/div)
INTERNAL REFERENCE START-UP
10V
10K
100K
Frequency (Hz)
1M
10M
INTERNAL REFERENCE OUTPUT vs TEMPERATURE
10.000
9.995
9.990
0V
9.985
–40
Time (2ms/div)
–15
10
35
60
85
Temperature (°C)
REFOUT VOLTAGE vs LOAD
11.0
Source
Loaded to VCC
VCC = +15V
8
10.5
4
VOUT (V)
REFOUT (V)
OUTPUT VOLTAGE vs RLOAD
12
10.0
9.5
0
–4
Sink
9.0
–8
Loaded to AGND
8.5
–12
1
10
100
0.0
1K
DAC7731
SBAS249
0.1
1.0
10.0
100.0
RLOAD (kΩ)
REFOUT LOAD(kΩ)
www.ti.com
7
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at REFOUT)
10
–20
VCC
–30
–40
VDD
VSS
–50
–60
700
600
Code FFFFH
500
400
300
200
–70
Code 0000H
100
–80
1
800
OUTPUT NOISE vs FREQUENCY
Unipolar Configuration, Internal Reference Enabled
800
Output Noise (nV/Hz)
0
–10
PSRR (dB)
900
Internal Reference Enabled
–VSS, VCC = 15V + 1Vp-p,
VDD = 5V + 0.5Vp-p
10
100
1K
10K
Frequency (Hz)
100K
1M
10M
0
0.01K
0.1K
1K
10K
100K
Frequency (Hz)
1M
10M
BROADBAND NOISE
OUTPUT NOISE vs FREQUENCY
Bipolar Configuration: ±10V, Internal Reference Enabled
600
VOUT (V, 50µV/div)
Output Noise (nV/rtHz)
700
500
400
Code 0000H
300
Code FFFFH
200
100
0
0.01K
Code 8000H
0.1K
1K
10K
100K
Frequency (Hz)
1M
10M
Time (100µs/div)
BIPOLAR FULL-SCALE SETTLING TIME
UNIPOLAR FULL-SCALE SETTLING TIME
Large-Signal Output (5V/div)
Large-Signal Output (5V/div)
Small-Signal Error (150µV/div)
Small-Signal Error (300µV/div)
Unipolar Configuration: VOUT = 0 to +10V
Zero-Scale to +Full-Scale Change
5kΩ, 200pF Load
Bipolar Configuration: VOUT = –10 to +10V
–Full-Scale to +Full-Scale
5kΩ, 200pF Load
Time (2µs/div)
Time (2µs/div)
8
Internal Reference Enabled
Filtered with 1.6Hz Low-Pass
Code FFFFH, Bipolar ±10V Configuration
10kHz Measurement BW
DAC7731
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SBAS249
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
BIPOLAR FULL-SCALE SETTLING TIME
UNIPOLAR FULL-SCALE SETTLING TIME
Small-Signal Error (150µV/div)
Small-Signal Error (300µV/div)
Large-Signal Output (5V/div)
Large-Signal Output (5V/div)
Unipolar Configuration: VOUT = 0V to +10V
+Full-Scale to Zero-Scale Change
5kΩ, 200pF Load
Bipolar Configuration: VOUT = –10 to +10V
+Full-Scale to –Full-Scale
5kΩ, 200pF Load
Time (2µs/div)
Time (2µs/div)
MID-SCALE GLITCH
MID-SCALE GLITCH
Code 8000H to 7FFFH
Bipolar Configuration: ±10V VOUT
VOUT (V, 100mV/div)
VOUT (V, 100mV/div)
Code 7FFFH to 8000H
Bipolar Configuration: ±10V VOUT
Time (1µs/div)
Time (1µs/div)
DAC7731
SBAS249
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9
THEORY OF OPERATION
The DAC7731 is a voltage output, 16-bit DAC with a +10V
built-in internal reference. The architecture is an R-2R ladder
configuration with the three MSB’s segmented, followed by
an operational amplifier that serves as a buffer, as shown in
Figure 1. The output buffer is designed to allow userconfigurable output adjustments giving the DAC7731 output
voltage ranges of 0V to +10V, –5V to +5V, or –10V to +10V.
Please refer to Figures 2, 3, and 4 for pin configuration
information.
REFADJ
The digital input is a serial word made up of the DAC code
(MSB first) and is loaded into the DAC register using the
LDAC input pin. The converter can be powered from ±12V
to ±15V dual analog supplies and a +5V logic supply. The
device offers a reset function, which immediately sets the
DAC output voltage and DAC register to min-scale (code
0000H) or mid-scale (code 8000H). The data I/O and reset
functions are discussed in more detail in the following sections.
REFIN
REFOUT
ROFFSET
VREF
RFB2
R/4
Buffer
RFB1
+10V Internal
Reference
R/2
R/2
R/4
SJ
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
R/4
VREF
AGND
FIGURE 1. DAC7731 Architecture.
VCC
VCC
DAC7731
DAC7731
0.1µF
VSS
1µF
1
VCC
2
REFOUT
3
REFIN
4
REFADJ
5
VREF
VDD
0.1µF
24
2
REFOUT
22
3
REFIN
SCLK
21
4
REFADJ
CS
20
5
VREF
6
ROFFSET
1µF
0.1µF
Control/Data
Bus
VSS
24
REFEN
23
RSTSEL
22
SCLK
21
CS
20
SDO
19
SDO
19
SDI
18
7
AGND
SDI
18
LDAC
17
8
RFB2
LDAC
17
16
9
RFB1
RST
16
15
10 SJ
NC
15
11 VOUT
TEST
14
12 VDD
DGND
13
AGND
8
RFB2
9
RFB1
RST
NC
TEST
DGND
(–5V to +5V)
14
VDD
13
1µF
FIGURE 2. Basic Operation: VOUT = 0V to +10V.
10
VCC
23
7
12 VDD
1
REFEN
ROFFSET
11 VOUT
VSS
1µF
RSTSEL
6
10 SJ
(0V to +10V)
VSS
0.1µF
0.1µF
1µF
0.1µF
Control/Data
Bus
1µF
FIGURE 3. Basic Operation: VOUT = –5V to +5V.
DAC7731
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VCC
REFSEL
ACTION
1
Internal Reference disabled;
REFOUT = High Impedance
0
Internal Reference enabled;
REFOUT = +10V
DAC7731
0.1µF
VSS
1µF
1
VCC
2
REFOUT
3
REFIN
4
REFADJ
5
VREF
6
ROFFSET
7
AGND
8
9
VSS
24
REFEN
23
RSTSEL
22
SCLK
21
CS
20
SDO
19
SDI
18
RFB2
LDAC
17
RFB1
RST
16
NC
15
(–10V to +10V)
11 VOUT
TEST
14
VDD
12 VDD
DGND
13
10 SJ
0.1µF
1µF
0.1µF
TABLE I. REFEN Action.
DIGITAL INTERFACE
Control/Data
Bus
Table II shows the input data format for the DAC7731 and
Table III illustrates the basic control logic of the device. The
serial interface consists of a chip select input (CS), serial data
clock input (SCLK), serial data input (SDI), serial data output
(SDO), and load control input (LDAC). An asynchronous reset
input (RST), which is active LOW, is provided to simplify startup conditions, periodic resets, or emergency resets to a known
state, depending on the status of the reset select (RSTSEL)
signal. Please refer to the "DAC Reset" section for additional
information regarding the reset operation.
1µF
ANALOG OUTPUT
FIGURE 4. Basic Operation: VOUT = –10V to +10V.
DIGITAL INPUT
Unipolar Configuration
Bipolar Configuration
Unipolar Straight Binary
Bipolar Offset Binary
0x0000
Zero (0V)
–Full-Scale (–VREF or –VREF/2)
The output amplifier can swing to within 1.4V of the supply
rails, specified over the –40°C to +85°C temperature range.
This allows for a ±10V DAC voltage output operation from
±12V supplies with a typical 5% tolerance.
0x0001
Zero + 1LSB
–Full-Scale + 1LSB
:
:
:
0x8000
1/2 Full-Scale
Bipolar Zero
0x8001
1/2 Full-Scale + 1LSB
Bipolar Zero + 1LSB
:
:
:
When the DAC7731 is configured for a unipolar, 0V to 10V
output, a negative voltage supply is required. This is due to
internal biasing of the output stage. Please refer to the
“Electrical Characteristics” table for more information.
0xFFFF
Full-Scale (VREF – 1LSB)
+Full-Scale (+VREF – 1LSB
ANALOG OUTPUTS
The minimum and maximum voltage output values are dependent upon the output configuration implemented and
reference voltage applied to the DAC7731. Please note that
VSS (the negative power supply) must be in the range of
–4.75V to –15.75V for unipolar operation. The voltage on VSS
sets several bias points within the converter and is required
in all modes of operation. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not ensured.
REFERENCE INPUTS
The DAC7731 provides a built-in +10V voltage reference and
on-chip buffer to allow external component reference drive. To
use the internal reference, REFEN must be LOW, enabling the
reference circuitry of the DAC7731 (as shown in Table I) and
the REFOUT pin must be connected to REFIN. This is the input
to the on-chip reference buffer. The buffer’s output is provided
at the VREF pin. In this configuration, VREF is used to setup the
DAC7731 output amplifier into one of three voltage output
modes as discussed earlier. VREF can also be used to drive
other system components requiring an external reference.
The internal reference of the DAC7731 can be disabled when
use of an external reference is desired. When using an
external reference, the reference input, REFIN, can be any
voltage between 4.75V (or VSS + 14V, whichever is greater)
and VCC – 1.4V.
or +VREF/2 – 1LSB)
TABLE II. DAC7731 Data Format.
CONTROL STATUS
ACTION
H
H
X
X
X
Shift Register is disabled on the serial bus.
L
H
X
X
X
Enable SDO pin from High Impedance;
enables shift operation and I/O bus
(SCLK, SDI, SDO).
L
H
X
X
↑
Serial Data Shifted into Input Register
↑
H
X
X
L
Serial Data Shifted into Input Register(1)
X
H
X
↑
X
Data in Input Register is Loaded into DAC Register.
X
L
H
X
X
Resets Input and DAC Registers to mid-scale.
X
L
L
X
X
Resets Input and DAC Registers to min-scale.
NOTE: (1) In order to avoid unwanted shifting of the input register by an
additional bit, care must be taken that a rising edge on CS only occurs
when SCLK is HIGH.
TABLE III. DAC7731 Logic Truth Table.
The DAC code is provided via a 16-bit serial interface, as shown
in Table II. The digital input word makes up the digital code to
be loaded into the data input register of the device. A typical
data transfer and DAC output update takes place as follows:
Once CS is active (LOW), the DAC7731 is enabled on the serial
bus and the 16-bit serial data transfer can begin. The serial data
is shifted into the device on each rising SCLK edge until all 16
bits are transferred (1 bit per 1 rising SCLK edge). Once
received, the data in the input register is loaded into the DAC
register upon reception of a rising edge on the LDAC input (load
command). This action updates the analog output, VOUT, to the
desired voltage specified by the digital input word. A rising edge
DAC7731
SBAS249
COMMAND
CS RST RSTSEL LDAC SCLK
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11
Byte transfer mode is especially useful when an 8-bit host is
communicating with the DAC. Data transfer can occur without requiring an additional general purpose I/O pin to control
the CS input of the DAC in cycles of 16 clocks. A HIGH state
on CS stops data from coming into and out of the internal
shift register. This provides byte-wide support for 8-bit host
processors. Figure 5 is an example of the timing cycle of
such a data transfer.
on LDAC is completely asynchronous to the serial interface of
the device and can occur at any time. Care must be taken to
ensure that the entire 16 bits of data are loaded into the input
register before issuing a LDAC active edge. Additional load
commands will have no effect on the DAC output if the data in
the input register is unchanged between rising LDAC edges.
When CS is returned HIGH, the rising edge on CS must
occur when SCLK is HIGH. Application of a rising CS edge
when SCLK is LOW will cause one additional shift in the
serial input shift register, corrupting the desired input data.
The remaining data transfer mode accepted by the DAC7731
is continuous transfer. The CS of the DAC7731 can be tied
LOW or held LOW by the controller for an indefinite number of
serial clock cycles. Each clock cycle will transfer data into the
DAC via SDI and out of the DAC on SDO. Care must be taken
that the LDAC signal to the DAC(s) is timed correctly so that
valid data is transferred into the DAC register on each rising
LDAC edge. ("Valid data" refers to the serial data latched on
each of the 16 rising SCLK edges prior to the occurrence of a
rising LDAC signal.) The rising edge of LDAC must occur
before the first rising SCLK edge of the following 16-bit
TIMING CONSIDERATIONS
The flexible interface of the DAC7731 can operate under a
number of different scenarios as is required by a host
controller. Critical timing for a 16-bit data transfer cycle is
shown in the Interface Timing section of the Timing Characteristics. While this is the most common method of writing to
the DAC7731, the device accepts two additional modes of
data transfer from the host. These are byte transfer mode
and continuous transfer mode.
transfer. Figure 6 shows continuous transfer timing.
16-Bit Data Word
Most Significant Byte
CS
SCLK
SDI
1
2
B15
B14
Least Significant Byte
8
B13
9
B8
B7
Byte 1, Word N
SDO
A15
A14
10
16
B6
B0
Byte 2, Word N
A13
A7
A8
A0
A6
Byte 2, Word N – 1
Byte 1, Word N – 1
LDAC
FIGURE 5. Byte-Wide Data Write Cycle.
CS
SCLK
SDI
1
2
B15
B14
B1
16
1
2
B0
C15
C14
Word N
SDO
A15
A14
C1
16
1
2
C0
D15
D14
Word N + 1
A1
A0
B15
B14
Word N – 1
Word N + 2
B1
Word N
B0
C15
C14
Word N + 1
LDAC
FIGURE 6. Continuous Transfer Control.
12
DAC7731
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SBAS249
DAISY-CHAINING USING SDO
Multiple DAC7731’s can be connected to a single serial port
by attaching each of their control inputs in parallel and daisychaining the SDO and SDI I/O's of each device. The SDO
output of the DAC7731 is active when CS is LOW and can
be left unconnected when not required for use in a daisychain configuration.
Once a data transfer cycle begins, new data is shifted into SDI
and data currently residing in the shift register (from previous
cycle, power-up, or reset command) is presented on SDO, MSB
first. One data transfer cycle for each DAC7731 is required to
update all devices in the chain. The first data cycle written into
the chain will arrive at the last DAC7731 on the final cycle of the
data transfer. Upon completion of the required number of data
transfer cycles (one cycle per device), each DAC voltage output
is updated with a rising edge on the LDAC inputs.
Figure 8 shows the required timing to properly update two
DAC7731’s in a daisy-chained configuration, as shown in
Figure 7.
DAC RESET
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a low signal on
RST. Once RST is LOW, the DAC output will begin settling to
the mid-scale or min-scale code depending on the state of the
RSTSEL input. A HIGH value on RSTSEL will cause VOUT to
reset to the mid-scale code (8000H) and a LOW value will reset
VOUT to min-scale (8000H). A change in the state of the RSTSEL
input while RST is LOW will cause a corresponding change in
the reset command selected internally and consequently change
the output value of VOUT of the DAC. Note that a valid reset
signal also resets the input register of the DAC to the value
specified by the state of RSTSEL.
From Host
Controller
To next
DAC7731
DAC7731
1
VCC
2
REFOUT
3
REFIN
4
REFADJ
5
VREF
6
ROFFSET
7
AGND
8
9
DAC7731
VSS
24
1
VCC
REFEN
23
2
REFOUT
RSTSEL
22
3
REFIN
VSS
24
REFEN
23
RSTSEL
22
SCLK
21
CS
20
SDO
19
SDI
18
SCLK
21
4
REFADJ
CS
20
5
VREF
SDO
19
6
ROFFSET
SDI
18
7
AGND
RFB2
LDAC
17
8
RFB2
LDAC
17
RFB1
RST
16
9
RFB1
RST
16
NC
15
10 SJ
NC
15
11 VOUT
TEST
14
11 VOUT
TEST
14
12 VDD
DGND
13
12 VDD
DGND
13
10 SJ
First Device in Chain
Second Device in Chain
FIGURE 7. DAC7731 Daisy-Chain Schematic.
Both DAC VOUT's
are updated
LSBs latched
SCLK
1
2
16
LSBs latched
1
2
16
CS
LDAC
First Data Transfer Cycle
SDI
A15
A14
A0
B15
B14
B1
B0
X
A15
A14
A1
A0
Previous cycle word from host
(to DAC7731 B SDI)
SDO
X
X
FIGURE 8. DAC7731 Daisy-Chain Timing for Figure 7.
DAC7731
SBAS249
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13
RFB2
RFB1
8
9
10 SJ
AGND
7
ROFFSET
RPOT1
6
respectively.
VREF
DAC7731
Optional Gain
Adjust
5
The architecture of the DAC7731 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7731
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 9 and 10 illustrate the
relationship of offset and gain adjustments for the DAC7731
in a unipolar configuration and in a bipolar configuration,
REFADJ
GAIN AND OFFSET CALIBRATION
should be at +10V – 1LSB for the 0V to +10V or ±10V output
range and +5V – 1LSB for the ±5V output range. Figure 11
shows the generalized external offset and gain adjustment
circuitry using potentiometers.
4
APPLICATIONS
Optional Offset
Adjust
(+VREF)
ISJ
+ Full Scale
Gain Adjust
Rotates
the Line
Full Scale Range
Analog Output
1LSB
(Other Connections Omitted
for Clarity)
Input =
0000 H
Input =
FFFF H
Digital Input
OFFSET ADJUSTMENT
FIGURE 9. Relationship of Offset and Gain Adjustments for
VOUT = 0V to +10V Output Configuration.
(+VREF or +VREF/2)
Offset adjustment is accomplished by introducing a small
current into the summing junction (SJ) of the DAC7731. The
voltage at SJ, or VSJ, is dependent on the output configuration of the DAC7731. See Table IV for the required pin
strapping for a given configuration and the nominal values of
VSJ for each output range.
+ Full
Scale
REFERENCE
OUTPUT
PIN STRAPPING
CONFIGURATION CONFIGURATION ROFFSET RFB1 RFB2
1LSB
Gain
Adjust
Rotates
the Line
Full Scale
Range
Analog Output
+
VOADJ
–
FIGURE 11. Generalized External Calibration Circuitry for
Gain and Symmetrical Offset Adjustment.
Offset Adjust Translates the Line
Input =
FFFF H
Internal
Reference
External
Reference
Offset
Adjust
Translates
the Line
0V to +10V
–10V to +10V
–5V to +5V
VSJ(1)
+5V
to VREF to VOUT to VOUT
NC
NC
to VOUT +3.333V
to AGND to VOUT to VOUT +1.666V
to VREF to VOUT to VOUT
0V to VREF
–VREF to VREF
NC
NC
to VOUT
–VREF/2 to VREF/2 to AGND to VOUT to VOUT
VREF/2
VREF/3
VREF/6
NOTE: (1) Voltage measured at VSJ for a given configuration.
TABLE IV. Nominal VSJ versus VOUT and Reference Configuration.
Input = 8000H
– Full-Scale
(–VREF OR –VREF/2)
Digital Input
FIGURE 10. Relationship of Offset and Gain Adjustments for
VOUT = –10V to +10V Output Configuration. (Same
Theory Applies for VOUT = –5V to +5V.)
When calibrating the DAC’s output, offset should be adjusted
first to avoid first order interaction of adjustments. In unipolar
mode, the DAC7731’s offset is adjusted from code 0000H
and for either bipolar mode, offset adjustments are made at
code 8000H. Gain adjustment can then be made at code
FFFFH for each configuration, where the output of the DAC
14
RS
RPOT2
Zero Scale
(AGND)
Input =
0000H
R1
The current level required to adjust the DAC7731’s offset can
be created by using a potentiometer divider as shown in
Figure 11 Another alternative is to use a unipolar DAC in order
to apply a voltage, VOADJ, to the resistor RS. A ±2uA current
range applied to SJ will ensure offset adjustment coverage of
the ±0.1% maximum offset specification of the DAC7731.
When in a unipolar configuration (VSJ = 5V), only a single
resistor, RS, is needed for symmetrical offset adjustment with
a 0V to 10V VOADJ range. When in one of the two bipolar
configurations, VSJ is either +3.333V (±10V range) or +1.666V
(±5V range), and circuit values chosen to match those given
in Table V will provide symmetrical offset adjust. Please refer
to Figure 11 for component configuration.
DAC7731
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SBAS249
0V to +10V
–10V to +10V
–5V to +5V
10K
10K
10K
R1
RS
ISJ
RANGE
NOMINAL
OFFSET
ADJUSTMENT
0
5K
20K
2.5M
1.5M
1M
±2µA
±2.2µA
±1.7µA
±25mV
±55mV
±21mV
REFOUT ADJUST RANGE
40
Typical REFOUT
Adjustment Range
30
TABLE V. Recommended External Component Values for
Symmetrical Offset Adjustment (VREF = 10V).
Figure 12 illustrates the typical minimum offset adjustment
ranges provided by forcing a current at SJ for a given output
voltage configuration.
REFOUT Adjustment (mV)
OUTPUT
RPOT2
CONFIGURATION
20
10
Minimum REFOUT
Adjustment Range
0
–10
–20
–30
–40
0
2
4
6
8
10
REFADJ (V)
OFFSET ADJUST RANGE
Offset Adjustment at VOUT (mV)
50
FIGURE 13. Internal Reference Adjustment Transfer Characteristic.
typ –10V to +10V VOUT
Configuration
min (75% of typ)
25
typ
0
min (75% of typ)
0V to 10V and –5V to +5V
VOUT Configuration
–25
–1
10V + 25mV (min)
10V
10V – 25mV (max)
NOTE: "NC" is "Not Connected"
0
1
NOISE PERFORMANCE
2
ISJ (µA)
FIGURE 12. Offset Adjustment Transfer Characteristic.
GAIN ADJUSTMENT
When using the internal reference of the DAC7731, gain
adjustment is performed by adjusting the device’s internal
reference voltage via the reference adjust pin, REFADJ. The
effect of a reference voltage change on the gain of the DAC
output can be seen in the generic equation (for unipolar
configuration):
Increased noise performance of the DAC output can be
achieved by filtering the voltage reference input to the DAC7731.
Figure 14 shows a typical internal reference filter schematic. A
low-pass filter applied between the REFOUT and REFIN pins can
increase noise immunity at the DAC and output amplifier. The
REFOUT pin can source a maximum of 50µA so care should be
taken in order to avoid overloading the internal reference output.
DAC7731
Low-Pass Reference Filter
VOUT = VREFIN • (N/65536)
1.0µF
Where N is represented in decimal format and ranges from
0 to 65535.
REFADJ can be driven by a low impedance voltage source
such as a unipolar, 0V to +10V DAC or a potentiometer (less
than 100kΩ), see Figure 11. Since the input impedance of
REFADJ is typically 50kΩ, the smaller the resistance of the
potentiometer, the more linear the adjustment will be. A 10kΩ
potentiometer is suggested if linearity of the reference adjustment is of concern.
When the DAC7731’s internal reference is not used, gain
adjustments can be made via trimming the external reference applied to the DAC at REFIN. This can be accomplished
through using a potentiometer, unipolar DAC, or other means
of precision voltage adjustment to control the voltage presented to the DAC7731 by the external reference. Figure 13
and Table VI summarize the range of adjustment of the
internal reference via REFADJ.
100kΩ
1
VCC
VSS
24
2
REFOUT
REFEN
23
3
REFIN
RSTSEL
22
4
REFADJ
SCLK
21
5
VREF
CS
20
6
ROFFSET
SDO
19
7
AGND
SDI
18
8
RFB2
LDAC
17
9
RFB1
RST
16
NC
15
11 VOUT
TEST
14
12 VDD
DGND
13
10 SJ
(Other connections omitted for clarity.)
FIGURE 14. Filtering the Internal Reference.
DAC7731
SBAS249
REFOUT VOLTAGE
REFADJ = 0V
REFADJ = 5V or NC(1)
REFADJ = 10V
TABLE VI. Minimum Internal Reference Adjustment Range.
–50
–2
VOLTAGE AT REFADJ
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15
LAYOUT
A precision analog component requires careful layout, adequate
bypassing, and clean, well-regulated power supplies. The
DAC7731 offers separate digital and analog supplies, as it will
often be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more digital
logic present in the design and the higher the switching speed,
the more important it will become to separate the analog and
digital ground and supply planes at the device.
Since the DAC7731 has both analog and digital ground pins,
return currents can be better controlled and have less effect
on the DAC output error. Ideally, AGND would be connected
directly to an analog ground plane and DGND to the digital
ground plane. The analog ground plane would be separate
from the ground connection for the digital components until
they were connected at the power-entry point of the system.
16
The voltages applied to VCC and VSS should be well regulated
and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on
the output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connections and analog output.
In addition, a 1µF to 10µF bypass capacitor in parallel with a
0.1µF bypass capacitor is strongly recommended for each
supply input. In some situations, additional bypassing may be
required, such as a 100µF electrolytic capacitor or even a "Pi"
filter made up of inductors and capacitors–all designed to
essentially low-pass filter the analog supplies, removing any
high frequency noise components.
DAC7731
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SBAS249
PACKAGE DRAWING
MSSO002D – JANUARY 1995 – REVISED SEPTEMBER 2000
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°– 8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /D 09/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
DAC7731
SBAS249
www.ti.com
17
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
DAC7731E
ACTIVE
SSOP
DB
24
60
None
CU SNPB
Level-3-220C-168 HR
DAC7731E/1K
ACTIVE
SSOP
DB
24
1000
None
CU SNPB
Level-3-220C-168 HR
DAC7731EB
ACTIVE
SSOP
DB
24
60
None
CU SNPB
Level-3-220C-168 HR
DAC7731EB/1K
ACTIVE
SSOP
DB
24
1000
None
CU SNPB
Level-3-220C-168 HR
DAC7731EC
ACTIVE
SSOP
DB
24
60
None
CU SNPB
Level-3-220C-168 HR
DAC7731EC/1K
ACTIVE
SSOP
DB
24
1000
None
CU SNPB
Level-3-220C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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