DRV 104 DRV104 ® SBVS036A – SEPTEMBER 2003 – REVISED NOVEMBER 2003 1.2A PWM High-Side Driver for Solenoids, Coils, Valves, Heaters, and Lamps FEATURES DESCRIPTION ● HIGH OUTPUT DRIVE: 1.2A ● WIDE SUPPLY RANGE: +8V to +32V ● COMPLETE FUNCTION: PWM Output Adjustable Internal Oscillator: 500Hz to 100kHz Digitally Controlled Input Adjustable Delay and Duty Cycle Over-Current Indicator Flag ● FULLY PROTECTED: Thermal Shutdown with Indicator Flag Internal Current Limit ● PACKAGE: HTSSOP-14 Surface-Mount PowerPAD™ The DRV104 is a DMOS, high-side power switch employing a pulse-width modulated (PWM) output. Its rugged design is optimized for driving electromechanical devices such as valves, solenoids, relays, actuators, and positioners. It is also ideal for driving thermal devices such as heaters, coolers, and lamps. PWM operation conserves power and reduces heat rise, resulting in higher reliability. In addition, adjustable PWM allows fine control of the power delivered to the load. Time from dc-to-PWM output and oscillator frequency are externally adjustable. Separate supply pins for the circuit and driver transistor allow the output to operate on a different supply than the rest of the circuit. APPLICATIONS ● ELECTROMECHANICAL DRIVERS: Solenoids, Valves, Positioners, Actuators, Relays, Power Contactor Coils, Heaters, and Lamps ● FLUID AND GAS FLOW SYSTEMS ● FACTORY AUTOMATION ● PART HANDLERS AND SORTERS ● PHOTOGRAPHIC PROCESSING ● ENVIRONMENTAL MONITORING AND HVAC ● THERMOELECTRIC COOLERS ● MOTOR SPEED CONTROLS DRV104 ● SOLENOID PROTECTORS ● MEDICAL ANALYZERS The DRV104 can be set to provide a strong initial solenoid closure, automatically switching to a soft hold mode for power savings. The duty cycle can be controlled by a resistor, analog voltage, or a digital-to-analog (D/A) converter for versatility. The Status OK Flag pin indicates when thermal shutdown or over-current occurs. The DRV104 is specified for –40°C to +85°C at its case. The exposed lead frame must be soldered to the circuit board. Status OK Flag +VS Thermal Shutdown Over/Under Current +VPS1 VREF +VPS2 Oscillator PWM Input On OUT1 Delay OUT2 Off Delay Adj Osc Freq Adj Duty Cycle Adj GND BOOT Coil Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright © 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage VS, VPS1, VPS2(2) ....................................................... +40V Input Voltage, Master, SYNC ......................................... –0.2V to +5.5V(3) PWM Adjust Input .......................................................... –0.2V to +5.5V(3) Delay Adjust Input .......................................................... –0.2V to +5.5V(3) Frequency Adjust Input .................................................. –0.2V to +5.5V(3) Status OK Flag and OUT .................................................... –0.2V to VS(4) Boot Voltage ............................................................................... VS + 10V Operating Temperature Range ...................................... –55°C to +125°C Storage Temperature ..................................................... –65°C to +150°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) See the Bypass section for discussion about operating near the maximum supply. (3) Higher voltage may be applied if current is limited to 2mA. (4) Status OK flag will internally current limit at about 10mA. PACKAGE/ORDERING INFORMATION PRODUCT DRV104 PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PowerPAD HTSSOP-14 PWP –40°C to +85°C DRV104 " " " " DRV104PWP DRV104PWPR Rails, 90 Tape and Reel, 2000 " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. LOGIC BLOCK DIAGRAM Status OK Flag 13 DRV104 Master SYNC Thermal Shutdown Over Current 4 +VS 10 DMOS 8 12 9 1.25V VREF Oscillator +VPS1 +VPS2 DMOS Input 14 On PWM Delay 6 OUT1 2.75 • IREF IREF 7 OUT2 Off 2 2 Delay Adj 3 Osc Freq Adj CD RFREQ 1 Duty Cycle Adj 11 GND 5 CBOOT Coil RPWM DRV104 www.ti.com SBVS036A ELECTRICAL CHARACTERISTICS At TC = +25°C, VS = VPS = +24V, Load = 100Ω, 4.99kΩ Status OK flag pull-up to +5V, Boot capacitor = 470pF, Delay Adj Capacitor (CD) = 100pF to GND, Osc Freq Adj Resistor = 191kΩ to GND, Duty Cycle Adj Resistor = 147kΩ to GND, and Master and SYNC open, unless otherwise noted. DRV104 PARAMETER OUTPUT Output Saturation Voltage, Source Current Limit(1)(7) Leakage Current DELAY TO PWM(3) Delay Equation(4) Delay Time Minimum Delay Time(5) DUTY CYCLE ADJUST Duty Cycle Range Duty Cycle Accuracy vs Supply Voltage Nonlinearity(6) DYNAMIC RESPONSE Output Voltage Rise Time Output Voltage Fall Time SYNC Output Rise Time SYNC Output Fall Time Oscillator Frequency Range Oscillator Frequency Accuracy STATUS OK FLAG Normal Operation Fault(7) Over-Current Flag: Set—Delay INPUT(2) VINPUT Low VINPUT High IINPUT Low (output disabled) IINPUT High (output enabled) Propagation Delay (master mode) MASTER INPUT VMSTR Low VMSTR High IMSTR Low (slave mode) IMSTR High (master mode) SYNC INPUT VSYNC Low VSYNC High IMSTR Low (OUT disabled in slave mode) IMSTR High (OUT disabled in slave mode) Propagation Delay SYNC OUTPUT(9) VOL Sync VOH Sync CONDITIONS MIN IO = 1A IO = 0.1A 1.2 DMOS Output Off, VPS = VS = 32V MAX UNITS +0.45 +0.05 2.0 1 +0.65 +0.07 2.6 10 V V A µA DC to PWM Mode CD = 0.1µF CD = 0 Delay to PWM ≈ CD • 106(CD in F • 1.24) 60 80 100 18 s ms µs 50% Duty Cycle, 25kHz 50% Duty Cycle, VS = VPS = 8V to 32V 10% to 90% Duty Cycle 10 to 90 ±2 ±2 1 % % % % FSR VO = 10% to 90% of VPS VO = 90% to 10% of VPS VSYNC = 10% to 90% VSYNC = 10% to 90% External Adjust RFREQ = 191kΩ 1 0.2 0.5 0.5 0.5 to 100 25 20kΩ Pull-Up to +5V 4.99kΩ Pull-Up to +5V 20 +4.5 +5 +0.45 5 0 +2.2 VINPUT = 0V VINPUT = +4.5V On to Off and Off to On, INPUT to OUT On to Off and Off to On, INPUT to SYNC 0.01 0.01 2.2 0.4 0 +2.2 VINPUT = 0V VINPUT = +4.5V 15 15 0 +2.2 VINPUT = 0V VINPUT = +4.5V On to Off and Off to On, SYNC to OUT (slave) ISYNC = 100µA (sinking) ISYNC = 100µA (sourcing) 0.01 0.01 2.2 +4.0 THERMAL SHUTDOWN Junction Temperature Shutdown Reset from Shutdown POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current (VS) TYP 0.1 +4.2 ±5 2 2 2 2 30 +0.6 V V µA µA µs µs +1.2 +5.5 25 25 V V µA µA +1.2 +5.5 1 1 V V µA µA µs 0.3 V V °C °C +24 IO = 0 TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance, θJA(8) HTSSOP-14 with PowerPAD 0.6 –40 –55 –65 37.5 V V µs +1.2 +5.5 1 1 +160 +140 +8 µs µs µs µs kHz kHz +32 1 V V mA +85 +125 +150 °C °C °C °C/W NOTES: (1) Output current resets to zero when current limit is reached. (2) Logic high enables output (normal operation). (3) Constant dc output to PWM (PulseWidth Modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust Pin low corresponds to an infinite (continuous) delay. (5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 1 to percent of duty cycle at pins 6 and 7. (7) Flag indicates fault from overtemperature or over-current conditions. (8) θJA = 37.5°C/W measured on JEDEC standard test board. θJC = 2.07°C/W. (9) SYNC output follows power output in master mode. Power output follows SYNC input in slave mode. DRV104 SBVS036A www.ti.com 3 PIN CONFIGURATION Top View HTSSOP Duty Cycle Adj 1 14 Input Delay Adj 2 13 Status OK Flag Osc Freq Adj 3 12 SYNC Master 4 Boot 5 10 +VS OUT1 6 9 VPS1 OUT2 7 8 VPS2 DRV104 PowerPAD Top View SO Duty Cycle Adj 1 Delay Adj 3 14 Input 12 Status OK Flag DRV103 PowerPAD 11 GND Osc Freq Adj 5 10 +VS GND 7 8 OUT DRV103 for Reference PIN DESCRIPTIONS 4 PIN NAME DESCRIPTION 1 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a (2.75 x IREF) current source from VS. The voltage at this node linearly sets the duty cycle. The duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, the output duty cycle is near 90%. At 1.5V, the output duty cycle is near 10%. Internally, this pin is forced to 1.24V. No connection is required when the device is in slave mode. 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results in a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than 3µs by tying the pin to 5V. This pin connects internally to a 15µA current source from VS and to a 2.6V threshold comparator. When the pin voltage is below 2.6V, the output device is 100% On. The PWM oscillator is not synchronized to the Input (pin 1), so the duration of the first pulse may be any portion of the programmed duty cycle. No connection is required when the device is in slave mode. 3 Oscillator Frequency Adjust PWM frequency is adjustable. A resistor to ground sets the current IREF and the internal PWM oscillator frequency. A range of 500Hz to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors higher than 10MΩ will be required. The pin then becomes a very high-impedance node and is, therefore, sensitive to noise pickup and PCB leakage currents. Resistor connection to this pin in slave mode sets the frequency at which current limit reset occurs. 4 Master With no connection, this pin is driven to 5V by an internal 15µA current source. In this mode the device is the master and the SYNC pin becomes a 0V to 4.2V output, which is High when the power device is on. When the Master/Input is 0V, the SYNC pin is an input. In slave mode, the output follows the SYNC pin; the output is High when SYNC is High. 5 BOOT The bootstrap capacitor between this pin and the output, supplies the charge to provide the VGS necessary to turn on the power device. CBOOT should be larger than 100pF. Use of a smaller CBOOT may slow the output rise time, device is specified and tested with 470pF. 6, 7 OUT1, OUT2 The output is the source of a power DMOS transistor with its drain connected to VPS. Its low on-resistance (0.45Ω typ) assures low power dissipation in the DRV104. Gate drive to the power device is controlled to provide a slew-rate limited rise-and-fall time. This reduces the radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off cycle. The external diode should be selected for low forward voltage and low storage time. The internal diode should not be used as a flyback diode. If devices are connected in parallel, the outputs must be connected through individual diodes. Devices are current-limit protected for shorts to ground, but not to supply. 8, 9 VPS1, VPS2 These are the load power-supply pins to the drain of the power device. The load supply voltage may exceed the voltage at pin 10 by 5V, but must not exceed 37V. 10 +VS This is the power-supply connection for all but the drain of the power device. The operating range is 8V to 32V. 11 GND This pin must be connected to the system ground for the DRV104 to function. It does not carry the load current when the power DMOS device is switched on. 12 SYNC The SYNC pin is a 0V to 4.2V copy of the output when the Master/Slave pin is High. As an output, it can supply 100µA with 1kΩ output resistance. At 2mA, it current limits to either 4.2V or 0V. When the Master pin is Low, it is an input and the threshold is 2V. SYNC output follows power output in master mode, and is not affected by thermal or current-limit shutdown. Power output follows SYNC input in slave mode. 13 Status OK Flag Normally High (active Low), a Flag Low signals either an over-temperature or over-current fault. A thermal fault (thermal shutdown) occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pullup resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA, typical. 14 Input The input is compatible with standard TTL levels. The device becomes enabled when the input voltage is driven above the typical switching threshold, 1.8V; below this level, the device is disabled. Input current is typically 1µA when driven High and 1µA when driven Low. The input should not be directly connected to the power supply (VS) or damage will occur. DRV104 www.ti.com SBVS036A TYPICAL CHARACTERISTICS At TC = +25°C and VS = +24V, unless otherwise noted. VOUT AND ISOLENOID WAVEFORMS WITH SOLENOID LOAD VOUT AND IOUT WAVEFORMS WITH RESISTIVE LOAD Input PWM Mode +VS +VS PWM Mode 0 VOUT 0 0 2 RL 1 0 IOUT (A) 1 drop-out pull-in 0 IAVG +VS ISOLENOID (A) 2 0 ON ON 0 50 100 0 50 Time (ms) 100 Time (ms) CURRENT LIMIT SHUTDOWN WAVEFORMS QUIESCENT CURRENT vs TEMPERATURE 0.70 On Off 0.65 OK Status OK Flag OK OK OK OK OK 0 OK 24 0 24 VOUT 0 32V Current (mA) 5 VIN (V) Off VOUT (V) VIN 12V 24V 0.60 0.55 0.50 8V 0.45 0.40 0 50 100 –60 40 –10 Time (µs) 90 140 Temperature (°C) CURRENT LIMIT SHUTDOWN vs TEMPERATURE DELAY TO PWM vs TEMPERATURE 2.5 88 CD = 0.1µF 86 2.1 Delay (ms) Current Limit (A) 2.3 1.9 84 82 24V 1.7 12V, 8V 80 1.5 1.3 32V 78 –60 –10 40 90 140 –60 Temperature (°C) 40 90 140 Temperature (°C) DRV104 SBVS036A –10 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TC = +25°C and VS = +24V, unless otherwise noted. OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE MINIMUM DELAY vs JUNCTION TEMPERATURE 26.0 14 CD = 0pF 8V RFREQ = 191kΩ 32V 12V 12V 25.5 12 Frequency (kHz) Minimum Delay (µs) 13 11 10 9 32V 25.0 24V 12V 24.5 8 24V 7 24.0 6 –60 40 –60 140 –10 40 90 140 Temperature (°C) Temperature (°C) VSAT vs JUNCTION TEMPERATURE DUTY CYCLE vs JUNCTION TEMPERATURE 0.8 53 32V RPWM = 147kΩ 52 VSAT at 1 Amp (V) Duty Cycle (%) 24V 51 50 49 0.6 0.4 0.2 48 8V 12V 0 47 40 –60 –60 140 VREF vs TEMPERATURE 1.250 Input Current (µA) 1.248 VREF (V) 140 200 24V 1.247 12V 150 100 50 1.245 1.244 0 –60 –10 40 90 140 4 Temperature (°C) 6 90 INPUT CURRENT vs INPUT VOLTAGE 32V 8V 40 250 1.249 1.246 –10 Temperature (°C) Temperature (°C) 5 6 Input Voltage (V) DRV104 www.ti.com SBVS036A BASIC OPERATION to set a longer delay time. A resistor, analog voltage, or a voltage from a D/A converter can be used to control the duty cycle of the PWM output. The D/A converter must be able to sink a current of 2.75 • IREF (IREF = VREF/RFREQ). The DRV104 is a high-side, DMOS power switch employing a PWM output for driving electromechanical and thermal devices. Its design is optimized for two types of applications: as a 2-state driver (open/close) for loads such as solenoids and actuators; and a linear driver for valves, positioners, heaters, and lamps. Its low 0.45Ω On resistance, small size, adjustable delay to PWM mode, and adjustable duty cycle make it suitable for a wide range of applications. Figure 2 illustrates a typical timing diagram with the Delay Adjust pin connected to a 4.7nF capacitor, the duty cycle set to 75%, and oscillator frequency set to 1kHz. See the Adjustable and Adjustable Delay Time section for equations and further explanation. Ground (pin 11) must be connected to the system ground for the DRV104 to function. The load (relay, solenoid, valve, etc.) should be connected between the ground and the output (pins 6, 7). For an inductive load, an external flyback diode is required, as shown in Figure 1. The diode maintains continuous current flow in the inductive load during Off periods of PWM operation. For remotely located loads, the external diode is ideally located next to the DRV104. The internal ESD clamp diode between the output and ground is not intended to be used as a “flyback diode.” The Status OK Flag (pin 13) provides fault status for overcurrent and thermal shutdown conditions. This pin is active Low with an output voltage of typically +0.48V during a fault condition. Figure 1 shows the basic circuit connections to operate the DRV104. A 1µF (10µF when driving high current loads) or larger ceramic bypass capacitor is recommended on the power-supply pin. Control input (pin 14) is level-triggered and compatible with standard TTL levels. An input voltage between +2.2V and +5.5V turns the device’s output On, while a voltage of 0V to +1.2V shuts the DRV104’s output Off. Input bias current is typically 1µA. Delay Adjust (pin 2) and Duty Cycle Adjust (pin 1) allow external adjustment of the PWM output signal. The Delay Adjust pin can be left floating for minimum delay to PWM mode (typically 18µs) or a capacitor can be used +VS 1µF + RLED 2mA NOTES: (1) Motorola MSRS1100T3 (1A, 100V), (2) Performance specified with CBOOT = 470pF. (3) When switching a high-load current, a 100pF capacitor in parallel with RFREQ is 13 14 VPS Osc Freq Adj 2 6, 7 OUT Duty Cycle Adj 3 CD and duty cycle, see Figure 5. +VS DRV104 Delay Adj recommended to maintain a clean output switching waveform 10 8, 9 Status OK Flag TTL IN Motorola MBRS360T3 (3A, 60V), or Microsemi SK34MS (3A, 40V). +8V to +32V LED OK = LED On 1 RFREQ(3) 11 3A Flyback Diode(1) CBOOT(2) GND Relay 5 RPWM FIGURE 1. DRV104 Basic Circuit Connections. On TTL High Input (V) TTL Low Off Period = Off 1 = TON + TOFF FREQ +VS VO (V) 0 Delay Time +VS/RL IO (A) Duty Cycle = TOFF TON TON TON + TOFF 0 0 1 2 3 4 Time (ms) 5 6 7 8 9 FIGURE 2. Typical Timing Diagram. DRV104 SBVS036A www.ti.com 7 APPLICATIONS INFORMATION POWER SUPPLY The DRV104 operates from a single +8V to +32V supply with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage are shown in the Typical Characteristics. pickup and PCB leakage currents if very high resistor values are used. Refer to Figure 3 for a simplified circuit of the frequency adjust input. The DRV104’s adjustable PWM output frequency allows it to be optimized for driving virtually any type of load. +VS 3µA ADJUSTABLE DELAY TIME (INITIAL 100% DUTY CYCLE) A unique feature of the DRV104 is its ability to provide an initial constant DC output (100% duty cycle) and then switch to PWM mode output to save power. This function is particularly useful when driving solenoids that have a much higher pull-in current requirement than continuous-hold requirement. The duration of this constant DC output (before PWM output begins) can be externally controlled by a capacitor connected from Delay Adjust (pin 2) to ground according to Equation 1: Delay Time ≈ (CD • 106)/1.24 CD Reset +2.6V Input VREF VREF +1.25V IREF RFREQ (1) FIGURE 3. Simplified Delay Adjust and Frequency Adjust Inputs. (time in seconds, CD in Farads) Leaving the Delay Adjust pin open results in a constant output time of approximately 18µs. The duration of this initial output can be reduced to less than 3µs by connecting the pin to 5V. Table I provides examples of delay times (constant output before PWM mode) achieved with selected capacitor values. The internal Delay Adjust circuitry is composed of a 3µA current source and a 2.6V comparator, as shown in Figure 3. Thus, when the pin voltage is less than 2.6V, the output device is 100% On (DC output mode). OSCILLATOR FREQUENCY (Hz) RFREQ (nearest 1% values) (Ω) 100k 50k 25k 10k 5k 500 47.5k 100k 191k 499k 976M 10M TABLE II. Oscillator Frequency Resistance. PWM FREQUENCY vs RFREQ OSCILLATOR FREQUENCY ADJUST 1000M 100M 10M RFREQ (Ω) The DRV104 PWM output frequency can be easily programmed over a wide range by connecting a resistor (RFREQ) between Osc Freq Adj (pin 3) and ground. A range of 500Hz to 100kHz can be achieved with practical resistor values, as shown in Table II. Refer to the PWM Frequency vs RFREQ plot shown in Figure 4 for additional information. Although oscillator frequency operation below 500Hz is possible, resistors higher than 10MΩ will be required. The pin becomes a very high impedance node and is therefore sensitive to noise 1M 100k 10k RFREQ (kΩ ) = 1k INITIAL CONSTANT OUTPUT DURATION CD 3µs 18µs 81µs 0.81ms 8.1ms 81ms 0.81s 8.1s Pin 2 Tied to +5V Pin 2 Open 100pF 1nF 10nF 100nF 1µF 10µF 10 100 1 1.4518 × 10−6 + 2.0593 × 10−7 × F(Hz) 1k 10k 100k 1M Frequency (Hz) FIGURE 4. Using a Resistor to Program Oscillator Frequency. When switching a high-load current, 100pF capacitors in parallel with RFREQ are recommended to maintain a clean output switching waveform and duty cycle, see Figure 5. TABLE I. Delay Adjust Times. 8 DRV104 www.ti.com SBVS036A DUTY CYCLE vs RPWM 10M RFREQ only RPWM (kΩ) = 334.35 + 7.75(%DC) 1M RPWM (Ω) With 100pF in Parallel with RFREQ 5kHz RPWM (kΩ) = 68.73 + 1.52(%DC) 25kHz 100k 100kHz RPWM (kΩ) = 20.62 + 0.39(%DC) 10k Time (10µs) 0 20 40 60 80 100 Duty Cycle (%) FIGURE 5. Output Waveform at High Load Current. FIGURE 6. Using a Resistor to Program Duty Cycle. ADJUSTABLE DUTY CYCLE (PWM MODE) Voltage Controlled Duty Cycle The DRV104’s externally adjustable duty cycle provides an accurate means of controlling power delivered to a load. Duty cycle can be set over a range of 10% to 90% with an external resistor, analog voltage, or the voltage output of a D/A converter. A low duty cycle results in reduced power dissipation in the load. This keeps the DRV104 and the load cooler, resulting in increased reliability for both devices. The duty cycle can also be programmed by analog voltage VPWM. With VPWM ≈ 3.59V, the duty cycle is about 90%. Decreasing this voltage results in decreased duty cycles. Table IV provides VPWM values for typical duty cycles. Figure 7 shows the relationship of duty cycle versus VPWM and its linearity. Resistor Controlled Duty Cycle DUTY CYCLE AND DUTY CYCLE ERROR vs VOLTAGE 100 2.0 At VS = 24V and F = 25kHz: VPWM = 1.25 + 0.026 × %DC 90 1.0 Duty Cycle 70 0.5 60 0 50 40 –0.5 Duty Cycle Error 30 –1.0 Duty Cycle Error (%) 1.5 80 Duty Cycle (%) Duty cycle is easily programmed by connecting a resistor (RPWM) between Duty Cycle Adjust (pin 1) and ground. High resistor values correspond to high duty cycles. At 100kHz, the range of adjustable duty cycle is limited to 10% to 70%. Table III provides resistor values for typical duty cycles. Resistor values for additional duty cycles can be obtained from Figure 6. 20 (%) 5kHz 25kHz 100kHz 10 20 30 40 50 60 70 80 90 412k 487k 562k 649k 715k 787k 887k 953k 1050k 84.5k 97.6k 113k 130k 147k 162k 174k 191k 205k 25.5k 28.7k 31.6k 35.7k 39.2k 43.2k 44.9k — — –1.5 10 RPWM (Ω) (Nearest 1% Values) DUTY CYCLE –2.0 0 1 2 3 4 VPWM (V) FIGURE 7. Using a Voltage to Program Duty Cycle. TABLE III. Duty Cycle Adjust Resistance. DUTY CYCLE (%) VPWM (V) 10 20 40 60 80 90 1.501 1.773 2.296 2.813 3.337 3.589 TABLE IV. Duty Cycle Adjust Voltage. DRV104 SBVS036A www.ti.com 9 The Duty Cycle Adjust pin is internally driven by an oscillator frequency dependent current source and connects to the input of a comparator, as shown in Figure 8. The DRV104’s PWM adjustment is inherently monotonic; that is, a decreased voltage (or resistor value) always produces an decreased duty cycle. +5V 5kΩ Pull-Up TTL or HCT 8, 9 Status OK Flag 13 VPS Thermal Shutdown Over-Current 3.9V OSC PWM 1.3V +VS 6, 7 DRV104 2.75 • IREF OUT FIGURE 9. Non-Latching Fault Monitoring Circuit. RPWM +5V 74XX76A VS FIGURE 8. Simplified Duty Cycle Adjust Input. OK Q OK Q OK Reset 20kΩ J CLR CLK (1) STATUS OK FLAG GND The Status OK Flag (pin 13) provides a fault indication for over-current and thermal shutdown conditions. During a fault condition, the Status OK Flag output is driven Low (pin voltage typically drops to 0.45V). A pull-up resistor, as shown in Figure 9, is required to interface with standard logic. Figure 9 also gives an example of a non-latching fault monitoring circuit, while Figure 10 provides a latching version. The Status OK Flag pin can sink up to 10mA, sufficient to drive external logic circuitry, a reed relay, or an LED (as shown in Figure 11) to indicate when a fault has occurred. In addition, the Status OK Flag pin can be used to turn off other DRV104s in a system for chain fault protection. K 8, 9 Status OK Flag 13 VPS Thermal Shutdown Over-Current PWM 6, 7 DRV104 OUT NOTE: (1) A small capacitor (10pF) may be required in noisy environments. FIGURE 10. Latching Fault Monitoring Circuit. Over-Current Fault An over-current fault occurs when the PWM peak output current is greater than typically 2.0A. The Status OK flag is not latched. Since current during PWM mode is switched on and off, the Status OK flag output will be modulated with PWM timing (see the Status OK flag waveforms in the Typical Characteristics). +5V 5kΩ (LED) HLMP-Q156 Status OK Flag 13 Avoid adding capacitance to pins 6, 7 (OUT) because this can cause momentary current limiting. 8, 9 VPS Thermal Shutdown Over-Current Over-Temperature Fault A thermal fault occurs when the die reaches approximately 160°C, producing an effect similar to pulling the input low. Internal shutdown circuitry disables the output. The Status OK Flag is latched in the Low state (fault condition) until the die has cooled to approximately 140°C. PWM DRV104 6, 7 OUT FIGURE 11. Using an LED to Indicate a Fault Condition. 10 DRV104 www.ti.com SBVS036A PACKAGE MOUNTING THERMAL RESISTANCE vs PCB COPPER AREA Figure 12 provides recommended printed circuit board (PCB) layouts for the PowerPAD HTSSOP-14 package. The metal pad of the PowerPAD HTSSOP-14 package is electrically isolated from other pins and ideally should be connected to a ground. For reliable operation, the PowerPAD must be directly soldered to a circuit board, as shown in Figure 13. Increasing the heat-sink copper area improves heat dissipation. Figure 14 shows typical junction-to-ambient thermal resistance as a function of the PCB copper area. Thermal Resistance, θJA (°C/W) 80 DRV104 PowerPAD Surface-Mount Package 1oz. Copper 70 60 50 40 30 0 DRV104 Die 1 2 3 4 5 Copper Area (inches2) FIGURE 14. Heat-Sink Thermal Resistance vs PCB Copper Area. Pad-to-Board Solder Signal Trace POWER DISSIPATION The DRV104 power dissipation depends on power supply, signal, and load conditions. Power dissipation (PD) is equal to the product of output current times the voltage across the conducting DMOS transistor times the duty cycle. Using the lowest possible duty cycle necessary to assure the required hold force can minimize power dissipation in both the load and in the DRV104. At 1A, the output DMOS transistor on-resistance is 0.45Ω, increasing to 0.65Ω at current limit. Copper Pad Copper Traces Thermal Vias FIGURE 13. PowerPAD Heat Transfer. 3.5 2.0 2.0 2.4 1.0 2.0 0.0 Solder Attachment to PCB 0.65 (all dimensions in mm) FIGURE 12. Recommended PCB Layout. DRV104 SBVS036A www.ti.com 11 At very high oscillator frequencies, the energy in the DRV104’s linear rise and fall times can become significant and cause an increase in PD. THERMAL PROTECTION Power dissipated in the DRV104 causes its internal junction temperature to rise. The DRV104 has an on-chip thermal shutdown circuitry that protects the IC from damage. The thermal protection circuitry disables the output when the junction temperature reaches approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on load and signal conditions, the thermal protection circuit may cycle on and off. This limits the dissipation of the driver but may have an undesirable effect on the load. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature should be limited to a maximum of +125°C. To estimate the margin of safety in a complete design (including heat-sink), increase the ambient temperature until the thermal protection is triggered. Use worst-case load and signal conditions. For good reliability, thermal protection should trigger more than 35°C above the maximum expected ambient condition of your application. This produces a junction temperature of 125°C at the maximum expected ambient condition. The internal protection circuitry of the DRV104 is designed to protect against overload conditions. It is not intended to replace proper heat sinking. Continuously running the DRV104 into thermal shutdown will degrade device reliability. HEAT SINKING Most applications do not require a heat-sink to assure that the maximum operating junction temperature (125°C) is not exceeded. However, junction temperature should be kept as low as possible for increased reliability. Junction temperature can be determined according to the following equations: TJ = TA + PDθJA (3) θJA = θJC + θCH + θHA (4) Heat-Sink Selection Example A PowerPAD HTSSOP-14 package dissipates 2W. The maximum expected ambient temperature is 35°C. Find the proper heat-sink to keep the junction temperature below 125°C. Combining Equations 1 and 2 gives: TJ = TA + PD(θJC + θCH + θHA) (5) TJ, TA, and PD are given. θJC is provided in the specification table: 2.07°C/W. θCH depends on heat sink size, area, and material used. Semiconductor package type and mounting can also affect θCH. A typical θCH for a soldered-in-place PowerPAD HTSSOP-14 package is 2°C/W. Now, solving for θHA: θHA = θ HA = TJ – TA – (θ JC + θCH ) PD 125°C – 35°C – (2.07°C / W + 2°C / W ) 2W (6) θ HA = 40.9°C / W To maintain junction temperature below 125°C, the heat-sink selected must have a θHA less than 40.9°C/W. In other words, the heat-sink temperature rise above ambient temperature must be less than 81.8°C (40.9°C/W • 2W). Another variable to consider is natural convection versus forced convection air flow. Forced-air cooling by a small fan can lower θCA (θCH + θHA) dramatically. As mentioned above, once a heat-sink has been selected, the complete design should be tested under worst-case load and signal conditions to ensure proper thermal protection. where: RFI/EMI TJ = Junction Temperature (°C) Any switching system can generate noise and interference by radiation or conduction. The DRV104 is designed with controlled slew rate current switching to reduce these effects. By slowing the rise time of the output to 1µs, much lower switching noise is generated. TA = Ambient Temperature (°C) PD = Power Dissipated (W) θJC = Junction-to-Case Thermal Resistance (°C/W) θCH = Case-to-Heat Sink Thermal Resistance (°C/W) θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W) θJA = Junction-to-Air Thermal Resistance (°C/W) Using a heat sink significantly increases the maximum allowable power dissipation at a given ambient temperature. 12 The answer to the question of selecting a heat-sink lies in determining the power dissipated by the DRV104. For DC output into a purely resistive load, power dissipation is simply the load current times the voltage developed across the conducting output transistor times the duty cycle. Other loads are not as simple. (For further information on calculating power dissipation, refer to Application Bulletin SBFA002, available at www.ti.com.) Once power dissipation for an application is known, the proper heat-sink can be selected. Radiation from the DRV104-to-load wiring (the antenna effect) can be minimized by using twisted pair cable or by shielding. Good PCB ground planes are recommended for low noise and good heat dissipation. Refer to the Bypassing section for notes on placement of the flyback diode. DRV104 www.ti.com SBVS036A BYPASSING A 1µF ceramic bypass capacitor is adequate for uniform duty cycle control when switching loads of less than 0.5A. Larger bypass capacitors are required when switching high-current loads. A 10µF ceramic capacitor is recommended for heavyduty (1.2A) applications. It may also be desirable to run the DRV104 and load driver on separate power supplies at highload currents. Bypassing is especially critical near the absolute maximum supply voltage of 32V. In the event of a current overload, the DRV104 current limit responds in microseconds, dropping the load current to zero. With inadequate bypassing, energy stored in the supply line inductance can lift the supply sufficiently to exceed voltage breakdown with catastrophic results. Place the flyback diode at the DRV104 end when driving long (inductive) cables to a remotely located load. This minimizes RFI/EMI and helps protect the output DMOS transistor from breakdown caused by dI/dt transients. Fast rectifier diodes such as epitaxial silicon or Schottky types are recommended for use as flyback diodes. APPLICATIONS CIRCUITS SINGLE AND MULTICHANNEL The DRV104 can be used in a variety of ways with resistive and inductive loads. As a single-channel driver, it can be placed on one PC board or inside a solenoid, relay, actuator, valve, motor, heater, thermoelectric cooler, or lamp housing. In high-density systems, multichannel power drivers may be packed close together on a PC board. For these switching applications, it is important to provide power supply bypassing as close to the driver IC as possible to avoid crosscoupling of spikes from one circuit to another. Also, in some applications, it may be necessary to keep beat frequencies (sum and difference between DRV oscillators or between DRV oscillators and system clock frequencies) from interfering with low-level analog circuits that are located relatively near to the power drivers. Paralleling device outputs is not recommended as unequal load sharing and device damage will result. BEAT FREQUENCIES IN NON-SYNCHRONIZED MULTICHANNEL SYSTEMS In many multichannel systems, beat frequencies are of no consequence where each DRV uses its own internal oscillator. DRV104s, a beat frequency of 22.5kHz can be established by setting one internal oscillator to a center of 62.5kHz and the other to 40kHz. Considering the specification of ±20% frequency accuracy, the beat could range from 2kHz (48kHz and 50kHz) to 43kHz (75kHz and 32kHz). By limiting the analog measurement bandwidth to 100Hz, for example, interference can be avoided. BEAT FREQUENCY ELIMINATION—OPTIONAL SYNCHRONIZATION The benefit of synchronization in multichannel systems is that measurement interference can be avoided in low-level analog circuits, particularly when physically close to the DRVs. Specifically, synchronization will accomplish the following: 1. Eliminate beat frequencies between DRVs or DRVs and the system clock. 2. Predict quiet or non-switching times. Synchronization of DRV104s is possible by using one oscillator frequency for all DRVs. See Figure 15 for an example of one DRV internal oscillator as the master and the others as slaves. Also, one external clock can be used as the master and all the others as slaves. PEAK SUPPLY CURRENT ELIMINATION—OPTIONAL SWITCHING SKEW In many systems, particularly where only a few channels are used or low magnitude load currents are present, it is unnecessary to skew the switching times. In some multichannel systems, where just PWM is used, without initial dc time delay, simultaneous switching of edges can cause large peak currents to be drawn from the main power supply. This is similar to that which occurs when multiple switching power supplies draw current from one power source. Peak currents can be reduced by synchronizing oscillators and skewing switching edges. Synchronization has the added benefit of eliminating beat frequencies, as discussed above. Skewing can be accomplished by using a polyphase clock approach, which intentionally delays the time that each DRV switches on PWM edges. The DRV104 is useful for a variety of relay driver applications (see Figures 16 and 17), as well as valve drivers (see Figures 18 and 19). Beat frequencies can be intentionally set up to be outside the measurement base-band to avoid interference in sensitive analog circuits located nearby. For example, with two DRV104 SBVS036A www.ti.com 13 +VS 10 Sync 12 Master/Slave 4 9 8 +5V Master DRV104 +VPS 6 dc pwm dc pwm dc pwm 7 Input 14 Boot 5 On 3 2 Off Delay 1 11 Duty Cycle Osc Freq LOAD 1 470pF GND +VS 10 Sync 12 Master/Slave 4 9 8 Slave DRV104 #2 +VPS 6 7 Input 14 Boot 5 On 3 2 Off Delay 1 11 Duty Cycle Osc Freq LOAD 2 470pF GND … +VS 10 Sync 12 Master/Slave 4 9 8 Slave DRV104 #n +VPS 6 7 Input On Off 14 Boot 5 3 2 Delay Osc Freq 1 11 Duty Cycle 470pF LOAD n GND FIGURE 15. Multichannel DRV104s, Synchronized with One as the Master and the Others as Slaves. 14 DRV104 www.ti.com SBVS036A +12V 5.6kΩ 10µF Fault HLMP-0156 1MΩ 13 CT + 47µF Tantalum 14 8, 9 10 Status OK Flag 1.7V Microsemi SK34MS 3A 40V Schottky + Relay VPS +VS OUT 6, 7 Input 470pF 5 DRV104 316kΩ Delay Adj Duty Cycle Adj 2 Osc Freq Adj 1 3 147kΩ 0.22µF GND 11 CT (µF) TON (s) 47 22 10 4.7 2.2 10 5 2 1 0.5 191kΩ FIGURE 16. Time-Delay Relay Driver. +28V 10µF + 24kΩ 10 Relay 8, 9 +VS DRV104 VPS OUT 14 6, 7 470pF Input 5 3.9kΩ Delay Adj Duty Cycle Adj 2 1 0.1µF 137kΩ Osc Freq Adj GND 11 3 205kΩ Housing FIGURE 17. Remotely-Operated Solenoid Valve or Relay. DRV104 SBVS036A www.ti.com 15 +12V 10µF (1) LOAD 8, 9 10 +VS 14 VPS IRF7476 Input 6, 7 OUT TTLIN DRV104 High = Load On 5 Low = Load Off Duty Cycle Adj Delay Adj 2 12V 70A 1 3kΩ 11 GND Osc Freq Adj CBOOT 3 10MΩ CD F ~ 500Hz NOTE: (1) Flyback diode required for inductive loads: IXYS DSE160-06A. FIGURE 18. High-Power, Low-Side Driver. +8V to +32V 2mA HLMP-Q156 13 Status OK Flag 14 TTL IN High = On Low = Off 10 8, 9 +VS VPS OUT NC 2 NC = No Connection D/A Converter Duty Cycle Adj 1 6, 7 5 DRV104 Delay Adj DATA 10µF + Fault Osc Freq Adj GND CBOOT 11 Microsemi SK34MS 3A 40V Schottky Linear Valve Actuator 3 191kΩ 1.3V ≅ 5% Duty Cycle 3.7V ≅ 95% Duty Cycle FIGURE 19. Linear Valve Driver. 16 DRV104 www.ti.com SBVS036A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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