49% FPO ® PCM1715U Dual Voltage Output CMOS Delta-Sigma DIGITAL-TO-ANALOG CONVERTER With On-Chip Digital Filter FEATURES DESCRIPTION ● DUAL MULTI-LEVEL NOISE SHAPING DAC WITH ON-CHIP DIGITAL FILTER ● HIGH PERFORMANCE: THD+N: 0.0025% (–92dB) typ Dynamic Range: 98dB typ S/N RATIO: 110dB typ ● ANALOG VOLTAGE OUTPUT: VO = 3.2Vp-p ● ON-CHIP ANALOG LOW PASS FILTER ● JITTER TOUGH AND LOW RADIO FREQUENCY INTERFERENCE ENERGY ARCHITECTURE The PCM1715 is a low cost, dual voltage output CMOS digital-to-analog converter. Incorporated into the PCM1715 is a unique multi-level 4th-order deltasigma architecture that eliminates influence from input clock jitter and RF interferance resulting in truly superior performance. ● SYSTEM CLOCK 256fs or 384fs ● ON-CHIP 8X OVERSAMPLING DIGITAL FILTER WITH: Lch/Rch Individual Attentuator Control Digital De-Emphasis (44.1kHz) Analog Output Mode Select ● SINGLE +5V POWER SUPPLY OPERATION ● SMALL 28-PIN SOIC PACKAGE The PCM1715 can be used in a wide variety of consumer audio applications. Its low cost, small size, and single +5V operation make it ideal for portable, automotive, CD players, CD-I, CD-ROM, VIDEOCD, tuners, music instruments, and other digital audio applications. The PCM1715 has individual channel attenuator and analog output mode select function which is suitable for CD-ROM application. The on-chip digital filter of the PCM1715 has –62dB stop band attenuation and ±0.008dB ripple in the pass band. Lch/Rch ATT Control Digital In Input Interface and Attentuator Oversampling Digital Filter Mode Control System Clock 4th-Order Multi-Level DeltaSigma International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1994 Burr-Brown Corporation Lch OUT DAC Low-Pass Filter Output Op Amp Rch OUT • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-1247 Printed in U.S.A. July, 1994 SPECIFICATIONS ELECTRICAL All specifications at +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, SYSCLK = 384fs/256fs, and 16-bit data, unless otherwise noted. PCM1715U PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 16 DIGITAL INPUT Logic Family Input Logic Level (except XTi) VIH VIL Input Logic Current (except XTi) Input Logic Level (XTi) VIH VIL Input Logic Current (XTi) Output Logic Level (CLKO): VOH VOL Output Logic Current (CLKO) Data Format Sampling Frequency System Clock Frequency System Clock Frequency DC ACCURACY Gain Error Gain Mis-Match Channel-To-Channel Bipolar Zero Error Gain Drift Bipolar Gain Drift DYNAMIC PERFORMANCE THD+N at F/S (0dB)(1) THD+N at –60dB(1) Dynamic Range S/N Ratio Channel Separation DIGITAL FILTER PERFORMANCE Pass Band Ripple Stop Band Attenuation Pass Band Stop Band De-emphasis Error ANALOG OUTPUT Voltage Range Load Impedance Center Voltage POWER SUPPLY REQUIREMENTS Voltage Range: +VCC +VDD Supply Current +ICC +IDD Power Dissipation Bits 2.0 0.8 –200 VDC VDC µA 1.4 ±50 VDC VDC µA 3.2 4.5 0.5 ±10 MSB First, Two’s Complement 44.1 16.934 11.2894 384fs 256fs UNITS VDC VDC mA kHz MHz MHz ±5.0 ±5.0 VO = 1/2VCC at Bipolar Zero ±1.0 ±1.0 ±20.0 ±50 ±20 % of FSR % of FSR mV ppm of FSR/°C ppm of FSR/°C fIN = 991Hz fIN = 991Hz EIAJ A-weighted EIAJ A-weighted fIN = 991Hz –92 –36 98 110 94 –88 –32 dB dB dB dB dB ±0.008 dB dB fs fs dB 104 90 –62 0.4535 0.5465 (fs = 44.1kHz) +0.03 fs (0dB) OUT 3.2 Vp-p kΩ V 5 +1/2VCC +4.5 +4.5 +VCC = +V DD = +5.0V +VCC = +V DD = +5.0V TEMPERATURE RANGE Operation Storage –25 –55 +5.0 +5.0 45 225 +5.5 +5.5 70 350 VDC VDC mA mW +85 +100 °C °C NOTE: (1) 30kHz LPF, 400Hz HPF, Average Mode. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1715U 2 PIN CONFIGURATION LRCIN 1 DIN 2 BCKIN 3 CLKO 4 XTI 5 XTO 6 DGND 7 VDD 8 Input Interface Digital Filter Mode Control Timing Control Noise Shaper 5-Level DAC Left 5-Level DAC Right 28 ML 27 MC 26 MD 25 RSTB 24 NC 23 CKSL 22 DGND 21 VDD 20 VCC2L 19 AGND2L 18 EXT1L 17 EXT2L VCC2R 9 AGND2R 10 EXT1R 11 EXT2R 12 VOUTR 13 16 VOUTL AGND1 14 15 VCC1 Low-Pass Filter-Left CMOS Amp Left PIN ASSIGNMENTS PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LRCIN DIN BCKIN CLKO XTI XTO DGND VDD VCC2R AGND2R EXT1R EXT2R VOUTR AGND FUNCTION PIN NAME Sample Rate Clock Input (fs) Data Input Bit Clock Input Buffered Output of Oscillator Oscillator Input (External Clock Input) Oscillator Output Digital Ground Digital Power Supply (+5V) Analog (DAC) +VCC, Rch Analog (DAC) Ground, Rch Output Amp Common, Rch Output Amp Bias, Rch Rch Analog Output Analog Ground 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC1 VOUTL EXT2L EXT1L AGND2L VCC2L VDD DGND CKSL NC RSTB MD MC ML FUNCTION Analog Power Supply (+5V) Lch Analog Output Output Amp Bias, Lch Output Amp Common, Lch Analog (DAC) Ground, Lch Analog (DAC) +VCC, Lch Digital Power Supply, (+5V) Digital Ground System Clock Select (H:384fs, L:256fs) No Connection Reset Mode Control Mode Control, BCK Mode Control, WDCK NOTE: All input pins require pull up resistors. ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION(1) Power Supply Voltage .................................................................. ±6.5VDC +VCC to VDD Voltage ........................................................................... ±0.1V Input Logic Voltage ....................................................... –0.3V ~ VDD +0.3V Power Dissipation .......................................................................... 400mW Operating Temperature ..................................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C MODEL PCM1715U PACKAGE PACKAGE DRAWING NUMBER 28-Pin SOIC 217-4J NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® 3 PCM1715U CONNECTION DIAGRAM 1 Serial Data Input 28 Input Interface 2 Digital Filter 3 26 Timing Control 4 10pF ~ 22pF x 2 25 5 24 Noise Shaper 6 23 7 (1) 22 8 5-Level DAC Right 5-Level DAC Left Low-Pass Filter Right Low-Pass Filter Left 20 10 10µF + DAC Rch OUT (1) 10µF 18 CMOS Amp Left CMOS Amp Right (1) 19 11 12 NOTE: (1) Bipass Capacitor :1µF ~ 10µF. 21 9 (1) Mode Control 27 Mode Control 17 13 16 14 15 + DAC Lch OUT (1) +5V Power Supply 10kΩ 10kΩ 1500pF 10kΩ 680pF Rch OUT 10kΩ 100pF 10kΩ 1500pF 10kΩ 680pF 3rd ORDER LPF Lch OUT 100pF 3rd ORDER LPF TYPICAL PERFORMANCE CURVES All specifications at +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, SYSCLK = 384fs/256fs, and 16-bit data, unless otherwise noted. THD+N vs SUPPLY VOLTAGE (Full Scale Output) THD+N vs TEMPERATURE (Full Scale Output) 0.005 0.005 TA = +25°C, fIN = 991Hz VCC = VDD = +5.0V, fIN = 991Hz 0.004 THD+N (%) THD+N (%) 0.004 0.003 256fs 0.002 +85°C 0.003 256fs 0.002 384fs 384fs 0.001 0.001 –25 0 25 50 75 4.5 100 ® PCM1715U 5.0 VCC = VDD (V) Temperaure (°C) 4 5.5 TYPICAL PERFORMANCE CURVES (CONT) All specifications at +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, SYSCLK = 384fs/256fs, and 16-bit data, unless otherwise noted. PASSBAND RIPPLE FREQUENCY CHARACTERISTIC (De-Emphasis: OFF) OVERALL FREQUENCY CHARACTERISTIC (De-Emphasis: OFF) –0.03 0 –20 –0.035 –60 dB dB –40 –0.04 –80 –100 –0.045 –120 –0.05 –140 0 20 40 60 80 100 120 140 160 0 5 10 15 Frequency (kHz) Frequency (kHz) DE-EMPHASIS CHARACTERISTIC SIMULATED ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 20 1.0 0 –2 0.5 dB dB –4 –6 0 –8 –0.5 –10 –1.0 –12 0 10k 20k 30k 40k 20 50k Frequency (Hz) dB SIMULATED ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 100 1k Frequency (Hz) 10k 24k OUTPUT WAVE FORM FULL SCALE SIGNAL (Without External Filter) 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M NOTES: (1) Measured at VOUT Pin (Pin 13 or 16). (2) The PCM1715 has internal analog low pass filter to reduce high frequency noise-shaped spectrum. Application of the PCM1715 requires external post analog low pass filter which has 2nd-Order or 3rd-Order attenuation performance to get low noise analog output. 10M Frequency (Hz) ® 5 PCM1715U THEORY OF DELTA-SIGMA OPERATION A block diagram of the 4th-order filter section Hf(z) in the delta-sigma modulator is shown in Figure 2. In general, high order 1-bit delta-sigma modulators have disadvantages due to loop instability. The 5 level deltasigma modulator of the PCM1715 uses phase compensation techniques to obtain stable operation. In Figure 2, the coefficients, b1 to b4, give the basic form of the filter and –a1 and –a2 are used for phase compensation of the feedback loop. The theoretical quantization noise performance of the 5level delta-sigma modulator is shown in Figures 3 and 4. In the audio band, the quantization noise floor level of the PCM1715 is less than –130dB (384fs). The delta-sigma section of the PCM1715 is based on a 5level amplitude quantizer and a 4th-order filter. This converts the oversampled 16-bit input data to 5-level deltasigma form. A block diagram of the 5-level modulator is shown in Figure 1. 5-level Quantizer 4 + In Out 3 2 8fs/ 16 bits Hf(Z) – 1 + 0 + MODE OF OPERATION 32fs/48fs 5-level Serial inputs to MD, MC, and ML (Pins 26, 27 and 28) control the following functions: (1) Digital Attenuator [AL0 ~ AL7, AR0 ~ AR7] Attenuation data is constructed by 8-bit/Lch, 8-bit/Rch (total 16-bit), can be controlled as 255 step attenuation by individual channel. AL0 and AR0 are LSB, and AL7 and AR7 are MSB. Attenuation Level ATT is given by: FIGURE 1. Block Diagram of 5-Level Delta-Sigma Quantizer. This 5-level delta-sigma modulator has the advantage of stability of delta-sigma loop and jitter sensitivity over the typical 1-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8x oversampling digital filter is 48fs at a system clock speed of 384fs, 32fs at a system clock speed of 256fs. ATT = 20LOG10 (ATT DATA/255) [dB] In b4 b3 + b2 + + Z–1 b1 + Z–1 + + Z–1 + Z–1 + Out –a1 –a2 0 0 –100 –100 (dB) (dB) FIGURE 2. Block Diagram of the Hf(z). –120 –120 –140 –140 –160 –160 0 5 10 15 0 20 FIGURE 3. Quantization Noise Spectrum (256fs). 10 15 FIGURE 4. Quantization Noise Spectrum (384fs). ® PCM1715U 5 Frequency (kHz) Frequency (kHz) 6 20 At ATT DATA: 0XFF, output is 0dB. At ATT DATA 0X00, output is –∞. When “Muting” is chosen by output mode control, output goes to –∞ from the present ATT level. Moving speed from 0dB to –∞ is 1024/f. Initialized (RESET) ATT level is 0dB. (2) Versatile Output Mode [PL0 ~ PL3] By using PL0 ~ PL3 data, up to 16 different output modes (Lch/Rch/L+R/MUTE) can be selected to the output of Lch and Rch, as shown in Table I. Initialized mode is STEREO mode. (3) De-emphasis Control (DEM) De-emphasis function is controlled by DEM flag (H: ON, L: OFF) De-emphasis is enabled only at 44.1kHzfs. At other fs frequencies, de-emphasis error is not guaranteed. Initialized mode is De-emphasis OFF. PL0 PL1 PL2 PL3 Lch OUTPUT Rch OUTPUT NOTE 0 0 0 0 MUTE MUTE MUTE 0 0 0 1 MUTE R 0 0 1 0 MUTE L 0 0 1 1 MUTE (L + R)/2 0 1 0 0 R MUTE 0 1 0 1 R R 0 1 1 0 R L 0 1 1 1 R (L + R)/2 1 0 0 0 L MUTE 1 0 0 1 L R 1 0 1 0 L L 1 0 1 1 L (L + R)/2 1 1 0 0 (L + R)/2 MUTE 1 1 0 1 (L + R)/2 R 1 1 1 0 (L + R)/2 L 1 1 1 1 (L + R)/2 (L + R)/2 REVERSE STEREO MONO TABLE I. PCM1715 Output Mode Control. data is continuously “zero” for 8192 cycles of the bit clock, the infinity zero detect occurs and the DAC outputs are set to bipolar zero (1/2VCC). (6) Reset Normally, internal initialize (reset) is done automatically at power on (VDD > 3.5V). The RSTB-pin (Pin 25) accepts external forced reset by RSTB=L. During RSTB=L, the output of the DAC is invalid, set to 1/2VCC after internal initialize (1024XTI clock count after RSTB=H). (4) Attenuator Control (ATC) If common attenuator control of Lch and Rch is needed, use the ATC flag (ATC = “H”). Common attenuation can be controlled by Lch (AL0 ~ AL7) data. Initialized mode is individual. (5) Infinity-Zero Detection The PCM1715 has an infinity-zero detect function which monitors the input data and bit clock. When the input MODE CONTROL FORMAT MC MD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AL0 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 PL0 PL1 PL2 PL3 DEM ATC LSB MSB LSB MSB ML ® 7 PCM1715U 1 f/s Left-channel Data Right-channel Data MSB DIN 1 2 14 LSB MSB 16 1 15 LSB 2 14 15 16 BCKIN LRCIN FIGURE 5. Data Input Timing, 16-Bit. MC BCKIN tBCWH tMCWH tBCWL tMCWL tMCY tBCY MD DIN tDH tDS tBL tLB tMH tMS tMCS tMCH ML LRCIN tMLY FIGURE 6. Data Input Timing. BCK Pulsewidth (H Level) BCK Pulsewidth (L Level BCK Pulse Cycle Time DIN Setup Time DIN Hold Time BCK Rising Edge ➝ LRCI Edge LRCI Edge ➝ BCK Rising Edge FIGURE 7. Serial Mode Control Timing. tBCWH tBCWL tBCY tDS tDH tBL tLB MC Pulsewidth (H Level) MC Pulsewidth (L Level) MC Pulse Cycle Time MD Setup Time MD Hold Time ML Setup Time ML Hold Time ML Low-Level Time 70ns (min) 70ns (min) 140ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) TABLE II. Data Input Timing Specifications. 50ns (min) 50ns (min) 100ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) 1/sysclk + 20ns (min) TABLE III. Serial Mode Control Timing Specifications. ® PCM1715U tMCWH tMCWL tMCY tMS tMH tMCS tMCH tMLY 8 TH VIH VIIL TL NOTE: External system clock inputs to XTI should meet the following conditions: VIH > 0.64VDD VIL < 0.28VDD TH > 10ns TL > 10ns FIGURE 8. Operation Instruction For System Clock. Internal System Clock CLKO (XTI) XTI Internal System Clock XTO CLKO (XTI) XTI XTO(1) Crystal C1 C2 External System Clock Input C1, C2: 10pF ~ 20pF NOTE: (1) XTO must be open. FIGURE 10. Oscillator Circuit Connection Diagram. External system clock. FIGURE 9. Oscillator Circuit Connection Diagram. Optional external crystal oscillator. EVALUATION BOARD Burr-Brown’s DEM-PCM1710 evaluation board for the PCM1710 is capable of evalution of the PCM1715 and PCM1710. Digital input signals for the evaluation board are LRCK, BCK, DATA, and system clock (256fs or 384fs). Power supply requirement is only +5V. The DEM-PCM1710 has a pattern layout for an optional crystal oscillator. However, the crystal is not installed. ® 9 PCM1715U