® PCM PCM3006 300 6 16-Bit, Single-Ended Analog Input/Output STEREO AUDIO CODEC TM FEATURES DESCRIPTION ● MONOLITHIC 16-BIT ∆Σ ADC AND DAC The PCM3006 is a low cost single chip stereo audio CODEC (analog-to-digital and digital-to-analog converters) with single-ended analog voltage input and output. ● STEREO ADC: Single-Ended Voltage Input 64 X Oversampling High Performance THD+N: –84dB SNR: 89dB Dynamic Range: 89dB Digital High Pass Filter ● STEREO DAC: Single-Ended Voltage Output Analog Low Pass Filter 8X Oversampling Digital Filter High Performance THD+N: –85dB SNR: 93dB Dynamic Range: 93dB ● SPECIAL FEATURES Digital De-emphasis Power Down: ADC/DAC Independent ● SAMPLING RATE: Up to 48kHz Both ADCs and DACs employ delta-sigma modulation with 64X oversampling. The ADCs include a digital decimation filter, and the DACs include an 8X oversampling digital interpolation filter. The DACs also include a de-emphasis function. PCM3006 operates with 16-bit, left-justified for ADC, right-justified for DAC data formats. PCM3006 provides a Power-Down Mode that operates on the ADCs and DACs independently. Fabricated on a highly advanced 0.6µs CMOS process, PCM3006 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. Applications include sampling keyboards, digital mixers, effects processors, hard-disk recorders, data recorders and digital video cameras. ● SYSTEM CLOCK: 256fS, 384fS, 512fS ● SINGLE +3V POWER SUPPLY ● SMALL PACKAGE: 24-Lead TSSOP Lch In Analog Front-End Rch In Lch Out Rch Out Low Pass Filter and Output Buffer Delta-Sigma Modulator Multi-Level Delta-Sigma Modulator Digital Out Decimation Digital Filter Oversampling Interpolation Digital Filter Serial Interface and Mode Control Digital In Parallel Mode Control System Clock International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1998 Burr-Brown Corporation PDS-1436A 1 PCM3006 Printed in U.S.A. February, 1998 SPECIFICATIONS All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384f S, and 16-bit data, unless otherwise noted. PCM3006T PARAMETER CONDITIONS MIN DIGITAL INPUT/OUTPUT Input Logic Input Logic Level: VIH(1) VIL(1) Input Logic Current: IIN(2) Input Logic Current: IIN(3) Output Logic Output Logic Level: VOH(4) VOL(4) CLOCK FREQUENCY Sampling Frequency (fS) System Clock Frequency TYP MAX UNITS 0.3 x VDD ±1 100 VDC VDC µA µA 0.3 VDC VDC 48 12.2880 18.4320 24.5760 kHz MHz MHz MHz 0.7 x VDD IOUT = –1mA IOUT = +1mA VDD –0.3 32 8.1920 12.2880 16.3840 256fS 384fS 512fS 44.1 11.2896 16.9344 22.5792 ADC CHARACTERISTICS RESOLUTION 16 DC ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift DYNAMIC PERFORMANCE(5) THD+N: VIN = –0.5dB VIN = –60dB Dynamic Range Signal-to-Noise Ratio Channel Separation DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time HPF Frequency Response ANALOG INPUT Voltage Range Center Voltage Input Impedance Anti-Aliasing Filter Frequency Response High-Pass Filter Disabled(6) High-Pass Filter Disabled(6) A-Weighted A-Weighted 84 84 82 Bits ±1.0 ±2.0 ±20 ±1.7 ±20 ±3.0 ±5.0 % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C –84 –26 89 89 86 –77 dB dB dB dB dB 0.454fS –3dB 17.4/fS 0.019fS Hz Hz dB dB sec mHz –3dB 0.60 VCC 0.50 VCC 30 150 Vp-p V kΩ kHz 16 Bits 0.583fS ±0.05 –65 DAC CHARACTERISTICS RESOLUTION DC ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift ±1.0 ±1.0 ±20 ±2.5 ±20 ±3 ±5 % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C DYNAMIC PERFORMANCE(6) THD+N: VOUT = 0dB (Full Scale) VOUT = –60dB Dynamic Range Signal-to-Noise Ratio Channel Separation –85 –30 93 93 90 –77 dB dB dB dB dB EIAJ, A-Weighted EIAJ, A-Weighted 86 86 84 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM3006 2 SPECIFICATIONS (CONT) All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 16-bit data, unless otherwise noted. PCM3006T PARAMETER CONDITIONS MIN TYP MAX UNITS 0.445fS Hz Hz dB dB sec DAC CHARACTERISTICS (CONT) DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time ANALOG OUTPUT Voltage Range Center Voltage Load Impedance LPF Frequency Response POWER SUPPLY REQUIREMENTS Voltage Range: VCC, VDD Supply Current: ADC/DAC Operation ADC Operation DAC Operation ADC/DAC Power-Down(8) Power Dissipation: ADC/DAC Operation ADC Operation DAC Operation ADC/DAC Power-Down(8) 0.555fS ±0.17 –35 11.1/fS 0.6 x V CC 0.5 x V CC AC-Coupling f = 20kHz 10 –25°C to +85°C 0° C to +70°C(7) VCC = VDD = 3.0V VCC = VDD = 3.0V VCC = VDD = 3.0V VCC = VDD = 3.0V VCC = VDD = 3.0V VCC = VDD = 3.0V VCC = VDD = 3.0V VCC = VDD = 3.0V 2.7 2.4 Vp-p VDC kΩ dB –0.16 TEMPERATURE RANGE Operation Storage Thermal Resistance, ΘJA 3.0 3.0 18 12 7 50 54 36 21 150 –25 –55 3.6 3.6 24 16 10 72 48 30 +85 +125 100 VDC VDC mA mA mA µA mW mW mW µW °C °C °C/W NOTES: (1) Pins 7, 8, 9, 10, 11, 15, 17, 18: PDAD, PDDA, SYSCLK, LRCIN, BCKIN, DIN, DEM1, DEM0 (Schmitt-Trigger input with 100kΩ typical internal pulldown resistor). (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-Trigger input). (3) Pins 7, 8, 17, 18: PDAD, PDDA, DEM1, DEM0 (Schmitt-Trigger input, 100kΩ typical internal pull-down resistor). (4) Pin 12: DOUT. (5) fIN = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (6) fOUT = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (7) Applies for voltages between 2.4V to 2.7V for 0°C to +70°C and 256fS /512fS operation (384fS not available). (8) SYSCLK, BCKIN, and LRCIN are stopped. ® 3 PCM3006 PIN ASSIGNMENTS PIN CONFIGURATION Top View TSSOP PIN PCM3006 1 VCC2 24 VCC1 2 VCC1 NC 23 3 VINR AGND 22 4 NAME I/O DESCRIPTION 1 VCC1 — ADC Analog Power Supply 2 VCC1 — ADC Analog Power Supply 3 VINR IN ADC Analog Input, Rch 4 VREF1 — ADC Reference, 1 5 VREF2 — ADC Reference, 2 6 VINL IN ADC Analog Input, Lch 7 PDAD IN ADC Power Down, Active LOW(1, 2) 8 PDDA IN DAC Power Down, Active LOW(1, 2) 9 SYSCLK IN System Clock Input(2) IN Sample Rate Clock Input (fS)(2) Bit Clock Input(2) VREF1 VCOM 21 5 VREF2 VOUTR 20 10 LRCIN 6 VINL VOUTL 19 11 BCKIN IN 12 DOUT OUT 7 PDAD DEM0 18 13 DGND — 8 PDDA DEM1 17 14 VDD — Digital Power Supply 15 DIN IN Data Input 9 SYSCLK NC 16 10 LRCIN DIN 15 11 BCKIN VDD 14 12 DOUT DGND 13 NC = No Connection Data Output Digital Ground 16 NC IN No Connection 17 DEM1 IN De-emphasis Control(1, 2) 18 DEM0 IN De-emphasis Control 0(1, 2) 19 VOUTL OUT DAC Analog Output, Lch 20 VOUTR OUT DAC Analog Output, Rch 21 VCOM — 22 AGND — Analog Ground 23 NC — No Connection 24 VCC2 — DAC Analog Power Supply ADC/DAC Common NOTES: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger input. ABSOLUTE MAXIMUM RATINGS Supply Voltage +VDD, +VCC1, +VCC2 ...................................................................... +6.5V Supply Voltage Differences ............................................................... ±0.1V GND Voltage Differences .................................................................. ±0.1V Digital Input Voltage ...................................................... –0.3 to VDD + 0.3V Analog Input Voltage ......................................... –0.3 to VCC1, VCC2 + 0.3V Power Dissipation .......................................................................... 300mW Input Current ................................................................................... ±10mA Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C (reflow, 10s) ..................................................... +235°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) PCM3006T 24-Lead TSSOP 350 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® PCM3006 4 TYPICAL PERFORMANCE CURVES ADC SECTION At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and fSIGNAL = 1kHz, unless otherwise noted. DYNAMIC RANGE and SNR vs TEMPERATURE THD+N vs TEMPERATURE 0.010 6.0 92 5.0 90 92 4.0 0.004 3.0 50 75 85 86 86 100 84 0 25 THD+N vs SUPPLY VOLTAGE 6.0 92 0.008 5.0 90 0.006 4.0 Dynamic Range 0.002 Dynamic Range (dB) 3.0 THD+N at –60dB (%) THD+N at –0.5dB (%) –0.5dB 2.0 3.0 3.3 90 88 86 86 84 3.6 84 2.4 2.7 THD+N vs SAMPLING FREQUENCY 3.3 3.6 92 4.0 90 3.0 –0.5dB 0.004 2.0 0.002 1.0 Dynamic Range (dB) 0.006 DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY 5.0 THD+N at –60dB (%) THD+N at –0.5dB (%) –60dB 44.1 3.0 Supply Voltage (V) 0.010 32 88 SNR Supply Voltage (V) 0.008 100 92 –60dB 2.7 85 DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 0.010 2.4 75 Temperature (°C) Temperature (°C) 0.004 50 SNR (dB) 25 88 84 –25 2.0 0 SNR 88 92 90 Dynamic Range 88 88 SNR 86 86 84 48 84 32 fS (kHz) SNR (dB) 0.002 –25 90 SNR (dB) 0.5dB 0.006 Dynamic Range (dB) Dynamic Range THD+N at –60dB (%) THD+N at –0.5dB (%) –60dB 0.008 44.1 48 fS (kHz) ® 5 PCM3006 TYPICAL PERFORMANCE CURVES DAC SECTION At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and fSIGNAL = 1kHz, unless otherwise noted. THD+N vs TEMPERATURE DYNAMIC RANGE and SNR vs TEMPERATURE 0.010 4.0 96 3.0 94 96 –60dB 0.004 1.0 0.002 –25 0 0 25 50 75 85 92 92 SNR 90 88 –25 100 94 SNR (dB) 2.0 FS Dynamic Range (dB) 0.006 THD+N at –60dB (%) THD+N at FS (%) Dynamic Range 0.008 90 88 0 25 Temperature (°C) 50 75 85 100 Temperature (°C) THD+N vs SUPPLY VOLTAGE DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 0.010 4.0 96 3.0 94 96 2.0 FS 0.004 1.0 0.002 0 2.4 2.7 3.0 3.3 Dynamic Range 92 94 92 SNR 90 90 88 3.6 88 2.4 2.7 3.0 3.3 3.6 Supply Voltage (V) Supply Voltage (V) THD+N vs SAMPLING FREQUENCY and SYSTEM CLOCK DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY and SYSTEM CLOCK 0.010 96 4.0 SNR (dB) 0.006 Dynamic Range (dB) 0.008 THD+N at –60dB (%) THD+N at FS (%) –60dB 96 3.0 384fS 256fS, 512fS 2.0 0.004 1.0 0.002 0 32 44.1 SNR 94 92 Dynamic Range 92 384fS 90 90 88 48 88 32 fS (kHz) 44.1 fS (kHz) ® PCM3006 94 6 48 SNR (dB) FS 0.006 384fS 256fS, 512fS Dynamic Range (dB) THD+N at FS (%) –60dB 0.008 THD+N at –60dB (%) 256fS, 512fS TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. ADC DIGITAL FILTER OVERALL CHARACTERISTICS STOPBAND ATTENUATION CHARACTERISTICS 0 0 –10 –20 –30 Amplitude (dB) Amplitude (dB) –50 –100 –40 –50 –60 –70 –150 –80 –90 –200 –100 0 8 16 24 32 0 Normalized Frequency (x fS Hz) 0.2 0.4 0.6 0.8 1.0 Normalized Frequency (x fS Hz) TRANSIENT BAND CHARACTERISTICS PASSBAND RIPPLE CHARACTERISTICS 0.2 0 –1 –2 –0.2 Amplitude (dB) Amplitude (dB) 0.0 –0.4 –0.6 –4.13dB at 0.5 x fS –3 –4 –5 –6 –7 –8 –0.8 –9 –1.0 –10 0 0.1 0.2 0.3 0.4 0.5 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 Normalized Frequency (x fS Hz) Normalized Frequency (x fS Hz) HIGH PASS FILTER RESPONSE HIGH PASS FILTER RESPONSE 0 0.2 –10 0.0 –30 Amplitude (dB) Amplitude (dB) –20 –40 –50 –60 –70 –80 –0.2 –0.4 –0.6 –0.8 –90 –1.0 –100 0 0.1 0.2 0.3 0.4 0.5 0 Normalized Frequency (x fS /1000 Hz) 1 2 3 4 Normalized Frequency (x fS /1000 Hz) ® 7 PCM3006 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. ANTI-ALIASING FILTER ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE ANTI-ALIASING FILTER OVERALL FREQUENCY RESPONSE 0.2 0 0.0 Amplitude (dB) Amplitude (dB) –10 –20 –30 –40 –0.2 –0.4 –0.6 –0.8 –1.0 –50 0 10 100 1k 10k 100k 1M 0 10M ® PCM3006 10 100 1k Frequency (Hz) Frequency (Hz) 8 10k 100k TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. DAC DIGITAL FILTER PASSBAND RIPPLE CHARACTERISTICS (fS = 44.1kHz) 0 0 –20 –0.2 Level (dB) Level (dB) OVERALL FREQUENCY CHARACTERISTICS (fS = 44.1kHz) –40 –60 –0.4 –0.6 –80 –0.8 –100 –1.0 0 50k 100k Frequency (Hz) 150k 0 5k 5k 10k 15k 20k 25k 0 3628 15k 20k 25k 0 4999.8375 19999.35 20k 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 25k 5442 10884 16326 21768 Frequency (Hz) Frequency (Hz) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1Hz~20kHz) 20 0.15 0 0.10 –20 0.05 Level (dB) Level (dB) 15k 14999.5125 DE-EMPHASIS ERROR (48kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 10k 9999.675 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 14512 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 10884 DE-EMPHASIS ERROR (44.1kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 10k 7256 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 20k 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 15k DE-EMPHASIS ERROR (32kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (32kHz) 0 –2 –4 –6 –8 –10 –12 0 10k Frequency (Hz) –40 0 –60 –0.05 –80 –0.10 –100 –0.15 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) ® 9 PCM3006 BLOCK DIAGRAM (+) Analog Front-End Circuit VINL Decimation and High Pass Filter Delta-Sigma Modulator (–) LRCIN BCKIN VREF1 ADC Reference VCOM VREF2 Serial Data Interface DIN (–) Analog Front-End Circuit VINR Decimation and High Pass Filter Multi-Level Delta-Sigma Modulator Interpolation Filter 8X Oversampling (+) Analog Low-Pass Filter VOUTL Delta-Sigma Modulator DOUT Mode Control Interface DAC Analog Low-Pass Filter VOUTR Multi-Level Delta-Sigma Modulator Power Supply 1.0µF VINR + AGND VCC1 Clock DGND VDD SYSCLK 30kΩ 1 (+) (–) VCOM VREF1 + 4.7µF + VREF2 21 4 5 4.7µF VREF + 4.7µF FIGURE 1. Analog Front-End (Single-Channel). ® PCM3006 DEM1 Interpolation Filter 8X Oversampling Reset and Power Down VCC2 DEM0 10 Delta-Sigma Modulator PDAD PDDA PCM AUDIO INTERFACE The four-wire digital audio interface for PCM3006 is comprised of: LRCIN (pin 10), BCKIN (pin 11), DIN (pin 15), and DOUT (pin 12). PCM3006 accepts 16-bit Most Significant Bit (MSB) First. Figures 2 and 3 illustrate audio data input/output format and timing. PCM3006 can accept 32-, 48-, or 64-bit clocks (BCKIN) in one clock of LRCIN. FORMAT 0: PCM3006 DAC: 16-Bit, MSB-First, Right-Justified L–ch LRCIN R–ch BCKIN DIN 16 1 2 3 14 15 16 MSB 1 LSB 2 3 14 15 16 MSB LSB ADC: 16-Bit, MSB-First, Left-Justified LRCIN L–ch R–ch BCKIN DOUT 1 2 3 14 15 16 MSB 1 LSB 2 3 14 15 16 MSB 1 LSB FIGURE 2. Audio Data Input/Output Format. tLRP 0.5VDD LRCIN tBL tBCH tLB tBCL 0.5VDD BCKIN tBCY tDIS tDIH 0.5VDD DIN tLDO tBDO DOUT 0.5VDD BCKIN Pulse Cycle Time tBCY 300ns (min) BCKIN Pulse Width High tBCH 120ns (min) BCKIN Pulse Width Low tBCL 120ns (min) BCKIN Rising Edge to LRCIN Edge tBL 40ns (min) LRCIN Edge to BCKIN Rising Edge tLB 40ns (min) LRCIN Pulse Width tLRP tBCY (min) DIN Set-up Time tDIS 40ns (min) DIN Hold Time tDIH 40ns (min) DOUT Delay Time to BCKIN Falling Edge tBDO 40ns (max) DOUT Delay Time to LRCIN Edge tLDO 40ns (max) Rising Time of All Signals tRISE 20ns (max) Falling Time of All Signals tFALL 20ns (max) FIGURE 3. Audio Data Input/Output Timing. ® 11 PCM3006 SYSTEM CLOCK SAMPLING RATE FREQUENCY (kHz) The system clock for PCM3006 must be either 256fS, 384fS or 512fS, where fS is the audio sampling frequency. The system clock should be provided to SYSCLK (pin 9). 32 PCM3006 also has a system clock detection circuit which automatically senses if the system clock is operating at 256fS, 384fS, or 512fS. When 384fS or 512fS system clock is used, the clock is divded into 256fS automatically. The 256fS clock is used to operate the digital filter and the delta-sigma modulator. 0.3VDD tSCKL 1/256fS,1/384fS,or 1/512fS System Clock Pulse Width High tSCKH 12ns(min) System Clock Pulse Width Low tSCKL 12ns(min) 512fS 16.3840 44.1 11.2896 16.9340 22.5792 48 12.2880 18.4320 24.5760 PCM3006 has an internal Power-On Reset circuit, as well as an external forced reset. The internal Power-On Reset initializes (resets) when the supply voltage VDD >2.0V (typ). External forced reset occurs when PDAD = LOW or PDDA = LOW. Figure 5 shows the internal Power-On reset timing and Figure 6 shows the external forced reset timing by PDAD or PDDA. During external forced reset, the outputs of the DAC are forced to GND (see Figure 7). The analog outputs are then forced to 0.5VCC during tDACDLY1 (16384/fS) after reset removal. The outputs of ADC are also invalid, digital outputs are forced to all zero during tADCDLY1 (18432/fS) after reset removal. 0.7VDD "L" 384fS 12.2880 RESET tSCKH "H" 256fS 8.1920 TABLE I. System Clock Frequencies. Table I lists the relationship of typical sampling frequencies and system clock frequencies and Figure 4 illustrates the system clock timing. SYSCLK SYSTEM CLOCK FREQUENCY (MHz) FIGURE 4. System Clock Timing. VDD 2.4V 2.2V 2.0V Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock FIGURE 5. Internal Power-On Reset Timing. PDAD = LOW and PDDA = LOW Pulse Width tRST = 40ns minimum PDAD and PDDA tRST Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock FIGURE 6. External Forced Reset Timing. ® PCM3006 12 SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM by tDACDLY2 delay time. Internal operation of the ADC will also stop within 1/fS, and the digital output codes will be set to bipolar zero until re-synchronization occurs followed by tADCDLY2 delay time. If LRCIN is synchronized with 5 or less bit clocks to the system clock, operation will be normal. Figures 7 and 8 illustrate the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero (<1/fS seconds), the outputs are not defined and some noise may occur. During the transitions between normal data and undefined states, the output has discontinuities, which will cause output noise. PCM3006 operates with LRCIN synchronized to the system clock. PCM3006 does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization. If the synchronization between the system clock and LRCIN changes more than 6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC will stop within 1/fS, and the analog output will be forced to bipolar zero (0.5VCC) until the system clock is re-synchronized to LRCIN followed Reset Removal or Power Down OFF Internal Reset or Power Down Ready/Operation Reset Power Down DAC VOUT tDACDLY1 (16384/fS) VCOM GND (0.5VCC) tADCDLY1 (18432/fS) Zero ADC DOUT Normal Data(1) Zero NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially. FIGURE 7. DAC Output and ADC Output for Reset and Power Down. Synchronization Lost State of Synchronization Synchronous Resynchronization Asynchronous Synchronous within 1/fS tDACDLY2 (32/fS) Undefined Data DAC VOUT VCOM (= 1/2 x VCC) Normal tADCDLY2 (32/fS) Undefined Data ADC DOUT Normal Normal Zero Normal(1 ) NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially. FIGURE 8. DAC Output and ADC Output for Loss of Synchronization. ® 13 PCM3006 OPERATIONAL CONTROL GROUNDING In order to optimize the dynamic performance of PCM3006, the analog and digital grounds are not connected internally. The PCM3006 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3006 ground pins with low impedance connections to the analog ground plane. PCM3006 should reside entirely over this plane to avoid coupling high frequency digital switching noise into the analog ground plane. PCM3006 has hardwire functional control using PDAD (pin 7) and PDDA (pin 8) for Power-Down Control and DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis. PDAD: ADC Power-Down Control (Pin 7) This pin places the ADC section in the lowest power consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC Power-Down Mode enable. Figure 7 illustrates the ADC DOUT response for ADC power-down ON/OFF. This does not affect the DAC operation. PDDA: PDAD POWER-DOWN Low High ADC Power-Down Mode Enabled ADC Power-Down Mode Disabled VOLTAGE INPUT PINS A tantalum capacitor, between 1µF and 10µF, is recommended as an AC-coupling capacitor at the inputs. Combined with the 30kΩ characteristic input impedance, a 1.0µF coupling capacitor will establish a 5.3Hz cut-off frequency for blocking DC. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 30kΩ input impedance, creates a voltage divider and enables larger input ranges. DAC Power-Down Control (Pin 8) This pin places the DAC section in the lowest power consumption mode. The DAC operation is stopped by cutting the supply current to the DAC section and VOUT is fixed to GND during DAC Power-Down Mode enable. Figure 8 illustrates the DAC VOUT response for DAC Power-Down ON/ OFF. This does not affect the ADC operation. PDDA POWER-DOWN Low High DAC Power-Down Mode Enabled DAC Power-Down Mode Disable VREF Pins A 4.7µF to 10µF tantalum capacitor is recommended between VREF1, VREF2, and AGND to ensure low source impedance for the ADC’s references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference. VCOM Pin A 4.7µF to 10µF tantalum capacitor is recommended between VCOM and AGND to insure low source impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the VCOM pin to reduce dynamic errors on the DAC common. DEM1, 0: DAC De-emphasis Control (Pin 17 and Pin 18) These pins select the de-emphasis mode as shown below: DEM1 DEM0 Low Low High High Low High Low High De-emphasis De-emphasis De-emphasis De-emphasis SYSTEM CLOCK 44.1kHz ON OFF 48kHz ON 32kHz ON The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3006. The duty cycle and jitter at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN) and a word clock (LCRIN) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipation limit is exceeded. APPLICATION AND LAYOUT CONSIDERATIONS POWER SUPPLY BYPASSING The digital and analog power supply lines to PCM3006 should be bypassed to the corresponding ground pins with both 0.1µF ceramic and 10µF tantalum capacitors as close to the device pins as possible. Although PCM3006 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power supply sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems. RST CONTROL If the capacitance between VREF and VCOM exceeds 2.2µF, an external reset control delay time circuit must be used. ® PCM3006 14 EXTERNAL MUTE CONTROL THEORY OF OPERATION Click noises are caused by DC level changes at the DAC output. To avoid any click noises going in and out of PowerDown Mode, an External Mute Control is generally required. The recommended control sequence is as follows: External Mute ON, CODEC Power-Down OFF, and then, External Mute OFF. NOTE: If SYSCLK is stopped when the PCM3006 is in Power-Down Mode, the device is internally reset. ADC SECTION The PCM3006 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential 5th-level delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The Block Diagram in this data sheet illustrates the architecture of the ADC section, Figure 1 shows the single-to-differential converter, and Figure 10 illustrates the architecture of the 5-level delta-sigma modulator and transfer functions. +3V Analog VCC PCM3006 0.1µF and 10µF(1) + 0.1µF and 10µF(1) 1µF(3) + Rch In 4.7µF(2) + 4.7µF(2) + 1µF(3) + Lch In Audio Interface 1 VCC1 VCC2 24 2 VCC1 NC 23 3 VINR AGND 22 4 VREFL VCOM 21 5 VREFR VOUTR 20 6 VINL VOUTL 19 7 PDAD DEM0 18 Lch Out(5) DEM0 DEM1 17 DEM1 8 PDDA SYSCLK 9 SYSCLK L/R CLK 10 LRCIN DIN 15 BIT CLK 11 BCKIN VDD 14 DATA OUT 12 DOUT DGND 13 + 4.7µF(4) + 4.7µF(4) + 4.7µF(4) + Rch Out(5) NC 16 Control Interface 0.1µF and 10µF(1) DATA IN PDDA PDAD NOTES: (1) 0.1µF ceramic and 10µF tantalum, typical, depending on power supply quality and pattern layout. (2) 4.7µF typical, gives settling time with 30ms (4.7µF x 6.4kΩ) time constant in Power ON and Power-Down OFF period. (3) 1µF typical, gives 5.3Hz cut-off frequency of input HPF in normal operation and gives settling time with 30ms (1µF x 30kΩ) time constant in Power ON and Power -Down OFF period. (4) 4.7µF typical, gives 3.4Hz cut-off frequency of output HPF in normal operation and gives settling time with 47ms (4.7µF x 10kΩ) time constant in Power ON and Power-Down OFF period. (5) Post low pass filter with RIN >10kΩ, depending on requirement of system performance. FIGURE 9. Typical Connection Diagram for PCM3006. Analog In X(z) + – – 1st SW-CAP Integrator + – 2nd SW-CAP Integrator 3rd SW-CAP Integrator + + 4th SW-CAP Integrator + Qn(z) + + + 5th SW-CAP Integrator + + + Digital Out Y(z) H(z) Comparator 1-Bit DAC Y(z) = STF(z) • X(z) + NTF(z) • Qn(z) Signal Transfer Function Noise Transfer Function STF(z) = H(z) / [1 + H(z)] NTF(z) = 1/ [1 + H(z)] FIGURE 10. Simplified 5-Level Delta-Sigma Modulator. ® 15 PCM3006 An internal reference circuit with three external capacitors provides all reference voltages which are required by the ADC, which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves the design, space and extra parts needed for external circuitry required by many delta-sigma converters. The internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at 64X oversampling rate, eliminating the need for a sample-andhold circuit, and simplifying anti-alias filtering requirements. The 5-level delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. THEORY OF OPERATION DAC SECTION The delta-sigma DAC section of PCM3006 is based on a 5level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 11. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. The combined oversampling rate of the deltasigma modulator and the internal 8X interpolation filter is 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 12. The 64fS one-bit data stream from the modulator is converted to 1fS 16-bit data words by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. The DC components are removed by a high pass filter function contained within the decimation filter. + + In 8fS 16-Bit + + + Z–1 – + Z–1 – + + + 5-level Quantizer 4 3 Out 2 1 64fS (256fS) 0 FIGURE 11. 5-Level ∆Σ Modulator Block Diagram. Gain (–dB) 5-LEVEL ∆Σ MODULATOR 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 0 5 10 15 Frequency (kHz) FIGURE 12. Quantization Noise Spectrum. ® PCM3006 16 20 25 30 Z–1