BB PCM3003E

PCM3002
PCM3003
®
PCM
300
PCM
3
300
2
For most current data sheet and other product
information, visit www.burr-brown.com
16-/20-Bit Single-Ended Analog Input /Output
STEREO AUDIO CODECs
TM
FEATURES
●
●
●
●
●
●
●
●
●
●
●
DESCRIPTION
MONOLITHIC 20-BIT ∆Σ ADC AND DAC
16-/20-BIT INPUT/OUTPUT DATA
SOFTWARE CONTROL: PCM3002
HARDWARE CONTROL: PCM3003
STEREO ADC:
Single-Ended Voltage Input
64 X Oversampling
High Performance
THD+N: –86dB
SNR: 90dB
Dynamic Range: 90dB
STEREO DAC:
Single-Ended Voltage Output
Analog Low Pass Filter
64X Oversampling
High Performance
THD+N: –86dB
SNR: 94dB
Dynamic Range: 94dB
SPECIAL FEATURES
Digital De-emphasis
Digital Attenuation (256 Steps)
Soft Mute
Digital Loop Back
Power Down: ADC/DAC Independent
SAMPLING RATE: Up to 48kHz
SYSTEM CLOCK: 256fS, 384fS, 512fS
SINGLE +3V POWER SUPPLY
SMALL PACKAGE: SSOP-24
Lch In
Analog Front-End
Rch In
Lch Out
Rch Out
Low Pass Filter
and
Output Buffer
Delta-Sigma
Modulator
Multi-Level
Delta-Sigma
Modulator
The PCM3002 and PCM3003 are low cost single chip
stereo audio CODECs (analog-to-digital and digital-toanalog converters) with single-ended analog voltage
input and output.
The ADCs and DACs employ delta-sigma modulation
with 64X oversampling. The ADCs include a digital
decimation filter, and the DACs include an 8X
oversampling digital interpolation filter. The DACs
also include digital attenuation, de-emphasis, infinite
zero detection and soft mute to form a complete
subsystem. PCM3002 and PCM3003 operate with
left-justified, and right-justified formats, while the
PCM3002 also supports the I2S data format.
PCM3002 and PCM3003 provide a power-down mode
that operates on the ADCs and DACs independently.
Fabricated on a highly advanced CMOS process,
PCM3002 and PCM3003 are suitable for a wide variety of cost-sensitive consumer applications where good
performance is required.
PCM3002’s programmable functions are controlled
by software and the PCM3003’s functions include deemphasis, power down, and audio data format selections, which are controlled by hardware.
Digital
Decimation
Filter
Digital
Interpolation
Filter
Digital Out
Serial Interface
and
Mode Control
Digital In
Serial Mode Control
System Clock
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1997 Burr-Brown Corporation
PDS-1414C
1
Printed in U.S.A. January, 2000
PCM3002/3003
SPECIFICATIONS
All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, and 16-bit data, unless otherwise noted.
PCM3002E/3003E
PARAMETER
CONDITIONS
MIN
DIGITAL INPUT/OUTPUT
Input Logic
Input Logic Level: VIH(1, 2, 3)
VIL(1, 2, 3)
Input Logic Current: IIN(2)
Input Logic Current: IIN(1)
Output Logic
Output Logic Level: VOH(5)
VOL(5)
Output Logic Level: VOL(4)
CLOCK FREQUENCY
Sampling Frequency (fS)
System Clock Frequency
TYP
MAX
UNITS
0.3 x VDD
±1
100
VDC
VDC
µA
µA
0.3
0.3
VDC
VDC
VDC
48
12.2880
18.4320
24.5760
kHz
MHz
MHz
MHz
0.7 x VDD
IOUT = –1mA
IOUT = +1mA
IOUT = +1mA
VDD –0.3
32(7)
8.1920
12.2880
16.3840
256fS
384fS
512fS
44.1
11.2896
16.9344
22.5792
ADC CHARACTERISTICS
RESOLUTION
20
DC ACCURACY
Gain Mismatch Channel-to-Channel
Gain Error
Gain Drift
Bipolar Zero Error
Bipolar Zero Drift
DYNAMIC PERFORMANCE(8)
THD+N: VIN = –0.5dB
VIN = –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
DIGITAL FILTER PERFORMANCE
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
HPF Frequency Response
ANALOG INPUT
Voltage Range
Center Voltage
Input Impedance
Anti-Aliasing Filter Frequency Response
High-Pass Filter Disabled(6)
High-Pass Filter Disabled(6)
A-Weighted
A-Weighted
86
86
84
Bits
±1.0
±2.0
±20
±1.7
±20
±3.0
±5.0
% of FSR
% of FSR
ppm of FSR/°C
% of FSR
ppm of FSR/°C
–86
–28
90
90
88
–80
dB
dB
dB
dB
dB
0.454fS
–3dB
17.4/fS
0.019fS
Hz
Hz
dB
dB
sec
mHz
–3dB
0.60 VCC
0.50 VCC
30
150
Vp-p
V
kΩ
kHz
0.583fS
±0.05
–65
NOTES: (1) Pins 7, 8, 17 and 18: RST, ML, MD, MC for the PCM3002; PDAD, PDDA, DEM1, DEM0 for PCM3003 (Schmitt-Trigger input with 100kΩ typical internal
pull-down resistor). (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt Trigger input). (3) Pin16: 20BIT for PCM3003 (Schmitt-Trigger input, 100kΩ
typical internal pull-down resistor). (4) Pin 12: DOUT. (5) Pin 16: ZFLG (open drain output). (6) High Pass Filter for Offset Cancel. (7) Refer to Application Bulletin
AB-148 for information relating to operation at lower sampling frequencies. (8) fIN = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz
HPF used for performance calculation. (9) fOUT = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation.
(10) Applies for voltages between 2.4V to 2.7V for 0°C to +70°C and 256fS /512fS operation (384fS not available). (11) SYSCLK, BCKIN, and LRCIN are stopped.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.
®
PCM3002/3003
2
SPECIFICATIONS
All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted.
PCM3002E/3003E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC CHARACTERISTICS
RESOLUTION
20
Bits
DC ACCURACY
Gain Mismatch Channel-to-Channel
Gain Error
Gain Drift
Bipolar Zero Error
Bipolar Zero Drift
±1.0
±1.0
±20
±1.0
±20
±3
±5
% of FSR
% of FSR
ppm of FSR/°C
% of FSR
ppm of FSR/°C
DYNAMIC PERFORMANCE(9)
THD+N: VOUT = 0dB (Full Scale)
VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
–86
–28
94
94
91
–80
dB
dB
dB
dB
dB
0.445fS
Hz
Hz
dB
dB
sec
EIAJ, A-Weighted
EIAJ, A-Weighted
88
88
86
DIGITAL FILTER PERFORMANCE
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
0.555fS
±0.17
–35
11.1/fS
ANALOG OUTPUT
Voltage Range
Center Voltage
Load Impedance
LPF Frequency Response
0.60 x VCC
0.5 x VCC
POWER SUPPLY REQUIREMENTS
Voltage Range: VCC, VDD
Supply Current: Operation
Power-Down
Power Dissipation: Operation
Power-Down(11)
AC-Coupling
f = 20kHz
10
–25°C to +85°C
0° C to +70°C(10)
VCC = VDD = 3.0V
VCC = VDD = 3.0V
VCC = VDD = 3.0V
VCC = VDD = 3.0V
2.7
2.4
Vp-p
VDC
kΩ
dB
–0.16
TEMPERATURE RANGE
Operation
Storage
Thermal Resistance, ΘJA
3.0
3.0
18
50
54
150
–25
–55
3.6
3.6
24
72
+85
+125
100
VDC
VDC
mA
µA
mW
µW
°C
°C
°C/W
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM3002E
"
PCM3003E
"
SSOP-24
"
SSOP-24
"
338
"
338
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
–25°C to +85°C
"
–25°C to +85°C
"
PCM3002E
"
PCM3003E
"
PCM3002E
PCM3002E/2K
PCM3003E
PCM3003E/2K
Rails
Tape and Reel
Rails
Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM3002E/2K” will get a single 2000-piece Tape and Reel.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
+VDD, +VCC1, +VCC2 ...................................................................... +6.5V
Supply Voltage Differences ............................................................... ±0.1V
GND Voltage Differences .................................................................. ±0.1V
Digital Input Voltage ...................................................... –0.3 to VDD + 0.3V
Analog Input Voltage ......................................... –0.3 to VCC1, VCC2 + 0.3V
Power Dissipation .......................................................................... 300mW
Input Current ................................................................................... ±10mA
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) .................................................. +260°C
(reflow, 10s) ..................................................... +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
®
3
PCM3002/3003
PIN CONFIGURATION—PCM3002
PIN CONFIGURATION—PCM3003
Top View
SSOP
Top View
SSOP
PCM3002
PCM3003
1
VCC1
VCC2 24
1
VCC1
VCC2 24
2
VCC1
AGND1 23
2
VCC1
AGND1 23
3
VINR
AGND2 22
3
VINR
AGND2 22
4
VREFL
VCOM 21
4
VREFL
VCOM 21
5
VREFR
VOUTR 20
5
VREFR
VOUTR 20
6
VINL
VOUTL 19
6
VINL
VOUTL 19
7
RST
MC 18
7
PDAD
DEM0 18
8
ML
MD 17
8
PDDA
DEM1 17
9
SYSCLK
ZFLG 16
9
SYSCLK
20BIT 16
10
LRCIN
DIN 15
10
LRCIN
DIN 15
11
BCKIN
VDD 14
11
BCKIN
VDD 14
12
DOUT
DGND 13
12
DOUT
DGND 13
PIN ASSIGNMENTS—PCM3002
PIN
PIN ASSIGNMENTS—PCM3003
NAME
I/O
DESCRIPTION
PIN
NAME
I/O
DESCRIPTION
1
VCC1
—
ADC Analog Power Supply
1
VCC1
—
ADC Analog Power Supply
2
VCC1
—
ADC Analog Power Supply
2
VCC1
—
ADC Analog Power Supply
3
VINR
IN
ADC Analog Input, Rch
3
VINR
IN
ADC Analog Input, Rch
4
VREFL
—
ADC Reference, Lch
4
VREFL
—
ADC Reference, Lch
5
VREFR
—
ADC Reference, Rch
5
VREFR
—
ADC Reference, Rch
6
VINL
IN
ADC Analog Input, Lch
6
VINL
IN
ADC Analog Input, Lch
7
RST
IN
Reset, Active LOW(1, 2)
7
PDAD
IN
ADC Power Down, Active LOW(1, 2)
DAC Power Down, Active LOW(1, 2)
Control(1, 2)
8
ML
IN
Strobe Pulse for Mode
8
PDDA
IN
9
SYSCLK
IN
System Clock Input(2)
9
SYSCLK
IN
System Clock Input(2)
10
LRCIN
IN
Sample Rate Clock Input (fS)(2)
10
LRCIN
IN
Sample Rate Clock Input (fS)(2)
11
BCKIN
IN
Bit Clock Input(2)
11
BCKIN
IN
Bit Clock Input(2)
12
DOUT
OUT
Data Output
12
DOUT
OUT
13
DGND
—
Digital Ground
13
DGND
—
14
VDD
—
Digital Power Supply
14
VDD
—
Digital Power Supply
15
DIN
IN
Data Input(2)
15
DIN
IN
Data Input
16
ZFLG
OUT
Zero Flag Output, Active LOW(3)
16
20BIT
IN
20-Bit Format Select(1, 2)
17
MD
IN
Serial Data for Mode Control(1, 2)
17
DEM1
IN
De-emphasis Control(1, 2)
De-emphasis Control 0(1, 2)
Data Output
Digital Ground
18
MC
IN
Bit Clock for Mode Control(1, 2)
18
DEM0
IN
19
VOUTL
OUT
DAC Analog Output, Lch
19
VOUTL
OUT
20
VOUTR
OUT
DAC Analog Output, Rch
20
VOUTR
OUT
21
VCOM
—
ADC/DAC Common
21
VCOM
—
ADC/DAC Common
22
AGND2
—
DAC Analog Ground
22
AGND2
—
DAC Analog Ground
23
AGND1
—
ADC Analog Ground
23
AGND1
—
ADC Analog Ground
24
VCC2
—
DAC Analog Power Supply
24
VCC2
—
DAC Analog Power Supply
NOTES: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger
input. (3) Open drain output.
DAC Analog Output, Rch
NOTE: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger
input.
®
PCM3002/3003
DAC Analog Output, Lch
4
TYPICAL PERFORMANCE CURVES
ADC SECTION
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted.
THD+N vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
0.010
5.0
94
4.0
92
5.0
2.0
0.5dB
0.004
0.002
–25
3.0
1.0
0
25
50
75
85
4.0
SNR
90
88
3.0
86
–25
100
2.0
SNR (dB)
0.006
Dynamic Range (dB)
Dynamic Range
THD+N at –60dB (%)
THD+N at –0.5dB (%)
–60dB
0.008
1.0
0
25
Temperature (°C)
50
75
85
100
Temperature (°C)
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
THD+N vs SUPPLY VOLTAGE
5.0
94
0.008
4.0
92
0.006
3.0
0.010
94
2.0
Dynamic Range
90
90
SNR
88
88
–0.5dB
0.002
86
1.0
2.7
3.0
3.3
86
2.4
3.6
2.7
94
4.0
92
3.0
–0.5dB
0.004
2.0
0.002
Dynamic Range (dB)
0.006
5.0
THD+N at –60dB (%)
–60dB
94
92
Dynamic Range
90
90
SNR
88
88
86
1.0
44.1
3.6
DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY
THD+N vs SAMPLING FREQUENCY
0.010
32
3.3
Supply Voltage (V)
Supply Voltage (V)
0.008
3.0
86
32
48
SNR (dB)
2.4
THD+N at –0.5dB (%)
92
SNR (dB)
Dynamic Range (dB)
0.004
THD+N at –60dB (%)
THD+N at –0.50dB (%)
–60dB
44.1
48
fS (kHz)
fS (kHz)
®
5
PCM3002/3003
TYPICAL PERFORMANCE CURVES
DAC SECTION
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted.
THD+N vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
3.0
0.006
2.0
0dB
0.004
1.0
0.002
–25
Dynamic Range (dB)
–60dB
0.008
98
0
0
25
50
75
85
96
96
Dynamic Range
94
94
SNR
92
90
–25
100
98
SNR (dB)
4.0
THD+N at –60dB (%)
THD+N at FS (%)
0.010
92
90
0
25
Temperature (°C)
50
75
85
100
Temperature (°C)
THD+N vs SUPPLY VOLTAGE
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
0.010
4.0
98
3.0
96
98
0dB
0.004
1.0
0.002
0
2.4
2.7
3.0
3.3
96
Dynamic Range
94
94
SNR
92
92
90
90
2.4
3.6
2.7
3.0
3.3
3.6
Supply Voltage (V)
Supply Voltage (V)
THD+N vs SAMPLING FREQUENCY
and SYSTEM CLOCK
DYNAMIC RANGE and SNR
vs SAMPLING FREQUENCY and SYSTEM CLOCK
0.010
4.0
98
3.0
96
SNR (dB)
2.0
Dynamic Range (dB)
0.006
THD+N at –60dB (%)
THD+N at FS (%)
–60dB
0.008
98
0.006
384fS
256fS, 512fS
0dB
0.004
2.0
1.0
0.002
0
32
44.1
94
94
Dynamic
Range
384fS
92
92
90
48
90
32
fS (kHz)
44.1
fS (kHz)
®
PCM3002/3003
96
SNR
6
48
SNR (dB)
384fS
256fS, 512fS
Dynamic Range (dB)
–60dB
THD+N at –60dB (%)
THD+N at FS (%)
256fS, 512fS
0.008
TYPICAL PERFORMANCE CURVES
Output Spectrum
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted.
DACs
ADCs
OUTPUT SPECTRUM (0dB, N = 8192)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
OUTPUT SPECTRUM (0dB, N = 8192)
–60
–80
–60
–80
–100
–100
–120
–120
–140
–140
0
5
10
15
20 22
25
0
5
10
Frequency (kHz)
20 22
25
OUTPUT SPECTRUM (–60dB, N = 8192)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
OUTPUT SPECTRUM (–60dB, N = 8192)
–60
–80
–60
–80
–100
–100
–120
–120
–140
–140
0
5
10
15
20 22
0
25
5
10
15
20
22
25
–12
0
Frequency (kHz)
Frequency (kHz)
THD+N vs SIGNAL LEVEL
THD+N vs SIGNAL LEVEL
100
100
10
10
THD+N (%)
THD+N (%)
15
Frequency (kHz)
1
0.1
0.001
1
0.1
0.001
0.001
0.001
–96
–84
–72
–60
–48
–36
–24
–12
0
–96
Signal Level (dB)
–84
–72
–60
–48
–36
–24
Signal Level (dB)
®
7
PCM3002/3003
TYPICAL PERFORMANCE CURVES
Supply Current
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, DIN = BPZ, and VIN = BPZ, unless otherwise noted.
ICC + IDD vs TEMPERATURE
ICC + IDD vs SUPPLY VOLTAGE
15
1.5
ADC
10
1.0
DAC
5
0.5
Power Down & OFF
0
–50
–25
–0
25
50
75
2.5
20
2.0
ADC & DAC
15
1.5
10
ADC
1.0
5
DAC
0.5
Power Down & OFF
0
0
0
100
2.4
Temperature (°C)
ICC + IDD vs SAMPLING FREQUENCY
ADC & DAC
512fS
19
18
256fS
17
16
15
32
44.1
fS (kHz)
®
PCM3002/3003
2.7
3.0
3.3
Supply Voltage (V)
20
ICC + IDD (mA)
ICC + IDD (mA)
2.0
ICC + IDD (mA)
ADC & DAC
20
25
8
48
3.6
ICC + IDD: Power Down and OFF (mA)
2.5
ICC + IDD: Power Down and OFF (mA)
25
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted.
ADC DIGITAL FILTER
OVERALL CHARACTERISTICS
STOPBAND ATTENUATION CHARACTERISTICS
0
0
–10
–20
–30
Amplitude (dB)
Amplitude (dB)
–50
–100
–40
–50
–60
–70
–150
–80
–90
–200
–100
0
8
16
24
32
0
Normalized Frequency (x fS Hz)
0.2
0.4
0.6
0.8
1.0
Normalized Frequency (x fS Hz)
TRANSITION BAND CHARACTERISTICS
PASSBAND RIPPLE CHARACTERISTICS
0
0.2
–1
–2
–0.2
Amplitude (dB)
Amplitude (dB)
0.0
–0.4
–0.6
–4.13dB at 0.5 x fS
–3
–4
–5
–6
–7
–8
–0.8
–9
–10
–1.0
0
0.1
0.2
0.3
0.4
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
0.5
Normalized Frequency (x fS Hz)
Normalized Frequency (x fS Hz)
HIGH PASS FILTER RESPONSE
HIGH PASS FILTER RESPONSE
0
0.2
–10
0.0
–30
Amplitude (dB)
Amplitude (dB)
–20
–40
–50
–60
–70
–80
–0.2
–0.4
–0.6
–0.8
–90
–100
–1.0
0
0.1
0.2
0.3
0.4
0
0.5
Normalized Frequency (x fS /1000 Hz)
1
2
3
4
Normalized Frequency (x fS /1000 Hz)
®
9
PCM3002/3003
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted.
ANTI-ALIASING FILTER
ANTI-ALIASING FILTER OVERALL
FREQUENCY RESPONSE
ANTI-ALIASING FILTER PASSBAND
FREQUENCY RESPONSE
0
0.2
0.0
Amplitude (dB)
Amplitude (dB)
–10
–20
–30
–40
–0.2
–0.4
–0.6
–0.8
–50
–1.0
0
10
100
1k
10k
100k
1M
10M
0
Frequency (Hz)
100
1k
Frequency (Hz)
®
PCM3002/3003
10
10
10k
100k
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted.
DAC DIGITAL FILTER
PASSBAND RIPPLE CHARACTERISTICS (fS = 44.1kHz)
0
0
–20
–0.2
Level (dB)
Level (dB)
OVERALL FREQUENCY CHARACTERISTICS
(fS = 44.1kHz)
–40
–60
–0.4
–0.6
–80
–0.8
–100
–1.0
0
50k
100k
Frequency (Hz)
150k
0
5k
5k
10k
15k
20k
25k
0
3628
7256
15k
20k
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
25k
0
4999.8375
Frequency (Hz)
15k
19999.35
20k
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
25k
5442
10884
16326
21768
Frequency (Hz)
Frequency (Hz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(1Hz~20kHz)
20
0.15
0
0.10
–20
0.05
Level (dB)
Level (dB)
10k
14999.5125
DE-EMPHASIS ERROR (48kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
5k
9999.675
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
0
14512
DE-EMPHASIS ERROR (44.1kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
10k
10884
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
5k
20k
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Frequency (Hz)
0
15k
DE-EMPHASIS ERROR (32kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (32kHz)
0
–2
–4
–6
–8
–10
–12
0
10k
Frequency (Hz)
–40
0
–60
–0.05
–80
–0.10
–100
–0.15
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
®
11
PCM3002/3003
BLOCK DIAGRAM
(+)
Analog
Front-End
Circuit
VINL
Decimation
and
High Pass Filter
Delta-Sigma
Modulator
(–)
LRCIN
BCKIN
VREFL
ADC
Reference
VCOM
VREFR
Serial Data
Interface
DIN
(–)
Analog
Front-End
Circuit
VINR
Decimation
and
High Pass Filter
Multi-Level
Delta-Sigma
Modulator
Interpolation
Filter
8X Oversampling
(+)
Analog
Low-Pass
Filter
VOUTL
Delta-Sigma
Modulator
DOUT
MC(1 )/DEM0(2)
Mode
Control
Interface
DAC
Analog
Low-Pass
Filter
VOUTR
Multi-Level
Delta-Sigma
Modulator
MD(1 )/DEM1(2)
ML(1 )
20BIT(2)
Interpolation
Filter
8X Oversampling
Reset and
Power Down
Power Supply
AGND2
VCC2
AGND1
VCC1
DGND
VDD
Clock
Zero Detect(1)
SYSCLK
ZFLG(1)
PDDA(2)
RST(1)/PDAD(2)
NOTES: (1) MC, MD, ML, RST, and ZFLG are for PCM3002 only. (2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.
1.0µF
VINR
+
30kΩ
1
(+)
(–)
VCOM
VREFL
+
4.7µF
+
VREFR
21
4
5
4.7µF
VREF
+
4.7µF
FIGURE 1. Analog Front-End (Single-Channel).
®
PCM3002/3003
12
Delta-Sigma
Modulator
PCM AUDIO INTERFACE
the software mode. For the PCM3003, data formats are
selected by the 20BIT input (pin 16). Figures 2, 3 and 4
illustrate audio data input/output formats and timing.
The PCM3002/3003 can accept 32-, 48-, or 64-bit clocks
(BCKIN) in one clock of LRCIN. Only 16-bit data formats
can be selected when 32-bit clocks/LRCIN are applied.
The four-wire digital audio interface for PCM3002/3003 is
comprised of: LRCIN (pin 10), BCKIN (pin 11), DIN (pin
15), and DOUT (pin 12). The PCM3002 may be used with
any of the four input/output data formats (Formats 0 - 3),
while the PCM3003 may only be used with selected input/
output formats (Formats 0 - 1). For the PCM3002, these
formats are selected through PROGRAM REGISTER 3 in
FORMAT 0: PCM3002/3003
DAC: 16-Bit, MSB-First, Right-Justified
L–ch
LRCIN
R–ch
BCKIN
DIN
16
1
2
3
14 15 16
MSB
1
LSB
2
3
14 15 16
MSB
LSB
ADC: 16-Bit, MSB-First, Left-Justified
LRCIN
L–ch
R–ch
BCKIN
1
DOUT
2
3
14 15 16
MSB
1
LSB
2
3
14 15 16
MSB
1
LSB
FORMAT 1: PCM3002/3003
DAC: 20-Bit, MSB-First, Right-Justified
L–ch
LRCIN
R–ch
BCKIN
DIN
20
1
2
3
18 19 20
MSB
1
LSB
2
3
18 19 20
MSB
LSB
ADC: 20-Bit, MSB-First, Left-Justified
LRCIN
L–ch
R–ch
BCKIN
DOUT
1
2
18 19 20
3
1
LSB
MSB
2
3
18 19 20
1
LSB
MSB
FORMAT 2: PCM3002 Only
DAC: 20-Bit, MSB-First, Left-Justified
L–ch
LRCIN
R–ch
BCIN
DIN
1
2
3
18 19 20
MSB
1
LSB
2
3
18 19 20
MSB
1
LSB
ADC: 20-Bit, MSB-First, Left-Justified
LRCIN
L–ch
R–ch
BCIN
DOUT
1
2
3
MSB
18 19 20
1
LSB
2
MSB
3
18 19 20
1
LSB
FIGURE 2. Audio Data Input/Output Format.
®
13
PCM3002/3003
FORMAT 3: PCM3002 Only
DAC: 20-Bit, MSB-First, I2S
L-ch
LRCIN
R-ch
BCKIN
DIN
1
2
3
18 19 20
MSB
1
2
3
18 19 20
MSB
LSB
LSB
ADC: 20-Bit, MSB-First, I2S
L-ch
LRCIN
R-ch
BCKIN
DOUT
1
2
3
18 19 20
1
LSB
MSB
2
3
18 19 20
MSB
LSB
FIGURE 3. Audio Data Input/Output Format.
tLRP
0.5VDD
LRCIN
tLB
tBL
tBCH
tBCL
0.5VDD
BCKIN
tBCY
tDIS
tDIH
0.5VDD
DIN
tLDO
tBDO
DOUT
0.5VDD
BCKIN Pulse Cycle Time
tBCY
300ns (min)
BCKIN Pulse Width High
tBCH
120ns (min)
BCKIN Pulse Width Low
tBCL
120ns (min)
BCKIN Rising Edge to LRCIN Edge
tBL
40ns (min)
LRCIN Edge to BCKIN Rising Edge
tLB
40ns (min)
LRCIN Pulse Width
tLRP
tBCY (min)
DIN Set-up Time
tDIS
40ns (min)
DIN Hold Time
tDIH
40ns (min)
DOUT Delay Time to BCKIN Falling Edge
tBDO
40ns (max)
DOUT Delay Time to LRCIN Edge
tLDO
40ns (max)
Rising Time of All Signals
tRISE
20ns (max)
Falling Time of All Signals
tFALL
20ns (max)
FIGURE 4. Audio Data Input/Output Timing.
®
PCM3002/3003
14
SYSTEM CLOCK
POWER-ON RESET
Both the PCM3002 and PCM3003 have internal power-on
reset circuitry. Power-on reset occurs when system clock
(SYSCLK) is active and VDD > 2.2V. For the PCM3003, the
SYSCLK must complete a minimum of 3 complete cycles
prior to VDD > 2.2V to ensure proper reset operation. The
initialization sequence requires 1024 SYSCLK cycles for
completion, as shown in Figure 6. Figure 8 shows the state
of the DAC and ADC outputs during and after the reset
sequence.
The system clock for PCM3002/3003 must be either 256fS,
384fS or 512fS, where fS is the audio sampling frequency. The
system clock should be provided at the SYSCLK input (pin 9).
The PCM3002/3003 also has a system clock detection circuit
which automatically senses if the system clock is operating at
256fS, 384fS, or 512fS. When 384fS or 512fS system clock is
used, the clock is divided into 256fS automatically. The 256fS
clock is used to operate the digital filters and the delta-sigma
modulators.
EXTERNAL RESET
The PCM3002 includes a reset input, RST (pin 7), while the
PCM3003 utilizes both PDAD (pin 7) and PDDA (pin 8) for
external reset control. As shown in Figure 7, the external
reset signal must drive RST or PDAD/PDDA low for a
minimum of 40 nanoseconds while SYSCLK is active in
order to initiate the reset sequence. Initialization starts on the
rising edge of RST or PDAD/PDDA, and requires 1024
SYSCLK cycles for completion. Figure 8 shows the state of
the DAC and ADC outputs during and after the reset sequence.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies, while Figure 5 illustrates the
system clock timing.
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
32
256fS
384fS
512fS
8.1920
12.2880
16.3840
44.1
11.2896
16.9340
22.5792
48
12.2880
18.4320
24.5760
TABLE I. System Clock Frequencies.
tSCKH
"H"
0.7V
SYSCLK
0.3VDD
"L"
tSCKL
1/256fS,1/384fS,or 1/512fS
System Clock Pulse Width High
tSCKH
12ns
(min)
System Clock Pulse Width Low
tSCKL
12ns
(min)
FIGURE 5. System Clock Timing.
VDD
2.4V
2.2V
2.0V
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
SYSCLK
FIGURE 6. Internal Power-On Reset Timing.
RST
or
PDAD and PDDA
tRST = 40ns minimum
tRST
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
SYSCLK
FIGURE 7. External Forced Reset Timing.
®
15
PCM3002/3003
SYNCHRONIZATION WITH THE DIGITAL
AUDIO SYSTEM
synchronization occurs followed by tADCDLY2 delay time. If
LRCIN is synchronized with 5 or less bit clocks to the system
clock, operation will be normal. Figure 9 illustrates the effects
on the output when synchronization is lost. Before the outputs
are forced to bipolar zero (<1/fS seconds), the outputs are not
defined and some noise may occur. During the transitions
between normal data and undefined states, the output has
discontinuities, which will cause output noise.
The PCM3002/3003 operates with LRCIN synchronized to
the system clock. PCM3002/3003 does not require any specific phase relationship between LRCIN and the system
clock, but there must be synchronization. If the synchronization between the system clock and LRCIN changes more than
6 bit clocks (BCKIN) during one sample (LRCIN) period
because of phase jitter on LRCIN, internal operation of the
DAC will stop within 1/fS, and the analog output will be
forced to bipolar zero (0.5VCC) until the system clock is resynchronized to LRCIN followed by tDACDLY2 delay time.
Internal operation of the ADC will also stop within 1/fS, and
the digital output codes will be set to bipolar zero until re-
ZERO FLAG OUTPUT: PCM3002 ONLY
Pin 16 is an open-drain output, used as the infinite zero
detection flag on the PCM3002 only. When input data is
continuously zero for 65,536 BCKIN cycles, ZFLG is LOW,
otherwise, ZFLG is in a high-impedance state.
Reset Removal or Power Down OFF
Internal Reset
or Power Down
Ready/Operation
Reset
Power Down
tDACDLY1 (16384/fS)
VCOM
GND
DAC VOUT
(0.5VCC)
tADCDLY1 (18436/fS)
Zero
ADC DOUT
Normal Data(1)
Zero
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 8. DAC Output and ADC Output for Reset and Power Down.
Synchronization
Lost
State of
Synchronization
Synchronous
Resynchronization
Asynchronous
Synchronous
within
1/fS
tDACDLY2 (32/fS)
Undefined Data
DAC VOUT
VCOM
(= 1/2 x VCC)
Normal
tADCDLY2 (32/fS)
Undefined Data
ADC DOUT
Normal
Normal
Zero
Normal(1 )
NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 9. DAC Output and ADC Output for Loss of Synchronization.
®
PCM3002/3003
16
ML
MC
MD
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 10. Control Data Input Format.
tMLH
tMLH
tMLS
ML
tMCH
tMCL
tMLL
MC
tMCY
LSB
MD
tMDS
tMDH
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Setup Time
MD Hold Time
ML Low Level Time
ML High Level Time
ML Setup Time
ML Hold Time
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMLH
tMLS
tMLH
100ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns + 1SYSCLK (min)
40ns + 1SYSCLK (min)
40ns (min)
40ns (min)
SYSCLK: 1/256fS or 1/384fS or 1/512fS
FIGURE 11. Control Data Input Timing.
FUNCTION
ADC/DAC
PCM3002
PCM3003
Audio Data Format
LRCIN Polarity
ADC/DAC
ADC/DAC
4 Selectable Formats
O
2 Selectable Formats
X
Loop-Back Control
ADC/DAC
O
X
DAC
O
X
Left Channel Attenuation
Right Channel Attenuation
DAC
O
X
Attenuation Control
DAC
O
X
Infinite Zero Detection
DAC
O
X
DAC Output Control
DAC
O
X
Soft Mute Control
De-Emphasis (OFF, 32kHz, 44.1kHz, 48kHz)
DAC
DAC
O
O
X
O
ADC Power-Down Control
ADC
O
O
DAC Power-Down Control
DAC
O
O
High Pass Filter Operation
ADC
O
X
TABLE II. Selectable Functions (O = User Selectable; X = Not Available).
OPERATIONAL CONTROL
PCM3002 can be controlled in a software mode with a
three-wire serial interface on MC (pin 18), MD (pin 17), and
ML (pin 8). Table II indicates selectable functions, and
Figure 10 and 11 illustrate the control data input format and
timing. PCM3003 only allows for control of 16-/20-bit data
format, digital de-emphasis, and Power-Down Control by
hardware pins.
®
17
PCM3002/3003
MAPPING OF PROGRAM REGISTERS
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 0
res
res
res
res
res
A1
A0
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
REGISTER 1
res
res
res
res
res
A1
A0
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
REGISTER 2
res
res
res
res
res
A1
A0
PDAD
BYPS
PDDA
ATC
IZD
OUT
DEM1
DEM0
MUT
REGISTER 3
res
res
res
res
res
A1
A0
res
res
res
LOP
res
FMT1
FMT0
LRP
res
SOFTWARE CONTROL (PCM3002)
new attenuation data will be ignored, and the
output level will remain at the previous attenuation level. The LDR bit in REGISTER 1 has the
equivalent function as LDL. When either LDL or
LDR is set to “1”, the output level of the left and
right channels are simultaneously controlled.
PCM3002’s special functions are controlled using four program registers which are 16 bits long. There are four distinct
registers, with bits 9 and 10 determining which register is in
use. Table III describes the functions of the four registers.
AL (7:0): Bit 7:0
REGISTER
NAME
BIT
NAME
Register 0
A (1:0)
res
LDL
AL (7:0)
Register Address “00”
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Lch
Attenuation Data for Lch
Register 1
A (1:0)
res
LDR
AR (7:0)
Register Address “01”
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Rch
DAC Attenuation for Rch
A (1:0)
res
PDAD
PDDA
BYPS
ATC
IZD
OUT
DEM (1:0)
MUT
Register Address “10”
Reserved, should be set to “0”
ADC Power-Down Control
DAC Power-Down Control
ADC High-Pass Filter Operation Control
DAC Attenuation Data Mode Control
DAC Infinite Zero Detection Circuit Control
DAC Output Enable Control
DAC De-emphasis Control
Lch and Rch Soft Mute Control
A (1:0)
res
LOP
FMT (1:0)
LRP
Register Address “11”
Reserved, should be set to “0”
ADC/DAC Analog Loop-Back Control
ADC/DAC Audio Data Format Selection
ADC/DAC Polarity of LR-clock Selection
Register 2
Register 3
DESCRIPTION
ATT = 20 x log10 (ATT data/255) (dB)
res:
0
Register 0
Bit 11 : 15 Reserved
Bit 8 DAC Attenuation Data Load Control for
Left Channel
A0
0
1
Register 1
res:
Bit 15:11
LDR:
Bit 8 DAC Attenuation Data Load Control for
Right Channel
AR (7:0): Bit 7:0
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AL (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
Reserved
DAC Attenuation Data for Left
Channel
AR7 and AR0 are MSB and LSB respectively.
See REGISTER 0 for the attenuation formula.
®
PCM3002/3003
A1
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AL (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
new attenuation data will be ignored, and the
output level will remain at the previous attenuation level. The LDL bit in REGISTER 0 has the
equivalent function as LDR. When either LDL or
LDR is set to “1”, the output level of the left and
right channels are simultaneously controlled.
These bits are reserved and should be set to “0”.
LDL:
–∞dB (Mute)
–48.16dB
:
–0.07dB
0dB (default)
These bits are reserved and should be set to “0”
These bits define the address for REGISTER 0:
0
ATTENUATION LEVEL
00h
01h
:
FEh
FFh
These bits define the address for REGISTER 1:
PROGRAM REGISTER 0
A (1:0): Bit 10, 9
Register Address
A0
AL (7:0)
PROGRAM REGISTER 1
A (1:0): Register Address
TABLE III. Functions of the Registers.
A1
DAC Attenuation Data for Left Channel
AL7 and AL0 are MSB and LSB, respectively.
The attenuation level (ATT) is given by:
18
PROGRAM REGISTER 2
A (1:0): Bit 10, 9
Register Address
IZD:
res:
A0
1
0
Register 2
Bit 15:11, 6 Reserved
IZD
These bits are reserved and should be set to “0”.
PDAD:
Bit 8
ADC Power-Down Control
This bit places the ADC section in the lowest
power consumption mode. The ADC operation is
stopped by cutting the supply current to the ADC
section, and DOUT is fixed to zero during ADC
Power-down mode enable. Figure 8 illustrates the
ADC DOUT response for ADC power-down ON/
OFF. This does not affect the DAC operation.
PDAD
BYPS:
OUT:
0
Infinite Zero Detection Disabled (default)
1
Infinite Zero Detection Enabled
Bit 3
DAC Output Enable Control
When set to “1”, the outputs are forced to VCC/2
(bipolar zero). In this case, all registers in
PCM3002 hold the present data. Therefore, when
set to “0”, the outputs return to the previous
programmed state.
OUT
DAC POWER-DOWN
0
Power Down Mode Disabled (default)
0
DAC Outputs Enabled (default normal operation)
1
Power Down Mode Enabled
1
DAC Outputs Disabled (forced to BPZ)
Bit 7
ADC High-Pass Filter Bypass Control
DEM (1:0):Bit 2,1
BYPS
0
High-Pass Filter Enabled (default)
1
High-Pass Filter Disabled (bypassed)
Bit 6
DAC De-emphasis Control
These bits select the de-emphasis mode as shown
below:
This bit enables or disables the high-pass filter for
the ADC.
PDDA:
DAC Infinite Zero Detection Circuit
Control
This bit enables the Infinite Zero Detection Circuit
in PCM3002. When enabled, this circuit will disconnect the analog output amplifier from the deltasigma DAC when the input is continuously zero for
65,536 consecutive cycles of BCKIN.
These bits define the address for REGISTER 2:
A1
Bit 4
DEM1
DEM0
0
0
1
0
1
0
De-emphasis 44.1kHz ON
De-emphasis OFF (default)
De-emphasis 48kHz ON
1
1
De-emphasis 32kHz ON
DAC Power-Down Control
This bit places the DAC section in the lowest power
consumption mode. The DAC operation is stopped
by cutting the supply current to the DAC section
and VOUT is fixed to GND during DAC PowerDown Mode enable. Figure 8 illustrates the DAC
VOUT response for DAC Power-Down ON/OFF.
This does not affect the ADC operation.
MUT:
Bit 0
DAC Soft Mute Control
When set to “1”, both left and right-channel DAC
outputs are muted at the same time. This muting
is done by attenuating the data in the digital filter,
so there is no audible click noise when soft mute
is turned on.
MUT
PDDA
ATC:
0
Power-Down Mode Disabled (default)
1
Power-Down Mode Enabled
Bit 5
0
1
DAC Attenuation Channel Control
PROGRAM REGISTER 3
A (1:0): Bit 10:9
Register Address
When set to “1”, the REGISTER 0 attenuation
data can be used for both DAC channels. In this
case, the REGISTER 1 attenuation data is ignored.
These bits define the address for REGISTER 3:
ATC
0
Individual Channel Attenuation Data Control (default)
1
Common Channel Attenuation Data Control
Mute Disable (default)
Mute Enable
res:
A1
A0
1
1
Bit 15:11, 8:6, 4:0
Register 3
Reserved
These bits are reserved, and should be set to “0”.
®
19
PCM3002/3003
LOP:
Bit 5
ADC to DAC Loop-Back Control
LRP:
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I2S. In Format 3 (I2S Frame), Loopback is not supported.
Bit 1
Polarity of LRCIN Applies only to
Formats 0 through 2.
LRP
0
1
Left-channel is “H”, Right-channel is “L”. (default)
Left-channel is “L”, Right-channel is “H”.
LOP
0
Loop-back Disable (default)
1
Loop-back Enable
FMT (1,0) Bit 3:2
Audio Data Format Select
These bits determine the input and output audio
data formats.
FMT1
FMT0
DAC
Data Format
ADC
Data Format
NAME
0
0
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Left-justified
Format 0 (default)
0
1
20-bit, MSB-first,
Right-justified
20-bit, MSB-first,
Left-justified
Format 1
1
0
20-bit, MSB-first,
Left-justified
20-bit, MSB-first,
Left-justified
Format 2
1
1
20-bit, MSB-first,
20-bit, MSB-first,
Format 3
I2S
I2S
+3V Analog VCC
PCM3002/3003
0.1µF
and 10µF(1)
+
0.1µF and 10µF(1)
1µF
+
Rch In
4.7µF(2)
+
4.7µF(2)
+
1µF
+
Lch In
Audio
Interface
1
VCC1
VCC2 24
2
VCC1
AGND1 23
3
VINR
AGND2 22
4
VREFL
VCOM 21
5
VREFR
VOUTR 20
6
VINL
7
RST/PDAD
8
ML/PDDA
MD/DEM1
SYSCLK
9
SYSCLK
ZFLG/20BIT 16
L/R CLK
10 LRCIN
DIN 15
BIT CLK
11 BCKIN
VDD 14
DATA OUT
12 DOUT
DGND 13
+
4.7µF(4)
+
4.7µF(4)
+
Rch Out(5)
4.7µF(4)
VOUTL 19
+
Lch Out(5)
MC(6)/DEM0(7)
MC/DEM0 18
MD(6)/DEM1(7)
17
ZFLG(6)/20BIT(7)
10kΩ
Control
Interface
0.1µF
and
10µF(1)
DATA IN
ML(6)/PDDA(7)
RST(6)/PDAD(7)
NOTES: (1) 0.1µF ceramic and 10µF tantalum, typical, depending on power supply quality and
pattern layout. (2) 4.7µF typical, gives settling time with 30ms (4.7µF x 6.4kΩ) time constant in
Power ON and Power-Down OFF period. (3) 1µF typical, gives 5.3Hz cut-off frequency of input
HPF in normal operation and gives settling time with 30ms (1µF x 30kΩ) time constant in Power
ON and Power -Down OFF period. (4) 4.7µF typical, gives 3.4Hz cut-off frequency of output HPF
in normal operation and gives settling time with 47ms (4.7µF x 10kΩ) time constant in Power ON
and Power-Down OFF period. (5) Post low pass filter with RIN >10kΩ, depending on requirement
of system performance. (6) MC, MD, ML, ZFLG, RST and 10kΩ pull-up resistor are for the
PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
FIGURE 12. Typical Connection Diagram for PCM3002/3003.
®
PCM3002/3003
20
PCM3003 DATA FORMAT CONTROL
GROUNDING
PCM3003 has hardware functional control using PDAD (pin
7) and PDDA (pin 8) for Power-Down Control; DEM0 (pin
18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16)
for 16-/20-bit format selection.
In order to optimize the dynamic performance of PCM3002/
3003, the analog and digital grounds are not connected
internally. The PCM3002/3003 performance is optimized
with a single ground plane for all returns. It is recommended
to tie all PCM3002/3003 ground pins with low impedance
connections to the analog ground plane. PCM3002/3003
should reside entirely over this plane to avoid coupling high
frequency digital switching noise into the analog ground
plane.
Power-Down Control (Pin 7 and Pin 8)
Both the ADC’s and DAC’s Power-Down Control pins
place the ADC or DAC section in the lowest power consumption mode. The ADC/DAC operation is stopped by
cutting the supply current to the ADC/DAC section. DOUT
is fixed to zero during ADC Power-Down Mode enable and
VOUT is fixed to GND during DAC Power-Down Mode
enable. Figure 8 illustrates the ADC and DAC output response for Power-Down ON/OFF.
PDAD
PDDA
VOLTAGE INPUT PINS
A tantalum or aluminum electrolytic capacitor, between 1µF
and 10µF, is recommended as an AC-coupling capacitor at
the inputs. Combined with the 30kΩ characteristic input
impedance, a 1.0µF coupling capacitor will establish a 5.3Hz
cut-off frequency for blocking DC. The input voltage range
can be increased by adding a series resistor on the analog
input line. This series resistor, when combined with the 30kΩ
input impedance, creates a voltage divider and enables larger
input ranges.
POWER DOWN
Low
Low
Reset (ADC/DAC Power-Down Enable)
Low
High
ADC Power-Down/DAC Operates
High
Low
ADC Operates/DAC Power-Down
High
High
ADC and DAC Normal Operation
De-Emphasis Control (Pin 17 and Pin 18)
DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis
control pins.
DEM1
DEM0
VREF INPUTS
A 4.7µF to 10µF tantalum capacitor is recommended between VREFL, VREFR, and AGND to ensure low source
impedance for the ADC’s references. These capacitors should
be located as close as possible to the reference pins to reduce
dynamic errors on the ADC reference.
DE-EMPHASIS
Low
Low
Low
High
De-Emphasis Enabled for 44.1kHz
De-Emphasis Disabled
High
Low
De-Emphasis Enabled for 48kHz
High
High
De-Emphasis Enabled for 32kHz
VCOM INPUTS
20BIT Audio Data Selection (Pin 16)
20BIT
A 4.7µF to 10µF tantalum capacitor is recommended between VCOM and AGND to ensure low source impedance of
the ADC and DAC common voltage. This capacitor should
be located as close as possible to the VCOM pin to reduce
dynamic errors on the DC common mode voltage.
FORMAT
Low
ADC: 16-bit MSB-first, Left-justified
DAC: 16-bit MSB-first, Right-justified
High
ADC: 20-bit MSB-first, Left-justified
DAC: 20-bit MSB-first, Right-justified
SYSTEM CLOCK
APPLICATION AND LAYOUT
CONSIDERATIONS
The quality of the system clock can influence dynamic
performance of both the ADC and DAC in the PCM3002/
3003. The duty cycle and jitter at the system clock input pin
must be carefully managed. When power is supplied to the
part, the system clock, bit clock (BCKIN) and a word clock
(LCRIN) should also be supplied simultaneously. Failure to
supply the audio clocks will result in a power dissipation
increase of up to three times normal dissipation and may
degrade long term reliability if the maximum power dissipation limit is exceeded.
POWER SUPPLY BYPASSING
The digital and analog power supply lines to PCM3002/
3003 should be bypassed to the corresponding ground pins
with both 0.1µF ceramic and 10µF tantalum capacitors as
close to the device pins as possible. Although PCM3002/
3003 has three power supply lines to optimize dynamic
performance, the use of one common power supply is
generally recommended to avoid unexpected latch-up or pop
noise due to power supply sequencing problems. If separate
power supplies are used, back-to-back diodes are recommended to avoid latch-up problems.
®
21
PCM3002/3003
EXTERNAL MUTE CONTROL
delta-sigma noise shaper consists of five integrators which
use a switched-capacitor topology, a comparator and a
feedback loop consisting of a one-bit DAC. The delta-sigma
modulator shapes the quantization noise, shifting it out of
the audio band in the frequency domain. The high order of
the modulator enables it to randomize the modulator outputs, reducing idle tone levels.
For Power-Down ON/OFF control without click noise which
is generated by DAC output DC level change, an external
mute control is recommended. The control sequence, which
is external mute ON, CODEC Power-Down ON, SYSCLK
stop and resume if necessary, CODEC Power-down OFF,
and external mute OFF is recommended.
The 64fS one-bit data stream from the modulator is converted to 1fS 18-bit data words by the decimation filter,
which also acts as a low pass filter to remove the shaped
quantization noise. The DC components are removed by a
high pass filter function contained within the decimation
filter.
THEORY OF OPERATION
ADC SECTION
The PCM3002/3003 ADC consists of two reference circuits,
a stereo single-to-differential converter, a fully differential
5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The
Block Diagram in this data sheet illustrates the architecture
of the ADC section, Figure 1 shows the single-to-differential
converter, and Figure 13 illustrates the architecture of the
5th-order delta-sigma modulator and transfer functions.
THEORY OF OPERATION
DAC SECTION
The delta-sigma DAC section of PCM3002/3003 is based on
a 5-level amplitude quantizer and a 3rd-order noise shaper.
This section converts the oversampled input data to 5-level
delta-sigma format. A block diagram of the 5-level deltasigma modulator is shown in Figure 14. This 5-level deltasigma modulator has the advantage of improved stability
and reduced clock jitter sensitivity over the typical one-bit
(2 level) delta-sigma modulator. The combined oversampling
rate of the delta-sigma modulator and the internal 8X interpolation filter is 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level deltasigma modulator is shown in Figure 15.
An internal reference circuit with three external capacitors
provides all reference voltages which are required by the
ADC, which defines the full scale range for the converter.
The internal single-to-differential voltage converter saves
the space and extra parts needed for external circuitry
required by many delta-sigma converters. The internal fulldifferential signal processing architecture provides a wide
dynamic range and excellent power supply rejection performance. The input signal is sampled at 64X oversampling
rate, eliminating the need for a sample-and-hold circuit, and
simplifying anti-alias filtering requirements. The 5th-order
Analog In
X(z) +
–
1st SW-CAP
Integrator
–
+
–
2nd SW-CAP
Integrator
3rd SW-CAP
Integrator
+
4th SW-CAP
Integrator
5th SW-CAP
Integrator
Qn(z)
+
+
+
+
+
+
+
+
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)
Signal Transfer Function
Noise Transfer Function
FIGURE 13. Simplified 5th-Order Delta-Sigma Modulator.
®
PCM3002/3003
22
STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]
Digital Out
Y(z)
+
+
In
+
8fS
18-Bit
+
+
Z–1
+
Z–1
–
Z–1
–
+
+
5-level Quantizer
+
4
3
Out
2
1
64fS (256fS)
0
FIGURE 14. 5-Level Delta-Sigma Modulator Block Diagram.
Gain (–dB)
3rd ORDER ∆Σ MODULATOR
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
5
10
15
20
25
30
Frequency (kHz)
FIGURE 15. Quantization Noise Spectrum.
®
23
PCM3002/3003