49% FPO ® PCM1712U Stereo Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● 16-BIT RESOLUTION ● COMPLETE STEREO DAC: 8X Oversampling Digital Filter Multi-Level Delta-Sigma DAC Analog Low Pass Filter Output Amplifier The PCM1712 is a complete low cost stereo, audio digital-to-analog converter, including digital interpolation filter, 3rd-order delta-sigma DAC, and analog output amplifiers. PCM1712 accepts 16-bit normal input data (MSB first, right justified), or 16-bit IIS data (32-bits per word, continuous clock). ● HIGH PERFORMANCE: –87dB THD + N 94dB Dynamic Range 98dB SNR The digital filter performs an 8X interpolation function, as well as special functions such as soft mute, digital attenuation, de-emphasis and double-speed dubbing. ● SYSTEM CLOCK: 384fs ● SINGLE +5V POWER SUPPLY PCM1712 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. Its low cost, small size and single +5V power supply make it ideal for automotive CD players, bookshelf CD players, BS tuners, keyboards, MPEG audio, MIDI applications, set-top boxes, CD-ROM drives, CD-Interactive and CD-Karaoke systems. PCM1712 has the same pinout functions as PCM1710. ● ON-CHIP DIGITAL FILTER: Soft Mute and Attenuation Digital De-emphasis Double Speed Dubbing Mode ● SMALL 28-PIN SOIC PACKAGE Lch/Rch ATT Control Digital In Input Interface and Attentuator Oversampling Digital Filter Mode Control System Clock 3rd-Order Multi-Level Delta Sigma Lch OUT DAC Low-Pass Filter Output Op Amp Rch OUT International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1994 Burr-Brown Corporation PDS-1245B Printed in U.S.A. June, 1995 SPECIFICATIONS All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit data, SYSCLK = 384fs, unless otherwise noted. PCM1712U PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 16 DIGITAL INPUT/OUTPUT Logic Family Input Logic Level (pins 1 to 3) VIH VIL Input Logic Current (pins 1 to 3) II Input Logic Level (pins 24 to 28) VIH VIL Input Logic Level (pins 24 to 28) II Input Logic Level (XTI) VIH VIL Input Logic Current (XTI) II Output Logic Level (CLKO): VOH VOL Output Logic Current IO Data Format Data Bit Sampling Frequency System Clock Frequency DC ACCURACY Gain Error Gain Mis-Match Channel-To-Channel Bipolar Zero Error Gain Drift Bipolar Gain Drift DYNAMIC PERFORMANCE(1) THD+N at F/S (0dB) THD+N at –60fdB Dynamic Range S/N Ratio Channel Separation DIGITAL FILTER PERFORMANCE Pass Band Ripple Pass Band Ripple Stop Band Attenuation Stop Band Attenuation Pass Band Pass Band Stop Band Stop Band De-emphasis Error Bits 2.0 0.8 VDC VDC –200 µA 1.5 VDC VDC –200 µA 1.4 VDC VDC –120 µA 0.5 VDC VDC 3.5 3.2 4.5 384fs ±10 Normal/IIS (see Timing) SELECTABLE 16-Bit/MSB First, Two’s Complement 32 44.1 48 12.288 16.934 18.432 kHz MHz ±1.0 ±1.0 ±20 ±50 ±20 % of FSR % of FSR mV ppm of FSR/°C ppm of FSR/°C VO = 1/2VCC at Bipolar Zero fIN = 991Hz fIN = 991kHz EIAJ A-weighted EIAJ A-weighted fIN = 991Hz Normal Mode Double Speed Mode Normal Mode Double Speed Mode Normal Mode Double Speed Mode Normal Mode Double Speed Mode (fS 32kHz ~ 48kHz) ANALOG OUTPUT Voltage Range Load Impedance Center Voltage –82 92 90 ±5.0 ±5.0 –87 –34 94 98 96 ±0.17 ±0.22 –35 –34 0.4535 0.4535 0.5465 0.5465 –0.2 +0.55 3.1 +VCC = +VDD = +5.0V +VCC = +VDD = +5.0V TEMPERATURE RANGE Operation Storage +5.0 +5.0 28 140 –25 –55 dB dB dB dB fs fs fs fs dB Vp-p Ω V +1/2VCC +4.5 +4.5 mA dB dB dB dB dB 5k POWER SUPPLY REQUIREMENTS Voltage Range: +VCC +VDD Supply Current +ICC +IDD Power Dissipation UNITS +5.5 +5.5 40 200 VDC VDC mA mW +85 +100 °C °C NOTE: (1) Tested with Shibasoku #725 THD. Meter 400Hz HPF, 30kHz LPF On, Average Mode with 20kHz bandwidth limiting. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1712 2 PIN ASSIGNMENTS PIN NAME NUMBER FUNCTION Input Interface Pins LRCIN 1 DIN 2 Sample Rate Clock Input. Controls the update rate (fs). Serial Data Input. MSB first, right justified format contains a frame of 16-bit or 20-bit data. BCKIN 3 Bit Clock Input. Clocks in the data present on DIN input. Mode Controls and Clock Signals CLKO 4 Buffered Output of Oscillator. Equivalent to fs. XTI 5 Oscillator Input (External Clock Input). For an internal clock, tie XTI to one side of the crystal oscillator. For an external clock, tie XTI to the output of the chosen external clock. XTO 6 Oscillator Output. When using the internal clock, tie to the opposite side (from pin 5) of the crystal oscillator. When using an external clock, leave XTO open. MODE 24 Operation Mode Select. For serial mode, tie MODE “High”. For parallel mode, tie MODE “Low”. MUTE 25 Mute Control. To disable soft mute, tie MUTE “High”. To enable soft mute, tie MUTE “Low”. MD/DM1 26 Mode Control for Data/De-emphasis. See “Mode Control Functions” on page 10. MC/DM2 27 Mode Control for BCKIN/De-emphasis. See “Mode Control Functions” on page 10. ML/DSD 28 Mode Control for WDCK/Double speed dubbing. See “Mode Control Functions” on page 10. Analog Functions VOUTR 13 Right Channel Analog Output. VOUTL 16 Left Channel Analog Output. Power Supply Connections DGND 7, 22 Digital Ground. VDD 8, 21 Digital Power Supply (+5V). VCC2R 9 Analog Power Supply (+5V), Right Channel DAC. AGND2R 10 Analog Ground (DAC), Right Channel. EXT1R 11 Output Amplifier Common, Right Channel. Bypass to ground with a 10µF capacitor. EXT2R 12 Output Amplifier Bias, Right Channel. Connect to EXT1R. AGND 14 Analog Ground. VCC 15 Analog Power Supply (+5V). EXT2L 17 Output Amplifier Bias, Left Channel. Connect to EXT1L. EXT1L 18 Output Amplifier Common, Left Channel. Bypass to ground with a 10µF capacitor. AGND2L 19 Analog Ground (DAC), Left Channel. VCC2L 20 Analog Power Supply (+5V), Left Channel DAC. NC 23 No Connection. PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ....................................................................... +6.5V +VCC to VDD Voltage ......................................................................... ±0.1V Input Logic Voltage ......................................................... –0.3V~VDD+0.3V Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature Range .......................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C MODEL PACKAGE PACKAGE DRAWING NUMBER(1) PCM1712U 28-Pin SOIC 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® 3 PCM1712 CONNECTION DIAGRAM 1 Serial Data Input(3) 2 Digital Filter 3 4 10pF ~ 22pF x 2 28 Input Interface Mode Control Timing Control 24 Noise Shaper 6 23 7 8 22 5-Level ∆Σ DAC Right 5-Level ∆Σ DAC Left 9 (1) 10 10µF + DAC Rch OUT Low-Pass Filter Left (1) 21 20 Low-Pass Filter Right 11 12 Mode Control(3) 26 25 5 (1) 27 (1) 19 10µF + 18 CMOS Amp Right CMOS Amp Left 17 13 16 14 15 DAC Lch OUT (1) 100µF +5V Power Supply 10kΩ 10kΩ 1500pF 10kΩ Rch OUT 680pF 10kΩ 10kΩ 100pF 680pF NOTE: (1) Bypass Capacitor :1µF ~ 10µF. (2) Typical application circuit. To obtain guaranteed specifications, required 20kHz bandwidth limitation by low pass filter. (3) Input pins require pull-up resistors. 3rd ORDER LPF(2) 3rd ORDER LPF(2) PIN CONFIGURATION LRCIN 1 DIN 2 BCKIN 3 CLKO 4 XTI 5 XTO 6 DGND 7 VDD 8 VCC2R 9 Input Interface Digital Filter Mode Control Timing Control Noise Shaper 5-Level ∆Σ DAC Right 5-Level ∆Σ DAC Left Low-Pass Filter-Left 28 ML/DSD 27 MC/DM2 26 MD/DM1 25 MUTE 24 MODE 23 NC 22 DGND 21 VDD 20 VCC2L 19 AGND2L 18 EXT1L 17 EXT2L AGND2R 10 EXT1R 11 EXT2R 12 VOUTR 13 16 VOUTL AGND1 14 15 VCC1 CMOS Amp Left ® PCM1712 1500pF 10kΩ 4 Lch OUT 100pF DATA INPUT TIMING 1 f/s Left-channel Data Right-channel Data MSB DIN 1 2 14 15 LSB MSB 16 1 LSB 2 14 15 16 BCKIN LRCIN FIGURE 1. Normal Format, 16-Bit (LRCIN H: Lch). 1 f/s Left-channel Data Right-channel Data MSB DIN 16 1 LSB MSB 2 3 13 14 15 16 1 LSB 2 3 13 14 15 16 BCKIN LRCIN FIGURE 2 . IIS Format, 16-Bit (32 BCKIN/fs, continuous data). BCKIN tBCWH tBCWL tBCY DIN tDH tDS tBL tLB LRCIN FIGURE 3. Data Input Timing. BCK Pulsewidth (H Level) BCK Pulsewidth (L Level BCK Pulse Cycle Time DIN Setup Time DIN Hold Time BCK Rising Edge → LRCI Edge LRC I Edge → BCK Rising Edge tBCWH tBCWL tBCY tDS tDH tBL tLB 70ns (min) 70ns (min) 140ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) TABLE I. Data Input Timing Specifications. ® 5 PCM1712 MC tMCWH tMCWL tMCY MD tMH tMS tMCS tMCH ML tMLY FIGURE 4. Serial Mode Control Timing. MC Pulsewidth (H Level) MC Pulsewidth (L Level) MC Pulse Cycle Time MD Setup Time MD Hold Time ML Setup Time ML Hold Time ML Low-Level Time tMCWH tMCWL tMCY tMS tMH tMCS tMCH tMLY 50ns (min) 50ns (min) 100ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) 1/sysclk + 20ns (min) TABLE II. Serial Mode Control Timing Specifications (Refer to Figure 5). ® PCM1712 6 TYPICAL PERFORMANCE CURVES All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, fSYS = 384fs, and 16-bit data, unless otherwise noted. DIGITAL FILTER PASSBAND RIPPLE CHARACTERISTIC NORMAL MODE (De-emphasis: OFF) OVERALL FREQUENCY CHARACTERISTICS NORMAL MODE (De-emphasis: OFF) 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –1 –100 0 20k 40k 60k 80k 100k 120k 140k 160k 180k 0 10k 15k 20k Frequency (Hz) Frequency (Hz) OVERALL FREQUENCY CHARACTERISTICS DOUBLE-SPEED MODE (De-emphasis: OFF) PASSBAND RIPPLE FREQUENCY CHARACTERISTIC DOUBLE-SPEED MODE (De-emphasis: OFF) 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –100 –1 0 20k 40k 60k 80k 100k 120k 140k 160k 180k 0 5k 10k 15k 20k 25k 30k Frequency (Hz) Frequency (Hz) DE-EMPHASIS CHARACTERISTIC DOUBLE-SPEED MODE DE-EMPHASIS CHARACTERISTIC NORMAL MODE 0 0 –2 –2 –4 –4 dB dB 5k –6 40k –6 –8 –8 –10 –10 –12 35k –12 0 10k 20k 30k 40k 50k 0 Frequency (Hz) 5k 10k 15k 20k 25k Frequency (Hz) ® 7 PCM1712 TYPICAL PERFORMANCE CURVES (CONT) All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, fSYS = 384fs, and 16-bit data, unless otherwise noted. DYNAMIC PERFORMANCE (Based on 200 piece sample from 3 diffusion runs) BPZ ERROR vs TEMPERATURE THD FS vs TEMPERATURE 50 –82 45 –83 –84 35 Maximum Maximum 30 THD FS (%) BPZ Error (mV) 40 Average 25 20 15 Minimum Average –86 Minimum –88 –90 –94 10 –100 5 0 0 –25 0 25 50 70 85 90 –25 0 Temperature (°C) 100 –31 99 –31.7 98 –32.4 97 S/N (dB) Maximum –33 Average –35 85 90 Maximum Average 96 95 94 Minimum 93 –36 Minimum –37 92 91 –38.4 90 –40 –25 0 25 50 70 85 –25 90 0 25 50 70 85 90 Temperature (°C) Temperature (°C) THD+N AT FS vs SUPPLY VOLTAGE BPZ ERROR vs SUPPLY VOLTAGE 50 –82 45 –83 –25°C 40 –84 35 +85°C 30 –25°C 25 THD FS (dB) THD –60dB (%) 70 SNR vs TEMPERATURE THD –60dB vs TEMPERATURE BPZ Error (mV) 50 Temperature (°C) –30.5 –34 25 25°C 20 15 +85°C –86 –88 25°C –90 –94 10 –100 5 0 0 4.5 5.0 4.5 5.5 ® PCM1712 5.0 Voltage (V) Voltage (V) 8 5.5 TYPICAL PERFORMANCE CURVES (CONT) All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, fSYS = 384fs, and 16-bit data, unless otherwise noted. DYNAMIC PERFORMANCE (Based on 200 piece sample from 3 diffusion runs) SNR vs SUPPLY VOLTAGE 100 –31.0 99 –31.7 98 –32.4 85°C 97 –33.0 +85C°C –25°C S/N (dB) THD –60dB (dB) THD+N AT –60dB vs SUPPLY VOLTAGE –30.5 25°C –34.0 –35.0 25°C 95 94 –36.0 93 –37.0 92 –38.4 91 –40.0 –25°C 96 90 4.5 5.0 5.5 4.5 Voltage (V) 5.0 5.5 Voltage (V) CAUTION: Minimum and maximum values on typical performance curves are not meant to imply a guarantee. Curves should be used for reference only. Refer to specifications for guaranteed performance. ® 9 PCM1712 PARALLEL-MODE: DOUBLE-SPEED DUBBING CONTROL (PIN 24 [MODE] = L) FUNCTIONAL DESCRIPTION PCM1712 has several built-in functions including digital attenuation, digital de-emphasis and soft mute. These functions are software controlled. PCM1712 can be operated in two different modes, Serial or Parallel. Serial Mode is a three-wire interface using pin 26 (MD), pin 27 (MC), and pin 28 (ML). Data on these pins are used to control deemphasis modes, mute, double-speed dubbing, input resolution and input formats. PCM1712 can also be operated in parallel mode, where static control signals are used on pins 26 (DM1), pin 27 (DM2), and pin 28 (DSD). Operation of both of these modes are covered in detail in the next sections. Serial Mode Parallel Mode Double Speed Dubbing Mode In the parallel mode, double-speed dubbing can be enabled by holding pin 28 (DSD) at logic “low”. SERIAL MODE CONTROL In order to use all of PCM1712’s functionality, the serial mode control should be used. PCM1712 must be addressed three separate times to set all of the various registers and flags that control these functions. Table VII together with Figure 6 details the control of the PCM1712 in the serial mode. Internal latches are used to hold this serial data until the PCM1712 is enabled to use the data. The serial mode is used by applying clocked data to the following pins: MODE CONTROL: SERIAL/PARALLEL SELECTION MODE = L Normal Mode DSD = L TABLE VI. DSD (Pin 28). CAUTION: Mode control signals operate on level triggered logic. The minimum timing conditions detailed in Figures 4 and 5 MUST be observed. MODE = H DSD = H TABLE III. Serial and Parallel Mode are Selectable by MODE Pin (Pin 24). NAME PIN FUNCTION MC ML MD 27 28 26 Clock for Strobing in Data Latches Data into the Registers 8-bit Data Word Defining Operation MODE CONTROL: SELECTABLE FUNCTIONS FUNCTION SERIAL MODE (MODE = H) PARALLEL MODE (MODE = L) 0 0 0 0 0 0 X (Normal Mode Fixed) X 0 0 X 0 Input Data Format Selection Input LRCI Polarity Selection De-emphasis Control Mute Attenuation Double-Speed Dubbing DIGITAL ATTENUATION One of the functions which can be implemented through use of the serial mode control is attenuation. This function allows the user to control the level of the output, independent of the input level set by the actual input data supplied to the DAC. Referring to Figure 5, when the first data bit (B0) on MD (pin 26) is low, the attenuation function is enabled. The next seven bits (B1 - B6) define a binary value, ATT_DATA, that indicates the desired level of attenuation. The attenuation level is given by: NOTE: 0: Selectable, X: Not Selectable. TABLE IV. Selectable Functions in Serial Mode and Parallel Mode. Table IV indicates which functions are selectable within the user’s chosen mode. All of the functions shown are selectable within the serial mode, but only de-emphasis control, mute and double-speed dubbing may be selected when using PCM1712 in the parallel mode. Level = 20log10 (1 - ATT_DATA/127) dB When all 7 bits of the ATT_DATA word are high (ATT_DATA = 127), attenuation is infinite and the output of PCM1712 will be zero. PARALLEL-MODE: DE-EMPHASIS CONTROL (PIN 24 [MODE] = L) DM1 (Pin 26) DM2 (Pin 27) De-emphasis L H L H L L H H OFF 32kHz 48kHz 44.1kHz TABLE V. De-emphasis (Pins 26 and 27). In the parallel mode, de-emphasis conditions are controlled by the logic levels on pin 26 (DM1) and pin 27 (DM2). For PCM1712, de-emphasis can operate at 32kHz, 44.1kHz, 48kHz, or disabled. ® PCM1712 10 B0 B1 B2 FUNCTION MODE SELECTION BIT NO. MODE FLAG MODE B3 B4 DEEM2 DEEM1 Sampling Frequency BIT VALUE 1 0 0 B5 IIR DEEM1 De-emphasis 1 B6 MUTE B7 Mode 1 0 1 Mute DSD MODE BY DEFAULT DEEM2 0 for De-emphasis Mode SELECTED FUNCTION Double-Speed B3 Not Assigned B4 Not Assigned B5 Not Assigned 0 1 32kHz 1 48kHz 44.1kHz 0 De-emphasis OFF 1 De-emphasis ON 0 Mute OFF 1 Mute ON 0 Double-speed OFF 1 Double-speed ON 44.1kHz OFF OFF OFF 2 B6 LRPL B7 Polarity for LRCI IIS Input Format 0 Lch:high/Rch:low 1 Lch:low/Rch:high 0 Normal 1 IIS Lch:HIGH Rch:LOW Normal TABLE VII. Serial-Mode Control Input Format (MODE: H, Pin 24). MC ML ATT_DATA Alternation Mode L D6 D5 D4 D3 D2 D1 D0 Mode 1 H L L DEEM2 DEEM1 IIR MUTE DSD Mode 2 H L H LRPL IIS Bit# B0 B1 B2 B6 B7 MD B3 B4 B5 (NOTE: Cycle Time for Model Control—Cycle time for mode control must be set over 192 times of minimum system clock.) FIGURE 5. Mode Control Input Format, Serial Mode. MODE 1 CONTROLS This mode can be enabled with the sequence of 1, 0, 0 as the first three bits on MD (pin 26). This mode allows for the following functions: De-emphasis On/Off De-emphasis Frequency 32kHz, 44.1kHz, 48kHz Soft Mute On/Off Double-Speed Dubbing On/Off B3 B4 0 0 FREQUENCY OFF 0 1 48kHz 1 0 32kHz 1 1 44.1kHz Once the reset has been established on pin 27 (MC), the deemphasis frequency defaults to 44.1kHz. B5 can be used to override B3 and B4; a logic low on B5 disables de-emphasis, and a logic high on B5 forces de-emphasis at 44.1kHz. DIGITAL DE-EMPHASIS SOFT MUTE PCM1712 allows three different sampling rates for digital de-emphasis. B3 and B4 are used for binary control of the de-emphasis frequency: Soft mute is enabled when B6 is high. The soft mute occurs gradually, unlike the forced infinite zero detection. When the mute data bit is high, complete muting will occur in 127/fs seconds. ® 11 PCM1712 SYSTEM CLOCK DOUBLE-SPEED DUBBING Double-speed dubbing is enabled when B7 is high. Since fS is set at 44.1kHz, the system clock in double-speed mode is at 192fs. SAMPLING FREQUENCY SYSTEM CLOCK 32kHz 384fs 12.2880MHz 44.1kHz 384fs 16.9344MHz 48kHz 384fs 18.4320MHz MODE 2 CONTROLS This mode is enabled when the first three bits on MD are 1, 0, 1. Mode 2 allows for the following functions: LR Polarity Controls Left/Right Channel Select Input Format Normal/IIS (Philips format) FREQUENCY NORMAL/DOUBLE-SPEED DUBBING For most CD playback applications operating at 384fs, the system clock frequency must be 16.9344MHz, in both the normal mode and double-speed dubbing mode. Table VIII illustrates the relationship between fs and output clock frequency in both modes. SAMPLE RATE CLOCK POLARITY B6 controls the polarity of the sample rate clock (LRCIN) polarity. When B6 is low, data will be accepted on the left channel when LRCIN is high, and on the right channel when LRCIN is low. When B6 is high, data will be accepted on the right channel when LRCIN is high, and on the left channel when LRCIN is low. PARAMETER XTI Input Clock Frequency XTI Frequency CLKO Output Clock Frequency H (Normal) DSD L (Double Speed) 384fs 192fs 16.9344MHz (fS = 44.1kHz) 16.9344MHz (fS = 88.2kHz) 384fs 192fs TABLE VIII. Relationship Between Normal/Double Speed and fs. INPUT FORMAT Normal input mode for PCM1712 is MSB first, right justified. PCM1712 may also be operated with IIS input format. When B7 is low, the input format is “normal”. When B7 is high, the input format is “IIS”. EXTERNAL SYSTEM CLOCK Figure 7 is a diagram showing the internal clock in conjunction with an external crystal oscillator. DEFAULT MODE At initial power-on, default settings for PCM1712 are 44.1kHz fS, de-emphasis off, mute off, double speed off, infinite zero detect on, 16-bit input LRCIN left channel high, and normal input mode. Internal System Clock VIH > 0.64VDD CLKO (XTI) VIL < 0.28VDD XTI XTO TH > 10ns Crystal TL < 10ns C1 C2 C1, C2: 10pF ~ 22pF TH VIH FIGURE 7. External Crystal Oscillator. VIIL Figure 8 is a diagram showing the internal clock with an external clock source, instead of an oscillator. An external system clock (input to XTI) must meet timing requirement which is shown in Figure 6. TL In case of system clock inputs to XTI from external, system clock should be input with the following condition. FIGURE 6. Timing Requirement for External System Clock (XTi). ® PCM1712 12 Digital Power Supply Analog Power Supply Internal System Clock CLKO (XTI) XTI VDD VCC DGND AGND XTO(1) FIGURE 9. Latch-up Prevention Circuit. External System Clock Input BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. Refer to Figure 16 for optimal values of bypass capacitors. For applications which require very high performance at low levels (such as keyboards, synthesizers, etc.), it may be beneficial to provide additional bypassing on pin 15 (VCC1) with a low ESR 100µF capacitor. This will eliminate stray tones which may be above the noise floor. NOTE: (1) XTO must be open. FIGURE 8. Latch-up Prevention Circuit. POWER SUPPLY CONNECTIONS THEORY OF OPERATION The delta-sigma section of PCM1712 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled 16-bit input data to 5-level delta-sigma format. PCM1712 has two power supply connections: digital (VDD) and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.6V. A block diagram of the 5-level delta-sigma modulator is shown in Figure 10. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. An application circuit to avoid a latch-up condition is shown in Figure 9. + + In 8fs 16 Bit + Z–1 + + – + Z–1 Z–1 – + + + 5-level Quantizer 4 Out 3 48fs 2 1 0 FIGURE 10. 5 Level ∆Σ Modulator Block Diagram. ® 13 PCM1712 OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1712 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD + N, etc. to 20kHz. Failure to use such a filter will result in higher THD + N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 48fs. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 11. THIRD-ORDER ∆Σ MODULATOR 20 0 The performance of the internal low pass filter from DC to 24kHz is shown in Figure 12. The higher frequency rolloff of the filter is shown in Figure 13. If the user’s application has the PCM1712 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 14. For some applications, a passive RC filter or 2nd-order filter may be adequate. –20 Gain (–dB) –40 –60 –80 –100 –120 –140 –160 0 5 10 15 20 25 SIMULATED ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) Frequency (kHz) 1.0 FIGURE 11. Quantization Noise Spectrum. 0.5 dB APPLICATION CONSIDERATIONS 0 DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1712: TD = 12.625 x 1/fs –0.5 –1.0 20 100 1k Frequency (Hz) 10k FIGURE 12. Low Pass Filter Frequency Response. For fS = 44.1kHz, TD = 12.625/44.1kHz = 286.28µs SIMULATED ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. dB INTERNAL RESET When power is first applied to PCM1712, an automatic reset function occurs after 64 cycles of LRCIN. 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M Frequency (Hz) FIGURE 13. Low Pass Filter Frequency Response. ® PCM1712 24k 14 10M TEST CONDITIONS Figure 15 illustrates the actual test conditions applied to PCM1712 in production. The 11th-order filter is necessary in the production environment for the removal of noise resulting from the relatively long physical distance between the unit and the test analyzer. In most actual applications, the third-order filter shown in Figure 14 is adequate. Under normal conditions, THD+N typical performance is –70dB with a 30kHz low pass filter (shown here on the THD meter), improving to –92dB when the external 20kHz second-order filter is used. EVALUATION FIXTURES An evaluation fixture is available for PCM1712. DEM-PCM1712 This evaluation fixture is primarily intended for quick evaluation of the PCM1712’s performance. DEM-PCM1712 can accept either an external clock or a user-installed crystal oscillator. All of the functions can be controlled by on-board switches. DEM-PCM1712 does not contain a receiver chip or an external low pass filter. DEM-PCM1712 requires a single +5V power supply. 1 1500pF 4 + 5 10kΩ 2 3 10kΩ 10kΩ 100pF 680pF VSIN – GAIN vs FREQUENCY 90 6 –14 0 –34 –90 –180 –54 Phase (°) Gain (dB) Gain Phase –270 –74 –360 –94 100 1k 10k Frequency (Hz) 100k 1M FIGURE 14. 3rd-Order LPF. Shibasoku #725 Test Disk Through Lch CD Player DAI Digital DEMPCM1712 11th-order 20kHz LPF Rch PGA THD Meter 0dB/60dB 30KHz LPF on For test of S/N ratio and Dynamic Range, A-filter ON. FIGURE 15. Test Block Diagram. ® 15 PCM1712 CN1 DS LRCIN 1 28 DSD DM2 DIN 2 27 BCKIN 3 26 DM1 CLKO 4 25 MODE XTI 5 24 CKSL XTO 6 23 7 22 8 9 20 (2) 10 19 11 18 12 17 13 16 14 15 10µF (2) 21 + (1) (2) ML C N 2 10µF + PCM1712U (2) MC MD GND +VCC (2) + 100µF + + NOTE: (1) Bypass Capacitor. 0.1µF Ceramic. (2) Bypass Capacitor 1µF ~ 10µF Tantalum. CN3 C O U T • R D O G U N T D • R D O U T • L C O U T • L FIGURE 16. DEM-PCM1712 Schematic Circuit Diagram. ® PCM1712 16