BB PGA2500IDB

PGA2500
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
Digitally Controlled
Microphone Preamplifier
FEATURES
D Fully Differential Input-to-Output Architecture
D Digitally Controlled Gain Using Serial Port
D
D
D
D
D
D
D
D
D
D
Interface:
− Gain Range: 10dB through 65dB, 1dB per
step
− Unity (0dB) Gain Setting via Serial Port or
Dedicated Control Pin
Dynamic Performance:
− Equivalent Input Noise with ZS = 150Ω and
Gain = 30dB: −128dBu
− Total Harmonic Distortion plus Noise
(THD+N) with Gain = 30dB: 0.0004%
Zero Crossing Detection Minimizes Audible
Artifacts when Gain Switching
Integrated DC Servo Minimizes Output Offset
Voltage
Common-Mode Servo Improves CMRR
Four-Wire Serial Control Port Interface:
− Simple Interface to Microprocessor or
DSP Serial Ports
− Supports Daisy-Chaining of Multiple
PGA2500 Devices
Dedicated Input Pin for Selecting Unity Gain
Overload Output Pin Provides Clipping
Indication
Four General-Purpose Digital Output Pins
Requires ±5V Power Supplies
Available in an SSOP-28 Package
APPLICATIONS
D Microphone Preamplifiers and Mixers
D Digital Mixers and Recorders
DESCRIPTION
The PGA2500 is a digitally controlled, analog microphone
preamplifier designed for use as a front end for highperformance audio analog-to-digital converters (ADCs). The
PGA2500 features include low noise, wide dynamic range,
and a differential signal path. An on-chip DC servo loop is
employed to minimize DC offset, while a common-mode
servo function may be used to enhance common-mode
rejection.
The PGA2500 features a gain range of 10dB through 65dB
(1dB/step), along with a unity gain setting. The wide gain
range allows the PGA2500 to be used with a variety of
microphones. Gain settings and internal functions are
programmed using a 16-bit control word, which is loaded
using a simple serial port interface. A serial data output pin
provides support for daisy-chained connection of multiple
PGA2500 devices. Four programmable digital outputs are
provided for controlling the external switching of input pads,
phantom power, high pass filters, and polarity reversal
functions. The PGA2500 requires both +5V and −5V power
supplies and is available in a small SSOP-28 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2003, Texas Instruments Incorporated
! ! www.ti.com
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted(1)
PGA2500
UNIT
Supply Voltage, VA+
+5.5
V
Supply Voltage, VA−
−5.5
V
Supply Voltage, VD−
−5.5
V
Voltage Difference, VA− to VD−
Less than 300
mV
Analog input voltage
(VA−) −0.3 to (VA+) +0.3
V
Digital input voltage
−0.3 to (VA+) + 0.3
V
−40 to +85
°C
Operating Temperature Range
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Storage Temperature Range
−60 to +150
°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PGA2500
SSOP-28
DB
−40°C
−40
C to +85
+85°C
C
PGA2500I
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
2
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PGA2500IDB
Rails, 48
PGA2500IDBR
Tape and Reel, 1000
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
All parameters specified with TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and VCOMIN = 0V, unless otherwise noted.
PGA2500
PARAMETER
DC Characteristics
Step Size
Gain Error
TEST CONDITIONS
MIN
TYP
Gain = 10dB through 65dB
All Gain Settings
1
0.5
Gain = 0dB, VOUT = 3.5VRMS, VCOMIN = 0V
Gain = 30dB, VOUT = 3.5VRMS, VCOMIN = 0V
−114
−108
MAX
UNIT
dB
dB
AC Characteristics
THD+N with fIN = 1kHz
Analog Input
Maximum Input Voltage
Input Resistance
Per Input Pin
Differential
Gain = 0dB
VA− +1.5
−108
−102
dB
dB
VA+ −2.0
V
Ω
Ω
4600
9200
Analog Output
Output Voltage Range
Output Offset Voltage
Input Referred Offset
Output Resistive Loading
VCOMIN = 0V, RL = 600Ω
DC Servo On, Any Gain
DC Servo Off, Gain = 30dB
VA− +0.9
±0.04
±1
600
Load Capacitance Stability
Short Circuit Current
Digital Characteristics
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
VA+ −0.9
±1
10-second duration
IO = 200µA
IO = −3.2mA
100
pF
100
mA
+2.0
−0.3
(VA+) − 1.0
Input Leakage Current, IIN
V
mV
mV
Ω
VA+
0.8
2
0.4
V
V
V
V
10
µA
6.25
MHz
ns
Switching Characteristics
Serial Clock (SCLK) Frequency
Serial Clock (SCLK) Pulse Width Low
fSCLK
tPH
0
80
Serial Clock (SCLK) Pulse Width High
tPL
80
ns
SDI Setup Time
tSDS
20
ns
SDI Hold Time
CS Falling to SCLK Rising
tSDH
tCSCR
20
90
ns
ns
SCLK Falling to CS Rising
tCFCS
35
ns
Input Timing
Output Timing
CS Low to SDO Active
tCSO
35
ns
SCLK Falling to SDO Data Valid
CS High to SDO High Impedance
tCFDO
tCSZ
60
100
ns
ns
Power Supply
Operating Voltage
VA+
VA−
+4.75
−4.75
+5
−5
+5.25
−5.25
V
V
VD−
−4.75
−5
−5.25
V
Quiescent Current
IA+
IA−
VA+ = +5V
VA− = −5V
30
30
40
40
mA
mA
ID−
VD− = −5V
1
2
mA
3
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
PIN CONFIGURATION
GPO1
1
28
AGND
GPO2
2
27
V IN +
GPO3
3
26
V IN −
GPO4
4
25
V COM IN
OVR
5
24
C S1 1
DGND
6
23
C S1 2
DCEN
7
22
C S2 1
0dB
8
21
C S2 2
ZCEN
9
20
VA−
SDI
10
19
VA+
PGA2500
CS
11
18
VA+
SCLK
12
17
V OUT +
SDO
13
16
V OUT −
VD−
14
15
VA−
PIN DESCRIPTIONS
4
PIN NUMBER
NAME
DESCRIPTION
1
GPO1
General-Purpose CMOS Logic Output
2
GPO2
General-Purpose CMOS Logic Output
3
GPO3
General-Purpose CMOS Logic Output
4
GPO4
General-Purpose CMOS Logic Output
5
OVR
6
DGND
Digital Ground
7
DCEN
DC Servo Enable (Active Low)
8
0dB
Unity Gain Enable (Active High)
9
ZCEN
10
SDI
Serial Data Input
11
CS
Chip Select Input (Active Low)
12
SCLK
Serial Data Clock Input
13
SDO
Serial Data Output
14
VD−
−5V Digital Supply
15
VA−
−5V Analog Supply
16
VOUT−
Analog Output, Inverting
17
VOUT+
Analog Output, Non-Inverting
18
VA+
+5V Analog Supply
19
VA+
+5V Analog Supply
20
VA−
−5V Analog Supply
21
CS22
DC Servo Capacitor #2, Terminal 2
22
CS21
DC Servo Capacitor #2, Terminal 1
23
CS12
DC Servo Capacitor #1, Terminal 2
24
CS11
DC Servo Capacitor #1, Terminal 1
25
VCOMIN
26
VIN−
Analog Input, Inverting
27
VIN+
Analog Input, Noninverting
28
AGND
Over Range Output (Active High)
Zero Crossing Detector Enable (Active High)
Common Mode Voltage Input, 0V to +2.5V
Analog Ground
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
(with Z = 0Ω)
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
−122
−124
−126
−128
−130
−132
−134
−136
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
E.I.N. (dBu)
E.I.N. (dBu)
All specifications at TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and VCOMIN = 0V, unless otherwise noted.
THD+N vs GAIN
(with 4.0 VRMS Output and Z = 40Ω)
EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
(with Z = 150Ω)
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
−122
−124
−126
−128
−130
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
THD+N AND NOISE vs GAIN
(0dB = 4VRMS)
−80
0.01
THD+N and Noise (dB)
THD+N (%)
−85
0.001
THD+N
with Z = 40Ω
−90
−95
−100
−105
Noise
with Z = 0Ω
−110
−115
−120
−125
−130
0.0001
10
15
20
25
30
35 40 45
Gain (dB)
50
55
60
65
10
THD+N vs FREQUENCY
(RS = 40Ω, R L = 600Ω, VCOMIN = 0V, BW = 22Hz to 22kHz)
0.1
THD+N Ratio (%)
THD+N Ratio (%)
VOUT = 4.0Vrms Differential
for Gains = 10, 20, 30, 40, 50, and 60dB
VOUT = 3.5Vrms Differential for Gain = 0dB
60dB
50dB
40dB
0.001
20
25
30
35 40 45
Gain Set (dB)
50
55
60
65
THD+N vs FREQUENCY
(RS = 40Ω, RL = 600Ω, VCOMIN = +2.5V, BW = 22Hz to 22kHz)
0.1
0.01
15
VOUT = 2.0Vrms Differential
for Gains = 10, 20, 30, 40, 50, and 60dB
VOUT = 1.0Vrms Differential for Gain = 0dB
60dB
0.01
50dB
40dB
10dB
0.001
30dB
10dB
0dB
0dB
30dB
20dB
20dB
0.0001
0.0001
20
100
1k
Frequency (Hz)
10k
20k
20
100
1k
10k
20k
Frequency (Hz)
5
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and VCOMIN = 0V, unless otherwise noted.
THD+N vs FREQUENCY
(RS = 40Ω, RL = 600Ω, VCOMIN = +2.5V, BW = 22Hz to 22kHz)
BANDWIDTH vs GAIN
7
0.1
VOUT = 1.0Vrms Differential for All Gain Settings
6
0.01
Bandwidth (MHz)
THD+N Ratio (%)
60dB
50dB
40dB
30dB
0.001
5
4
3
2
1
10dB
0dB
20dB
0
0.0001
20
100
1k
10k
20k
10
15
20
25
30
Frequency (Hz)
THD+N vs OUTPUT AMPLITUDE
THD+N (%)
0.1
0.01
0.001
0.0003
Gain = 30dB
f = 1kHz
VCOMIN = 0V
RS = 40Ω
RL = 600Ω
0.3
0.30
Output Amplitude (Vrms)
6
3.00
6.00
35 40 45
Gain (dB)
50
55
60
65
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
OVERVIEW
The PGA2500 is a digitally controlled microphone
preamplifier integrated circuit designed for amplifying the
output of dynamic and condenser microphones and
driving high performance audio analog-to-digital
converters (ADCs). A functional block diagram of the
PGA2500 is shown in Figure 1.
The analog input to the preamplifier is provided
differentially at the VIN+ and VIN− inputs (pins 27 and 26,
respectively). The programmable gain amplifier can be
programmed to either pass through the signal at unity gain,
or apply 10dB to 65dB of gain to the input signal. The gain
of the amplifier is adjustable over the full 10dB to 65dB
range in 1dB steps. The differential output of the PGA2500
is made available at VOUT+ and VOUT− (pins 17 and 16,
respectively). Gain is controlled using a serial port
interface.
The four-wire serial port interface is used to program the
PGA2500 gain and support functions. A 16-bit control
word is utilized to program these functions (see Figure 2,
page 9). A serial data output pin provides support for
daisy-chaining multiple PGA2500 devices on a single
serial interface bus (see Figure 4, page 10).
The differential analog output of the PGA2500 is
constantly monitored by a DC servo amplifier loop. The
purpose of the servo loop is to minimize the DC offset
voltage present at the analog outputs by feeding back an
error signal to the input stage of the programmable gain
amplifier. The error signal is then used to correct the offset.
The DC servo may be disabled by driving the DCEN input
(pin 7) high or setting the DC bit in the serial control word
to 1. Normally, the DCEN pin is connected to DGND to
enable the DC servo, while the DC bit is set to 0.
0dB
CS
SCLK
ZCEN
SERIAL
PORT and
LOGIC
CONTROL
GPO1
GPO2
SDI
SDO
GPO3
GPO4
OVR
VCOMIN
VOUT+
VIN+
VIN−
PGA
VOUT−
Gain Range
AGND
VA+
VA+
VA−
0dB or
+10dB to +65dB
CS1
1dB per step
DC
Servo
VD−
DGND
VA−
CS2
DCEN
CS1 and CS2 are external DC servo integrator capacitors,
and are connected across the CS11/CS12 and CS21/CS22 pins, respectively.
Figure 1. PGA2500 Functional Block Diagram
7
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
Two external capacitors are required for the DC servo
function, with one capacitor connected between CS11 and
CS12 (pins 24 and 23), and the second capacitor connected
between CS21 and CS22 (pins 22 and 21). Capacitor values
up to 4.7µF may be utilized. However, larger valued
capacitors will result in longer settling times for the DC
servo loop. A value of 1µF is recommended for use in most
microphone preamplifier applications.
switching gain, thereby minimizing audible artifacts at the
preamplifier output. Since zero crossing detection can add
some delay when performing gain changes (up to 16ms
maximum for a detector timeout event), there may be
cases where the user may wish to disable the function.
Forcing the ZCEN input low disables zero crossing
detection, with gain changes occurring immediately when
programmed.
The PGA2500 includes a common-mode servo function.
This function is enabled and disabled using the CM bit in
the serial control word; see Figure 2. When enabled, the
servo provides common-mode negative feedback at the
input differential pair, resulting in very low common-mode
input impedance. The differential input impedance is not
affected by this feedback. This function is useful when the
source is floating, or has a high common-mode output
impedance. In this case, the only connection between the
source and the ground will be through the PGA2500
preamplifier input resistance.
An overflow indicator output, OVR, is provided at pin 5.
The OVR pin is an active high, CMOS-logic-level output.
The overflow output is forced high when the preamplifier
output voltage exceeds one of two preset thresholds. The
threshold is programmed through the serial port interface
using the OL bit. If OL = 0, then the threshold is set to
5.1VRMS differential, which is approximately −1dB below
the specified output voltage range. If OL = 1, then the
threshold is set to 4.0VRMS differential, which is
approximately −3dB below the specified output voltage
range.
In this case, input common-mode parasitic current is
determined by high output impedance of the source, not by
input impedance of the amplifier. Therefore, input
common-mode interference can be reduced by lowering
the common-mode input impedance while at the same
time not increasing the input common-mode current.
Increasing common-mode current degrades commonmode rejection. Using the common-mode servo, overall
common-mode rejection can be improved by suppressing
low and medium frequency common-mode interference.
The PGA2500 includes four programmable digital outputs,
named GPO1 through GPO4 (pins 1 through 4,
respectively), which are controlled via the serial port
interface. All four pins are CMOS-logic-level outputs.
These pins may be used to control relay drivers or
switches used for external preamplifier functions,
including input pads, filtering, polarity reversal, or phantom
power.
The common-mode servo function is designed to operate
with a total common-mode input capacitance (including
the microphone cable capacitance) of up to 10nF. Beyond
this limit, stable servo operation is not ensured.
The common-mode voltage control input, named VCOMIN
(pin 25), allows the PGA2500 output and input to be DCbiased to a common-mode voltage between 0 and +2.5V.
This allows for a DC-coupled interface between the
PGA2500 preamplifier output and the inputs of common
single-supply audio ADCs.
A dedicated 0dB input (pin 8) is provided so that the gain
of the PGA2500 may be forced to unity without using the
serial port interface. The 0dB input overrides gain settings
made through the serial port. While the 0dB input is active
(forced high), the serial port register may be updated or
data may passed through the serial interface to other
PGA2500 devices in daisy-chain configuration. However,
any changes made in the gain will not take effect until the
0dB input is driven low.
The zero crossing control input, named ZCEN (pin 9), is
provided for enabling and disabling the internal zero
crossing detector function. Forcing the ZCEN input high
enables the function. Zero crossing detection is used to
force gain changes on zero crossings of the analog input
signal. This limits the glitch energy associated with
8
ANALOG INPUTS AND OUTPUTS
An analog signal is input differentially across the VIN+ (pin
27) and VIN− (pin 26) inputs. The input voltage range and
input impedance are provided in the Electrical
Characteristics table. The Applications Information
section of this datasheet provides additional details
regarding typical input circuit considerations when
interfacing the PGA2500 to a microphone input.
Both VIN+ and VIN− are biased at approximately 0.65V
below the common-mode input voltage, supplied at
VCOMIN (pin 25). The use of AC-coupling capacitors (see
Figure 7, page 12) is highly recommended for the analog
inputs of the PGA2500. If DC-coupling is required for a
given application, the user must take this offset into
account.
It is recommended that a small capacitor be connected
from each analog input pin to analog ground. Values of at
least 50pF are recommended. See Figure 7 (page 12) for
larger capacitors being used for EMI filtering which will
satisfy this requirement.
The analog output is presented differentially across VOUT+
(pin 17) and VOUT− (pin 16). The output voltage range is
provided in the Electrical Characteristics table. The analog
output is designed to drive a 600Ω differential load while
meeting the published THD+N specifications and typical
performance curves.
"
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SERIAL PORT OPERATION
The SCLK input is used to clock serial data into the SDI pin
and out of the SDO pin. The SDI pin functions as the serial
data input, and is used to write the serial port register. The
SDO pin is the shift register serial output, and is used for
either register read-back or for daisy-chaining multiple
PGA2500 devices. Data on SDI is sampled on the rising
edge of SCLK, while data is clocked out of SDO on the
falling edge of SCLK.
The serial port interface for the PGA2500 is comprised of
four wires: CS (pin 11), SCLK (pin 12), SDI (pin 10), and
SDO (pin 13). Figure 2 illustrates the serial port protocol,
while Figure 3 and the Electrical Characteristics table
provide detailed timing parameters for the port.
The CS input functions as the chip select and word latch
clock for the serial port. The CS input must be low in order
to clock data into and out of the serial port. The control
word is latched on a low-to-high transition of the CS input.
The serial port ignores the SCLK and SDI inputs when CS
is high, and the SDO output is set to a high impedance
state while CS is high.
When the 0dB input (pin 8) is forced high, the gain set by
the serial port register will be overridden. The serial port
register may be updated while the 0dB input is forced high,
but the programmed gain will not take effect until the 0dB
input is forced low.
CS
SCLK
SDI
Data Ignored
DC
CM
0
OL
D4
D3
D2
D1
0
0
G5
G4
G3
G2
G1
G0
Data Ignored
SDO
High Impedance
DC
CM
0
OL
D4
D3
D2
D1
0
0
G5
G4
G3
G2
G1
G0
High Impedance
DC Servo Enable
(Active Low)
Preamplifier Gain
where N = G[5:0]DEC
CM Servo Enable
(Active High)
For N = 0
Gain = 0dB
Overload Indicator Bit
(0 = 5.1VRMS, 1 = 4.0VRMS )
For N = 1 to 56
Gain (dB) = 9 + N
Data for GPO4
For N = 57 to 63
Gain (dB) = 65
Data for GPO3
Data for GPO2
Data for GPO1
Figure 2. Serial Port Protocol
CS
t SDS
t CSCR
tCFCS
tSDH
SCLK
SDI
MSB
SDO
MSB
tCSO
tCFDO
tCSZ
Figure 3. Serial Port Timing Requirements
9
"
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DAISY-CHAINING MULTIPLE PGA2500
PREAMPLIFIERS
Since the serial port interface may be viewed as a serial in,
serial out shift register, multiple PGA2500 preamplifiers
may be connected in a cascaded or daisy-chained fashion,
as shown in Figure 4. The daisy-chained PGA2500
devices behave as a 16 x N-bit shift register, where N is the
VOUT+
VOUT−
PGA2500
#1
number of cascaded PGA2500 devices. To program all of
the devices, simply force CS low for 16 x N serial clock
periods and clock in 16 x N bits of control data. The CS
input is then forced high to latch in the new settings.
A timing diagram for the daisy-chain application is shown
in Figure 5.
SDI
DOUT
CS
CS
SCLK
VIN+
DATACLK
DIN
SDO
VIN −
VOUT+
Micro
or DSP
SDI
VOUT−
CS
PGA2500
#2
SCLK
VIN+
SDO
VIN−
VOUT+
SDI
VOUT−
CS
PGA2500
#N
SCLK
VIN+
SDO
VIN −
Figure 4. Daisy-Chain Configuration for Multiple PGA2500 Preamplifiers
CS
SCLK
SDI
G0
DC
Device #N
DC
G0
DC
Device #2
Figure 5. Serial Port Operation for Daisy-Chain Operation
10
G0
Device #1
"
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APPLICATION INFORMATION
This section provides practical information for designing
the PGA2500 into end applications.
BASIC CIRCUIT CONFIGURATION
A typical applications circuit, without the input and output
circuitry, is shown in Figure 6. Power-supply bypass and
DC servo capacitors are shown with recommended
values. All capacitors should be placed as close as
possible to the PGA2500 package to limit inductive noise
coupling. Surface-mount capacitors are recommended
(X7R ceramic for the 0.1µF and 1µF capacitors, and low
ESR tantalum for the 4.7µF capacitors).
1
2
To
Relay Drivers,
Switches, or Indicators
3
4
5
6
GPO1
The PGA2500 can be placed on a split ground plane, with
the package located over the split. However, there must be
a low impedance connection between the analog and
digital grounds at a common return point.
The DC common-mode input, VCOMIN (pin 25), can be
connected to analog ground or a DC voltage (such as the
reference or common voltage output of an audio ADC).
When biasing this input to a DC voltage, keep in mind that
both the analog output and input pins are level-shifted by
the value of the bias voltage.
AGND
GPO2
GPO3
VIN+
VIN−
GPO4
OVR
VCOMIN
DGND
CS11
7
8
To/From
MPU, MCU,
DSP, or Logic
9
10
11
12
13
0.1µF
4.7µF
+
14
0.1µF
0.1µF
15
20
28
CS12
DCEN
0dB
ZCEN
SDI
CS
PGA2500
CS21
CS22
VOUT+
VOUT−
27
25
24
VD−
VA−
VA−
1µF
0Ω(1)
0.1µF(1)
To
Optional
Common−Mode
Voltage
23
22
1µF
21
17
To
Analog Output
Circuit
16
SCLK
SDO
From
Analog Input
Circuit
26
19
18
0.1µF
0.1µF
4.7µF
+
VA−
VA−
VA+
4.7µF
+
= Analog Ground
Connect Digital and Analog Grounds at
one common return point in the circuit.
10Ω
VA−
= Digital Ground
NOTE: (1) Install a 0Ω shunt or jumper only when connecting VCOMIN
to analog ground. Install a 0.1µF ceramic capacitor (X7R type) only
when connecting VCOMIN to a DC common−mode voltage source.
Figure 6. Basic Circuit Configuration for the PGA2500
11
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
INPUT CIRCUIT CONSIDERATIONS
have a high working voltage rating, with 50V being the
minimum and 63V recommended for long term reliability.
The input circuit for the PGA2500 must include several
items that are common to most microphone preamplifiers.
Figure 7 shows a typical input circuit configuration. Other
functions, such as input attenuation (pads), filters, and
polarity reversal switches are commonly found in
preamplifier circuits, but are not shown here in order to
focus on the basic input circuit requirements.
The blocking capacitors, along with the PGA2500 input
resistance, form a high-pass filter circuit. With the typical
input resistance of the PGA2500 specified in the Electrical
Characteristics table, the value of the capacitor can be
chosen to meet the desired low frequency response for the
end application. At the same time, the value should be no
higher than required, since larger capacitors store more
charge and increase the surge current seen at the
preamplifier when a short circuit occurs on the microphone
input connector.
The microphone input is typically taken from a balanced
XLR or TRS input connection (XLR shown). The 1000pF
capacitors provide simple EMI filtering for the circuit.
Additional filtering for low- or high-frequency noise may be
added, depending upon the end application environment.
A bridging resistor is shown and may be selected to
provide the desired overall input impedance required for a
given microphone. This resistance will be in parallel with
the phantom power bias resistors and the PGA2500 input
resistance to set the actual impedance seen by the
microphone.
To protect the PGA2500 from large surge currents, power
Schottky diodes are placed on the input pins to both the
VA+ and VA− power supplies. Schottky diodes are used
due to their lower turn-on voltage compared to standard
rectifier diodes. Power devices are required since the
surge currents from a large valued blocking capacitor
(47µF) can exceed 4.5 amps for a very short duration of
time. It is recommended that the Schottky diode chosen for
this application be specified for at least a 10A surge
current.
Connections for +48V phantom power, required for
condenser microphones, are shown in Figure 7. The
phantom power requires an On/Off switch, as dynamic
microphones do not require phantom power and may be
damaged if power is applied. DC-blocking capacitors are
required between the phantom power connections and the
PGA2500 inputs. The blocking capacitors are selected to
The use of a series current-limiting resistor prior to the
protection diodes will aid in handling surge currents,
although the resistor will add noise to the circuit. Select a
current-liming resistor value that is as high as tolerable for
the desired noise performance of the preamplifier circuit.
10µF − 47µF
63WV
+
(3)
VIN+
(2)
1
2
(4)
6.81kΩ
0.25W
1000pF
Mic Input
(4)
VA+
VA−
1000pF
(1)
3
1000pF
6.81kΩ
0.25W
10µF − 47µF
63WV
+
(3)
(4)
(4)
(2)
Phantom
Power
Switch
+48V
NOTES: (1) Bridging resistor, used to set the impedance seen by the microphone.
(2) The blocking capacitor value is selected based upon the desired low frequency response.
(3) Current−limiting resistor. Select the highest value tolerable based upon input noise requirements.
(4) Schottky diode, selected for fast turn−on and rated for a minimum of a 10A surge current.
Recommended device is the MBRA120LT3 from ON Semiconductor.
Figure 7. Typical Input Circuit for the PGA2500
12
VIN−
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
OPERATION WITH VCOMIN = +2.5V
Plots of THD+N vs Frequency are shown in the Typical
Characteristics section of this datasheet for both
VCOMIN = 0V and +2.5V. The performance difference can
be seen when comparing the plots. The user needs to
consider whether the difference is acceptable for the end
application.
When interfacing the analog outputs of the PGA2500 with
audio ADC inputs, the converter will frequently have a
common-mode DC output pin. This pin may be connected
to the VCOMIN pin of the PGA2500 in order to facilitate a
DC-coupled interface between the two devices. The
common-mode DC voltage level is typically +2.5V,
although some converters may have a slightly lower value,
usually between +2.1V and +2.5V. There are several
issues that must be considered when operating the
PGA2500 in this fashion.
As a suggested alternative, the PGA2500 analog outputs
may be AC-coupled to the ADC inputs, allowing the
PGA2500 to operate with VCOMIN = 0V in order to achieve
best performance. The AC-coupling capacitors will affect
the overall low-frequency response of the preamplifier and
converter combination, and the user is advised to choose
a value that best suits the application requirements.
Both the analog input and output pins of the PGA2500 will
be level shifted by the VCOMIN voltage. The analog outputs
will be shifted to the VCOMIN level, while the analog inputs
will be shifted to approximately VCOMIN − 0.65V, due to the
offset that normally exists on the input pins. The level
shifting will limit the input and output swing of the
PGA2500, reducing the overall signal-to-noise ratio and
degrading the THD+N performance.
Figure 8 illustrates a typical PGA2500 to audio ADC
interface utilizing AC-coupling. In addition to the coupling
capacitors, a passive RC filter is required as an anti-alias
filter for the converter. The vast majority of audio ADCs are
of the oversampling delta-sigma variety, with a simple
single-pole filter meeting the anti-aliasing requirements for
this type of converter. Providing at least 6dB of attenuation
will also allow the PGA2500 to operate near full signal
swing without overdriving the ADC inputs.
Given VCOMIN = +2.5V and gains of 10dB through 65dB,
the output swing is limited to less than one-half that
specified in the Electrical Characteristics table. The output
will hard-clip at approximately a diode drop below the VA+
supply rail and a diode drop above analog ground.
Figure 9 illustrates an application where the VCOMIN pin of
the PGA2500 is connected to the common-mode DC
output of the audio ADC, with a DC-coupled interface
between the PGA2500 analog outputs and the ADC
analog inputs.
Given VCOMIN = +2.5V and a gain of 0dB, the practical
maximum input or output voltage swing is approximately
1.0Vrms differential. Increasing the signal level much
beyond this point will result in a substantial increase in
distortion.
PGA2500
Coupling
Capacitors
VOUT+
PGA
R
2R
+
VOUT−
VCOMIN
CC1
+
A/D Converter(1)
CC2
C
ADC
Serial Data Output
PCM or DSD
R
Attenuation and
Anti−Alias Filter
NOTE: (1) PCM1804, PCM4202, or PCM4204.
Figure 8. PGA2500 Analog Output to ADC Analog Input Interface, AC-Coupled
13
"
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
A/D Converter(1)
PGA2500
VOUT+
R
C
PGA
VOUT−
VCOMIN
ADC
Serial Data Output
PCM or DSD
R
Anti−Alias Filter
VCOM Output
0.1µF
NOTE: (1) PCM1804, PCM4202, or PCM4204.
Figure 9. PGA2500 Analog Output to ADC Analog Input Interface, DC-Coupled
14
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
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