TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 6.5-W MONO CLASS-D AUDIO POWER AMPLIFIER FEATURES • • • • • DESCRIPTION 6.5 W Into 8-Ω Load From 12-V Supply (10% THD+N) Short Circuit Protection (Short to VCC, Short to GND, Short Between Outputs) Third-Generation Modulation Technique: – Replaces Large LC Filter With Small, Low-Cost Ferrite Bead Filter in Most Applications – Improved Efficiency – Improved SNR Low Supply Current . . . 8 mA Typ at 12 V Shutdown Control . . . <1 µA Typ The TPA3007D1 is a 6.5-W mono bridge-tied load (BTL) class-D audio power amplifier with high efficiency, eliminating the need for heat sinks. The TPA3007D1 can drive 8-Ω speakers with only a ferrite bead filter required to reduce EMI. The gain of the amplifier is controlled by two input terminals, GAIN1 and GAIN0. This allows the amplifier to be configured for a gain of 12, 18, 23.6, and 36 dB. The differential input stage provides high common mode rejection and improved power supply rejection. The amplifier also includes depop circuitry to reduce the amount of pop at power-up and when cycling SHUTDOWN. APPLICATIONS • • • • The TPA3007D1 is available in the 24-pin TSSOP package (PW) and does not require an external heat sink. LCD Monitors/TVs Desktop Replacement Notebook PCs Hands-Free Car Kits Powered Speakers Functional Schematic Diagram U1 TPA3007D1 C1 IN− 0.47 µF 1 2 IN+ C2 0.47 µF 3 GAIN SELECT 4 GAIN SELECT 5 SHUTDOWN CONTROL 6 7 C10 1 µF VCC C7 10 µF R2 C8 0.22 µF 8 51 Ω 9 10 C5 1 µF 11 12 INN VCC VCC 24 VREF 23 C3 22 1 µF GAIN0 BYPASS GAIN1 COSC 21 INP SHUTDOWN PGND VCLAMP BSN ROSC 20 AGND 19 AGND 18 BSP 17 PVCC 16 OUTN OUTP 15 OUTN OUTP 14 PGND PGND PVCC C12 220 pF C4 1 µF C11 1 µF R1 120 kΩ R3 51 Ω C9 0.22 µF VCC C6 1 µF 13 D1 D2 L1 L2 (Ferrite (Ferrite Bead) Bead) C15 1 nF C14 1 nF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2004, Texas Instruments Incorporated TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 AVAILABLE OPTIONS PACKAGED DEVICES TA TSSOP (PW) (1) -40°C to 85°C (1) TPA3007D1PW The PW package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA3007D1PWR). PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 INN INP GAIN0 GAIN1 SHUTDOWN PGND VCLAMP BSN PVCC OUTN OUTN PGND 24 23 22 21 20 19 18 17 16 15 14 13 VCC VREF BYPASS COSC ROSC AGND AGND BSP PVCC OUTP OUTP PGND Terminal Functions TERMINAL NAME NO. AGND 18, 19 I/O DESCRIPTION Analog ground terminal BSN 8 I Bootstrap terminal for high-side gate drive of negative BTL output (connect a 0.22-µF capacitor with a 51-Ω resistor in series from OUTN to BSN) BSP 17 I Bootstrap terminal for high-side gate drive of positive BTL output (connect a 0.22-µF capacitor with a 51-Ω resistor in series from OUTP to BSP) BYPASS 22 I Connect 1-µF capacitor to ground for BYPASS voltage filtering COSC 21 I Connect a 220-pF capacitor to ground to set oscillation frequency GAIN0 3 I Bit 0 of gain control (see Table 2 for gain settings) GAIN1 4 I Bit 1 of gain control (see Table 2 for gain settings) INN 1 I Negative differential input INP 2 I Positive differential input OUTN 10, 11 O Negative BTL output, connect Schottky diode from PGND to OUTN for short-circuit protection OUTP 14, 15 O Positive BTL output, connect Schottky diode from PGND to OUTP for short-circuit protection PGND 6, 12, 13 PVCC 9, 16 I High-voltage power supply (for output stages) ROSC 20 I Connect 120 kΩ resistor to ground to set oscillation frequency SHUTDOWN 5 I Shutdown terminal (active low), TTL compatible, 21-V compliant VCC 24 I Analog high-voltage power supply VCLAMP 7 O Connect 1-µF capacitor to ground to provide reference voltage for H-bridge gates VREF 23 O 5-V internal regulator for control circuitry (connect a 0.1-µF to 1-µF capacitor to ground) 2 Power ground TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 Functional Block Diagram VREF AGND VCC VREF VCLAMP VCC Clamp Reference BSN PVCC + _ Gain Adjust INN Deglitch Logic Gate Drive OUTN _ PGND + _ + BSP + _ PVCC + Gain Adjust INP _ _ + Deglitch Logic Gate Drive OUTP PGND SD SHUTDOWN GAIN1 2 GAIN0 Gain Biases and References Start-Up Protection Logic Ramp Generator COSC ROSC BYPASS Thermal Short-Circuit Detect VCC OK ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage: VCC, PVCC -0.3 V to 21 V ≥7 Ω Load impedance, RL Input voltage SHUTDOWN -0.3 V to VCC + 0.3 V GAIN0, GAIN1 -0.3 V to 5.5 V INN, INP -0.3 V to 7 V Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA -40°C to 85°C Operating junction temperature range, TJ -40°C to 150°C Storage temperature range, Tstg -65°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA≤ 25°C PW (1) 1.43 W DERATING FACTOR 11.45 mW/°C (1) TA = 70°C TA = 85°C 0.915 W 0.744 W Based on High-K board 3 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 RECOMMENDED OPERATING CONDITIONS Supply voltage, VCC, PVCC RL≥ 7.0Ω (1) Load impedance, RL MIN MAX 8 18 GAIN0, GAIN1, SHUTDOWN Low-level input voltage, VIL GAIN0, GAIN1, SHUTDOWN Operating free-air temperature, TA 2 40 Operating junction temperature, TJ (2) (2) V Ω 7.0 High-level input voltage, VIH (1) UNIT V 0.8 V 85 °C 125 °C The TPA3007D1 must not be used with any speaker or load (including speaker with output filter) that could vary below 7.0Ω over the audio frequency band. Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device. The junction temperature is controlled by the thermal design of the application and should be carefully considered in high power dissipation applications. See the thermal considerations section on page 14 for recommendations on improving the thermal performance of your application. ELECTRICAL CHARACTERISTICS TA= 25°C, PVCC = VCC = 12 V (unless otherwise noted) PARAMETERS TEST CONDITIONS |VOS| Output offset voltage (measured differentially) VI = 0 V, AV = 12 dB, 18, 23.6 dB PSRR Power supply rejection ratio PVCC = 11.5 V to 12.5 V |IIH| High-level input current PVCC = 12 V, VI = PVCC |IIL| Low-level input current PVCC = 12 V, VI = 0 V MIN 50 VI = 0 V, AV = 36 dB 100 73 ICC Supply current SHUTDOWN = VCC, VCC = 18 V,PO = 6.5 W, RL = 8Ω ICC(SD) Supply current, shutdown mode SHUTDOWN = 0.8 V fs Switching frequency ROSC = 120 kΩ, COSC = 220 pF rds(on) Output transistor on resistance (total) IO = 1 A, TJ = 25°C Gain 1 µA 15 mA 0.42 1 µA A 2 250 µA kHz 1.4 Ω GAIN1 = 0.8 V, GAIN0 = 0.8 V 10.9 12 12.8 dB GAIN1 = 0.8 V, GAIN0 = 2 V 17.1 18 18.5 dB GAIN1 = 2 V, GAIN0 = 0.8 V 23 23.6 24.3 dB 33.9 36 36.5 dB GAIN1 = 2 V, GAIN0 = 2 V 4 8 mV dB 1 SHUTDOWN = 2.0 V, No load G TYP MAX UNIT TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 OPERATING CHARACTERISTICS PVCC = VCC = 12 V, Gain = 12 dB, TA= 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Continuous output power at 10% THD+N f = 1 kHz, RL = 8Ω 6.5 Continuous output power at 1% THD+N f = 1 kHz, RL = 8Ω 5.0 THD + N Total harmonic distortion plus noise PO = 3.25 W, RL = 8 Ω , f = 1 kHz BOM Maximum output power bandwidth THD = 1% 20 kHz kSVR Supply ripple rejection ratio f = 1 kHz, C(BYPASS) = 1 µF 70 dB SNR Signal-to-noise ratio PO = 3.25 W, RL = 8 Ω 97 dB C(BYPASS) = 1 µF, f = 20 Hz to 22 kHz, No weighting filter used 86 µV(rms) 81 dBV C(BYPASS) = 1 µF, f = 20 Hz to 22 kHz, A-weighted filter 66 µV(rms) 84 dBV >23 kΩ PO Vn Noise output voltage Zi Input impedance W 0.19% See Table 2, page 14 OPERATING CHARACTERISTICS PVCC = VCC = 18 V, Gain = 12 dB, TA= 25°C (unless otherwise noted) PARAMETER THD + N Total harmonic distortion plus noise TEST CONDITIONS PO = 3.25 W, RL = 8 Ω, f = 1 kHz MIN TYP MAX UNIT 0.16% BOM Maximum output power bandwidth THD = 1% 20 kHz kSVR Supply ripple rejection ratio f = 1 kHz, CBYPASS = 1 µF 70 dB SNR Signal-to-noise ratio PO = 3.25 W, RL = 8Ω 97 dB C(BYPASS) = 1 µF, f = 20 Hz to 20 kHz, No weighting filter used 86 µV(rms) 81 dBV C(BYPASS) = 1 µF, f = 20 Hz to 22 kHz, A-weighted filter 66 µV(rms) 84 dBV >23 kΩ Vn Zi Noise output voltage Input impedance See Table 2, page 14 5 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURE Efficiency vs Output power 1 PO Output power vs Supply Voltage 2 ICC Supply current ICC(SD) Shutdown current 3 vs Supply voltage THD+N Total harmonic distortion + noise kSVR Supply voltage rejection ratio 4 vs Output power 5, 6 vs Frequency 7, 8 9 Gain and phase vs Frequency CMRR Common-mode rejection ratio VIO Input offset voltage 10 11 vs Common-mode input voltage EFFICIENCY vs OUTPUT POWER MAXIMUM OUTPUT POWER vs SUPPLY VOLTAGE 90 10 8Ω 9 Maximum Output Power − W 80 Efficiency − % 70 60 50 40 VCC = 12 V 30 20 6 8 10% THD+N 7 Thermally Limited 6 5 1% THD+N 4 3 2 10 0 12 1 0 4 8 12 16 20 0 PO − Output Power − W 8 9 10 11 12 13 14 15 VCC − Supply Voltage − V Figure 1. Figure 2. 16 17 18 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 SUPPLY CURRENT vs SUPPLY VOLTAGE SHUTDOWN CURRENT vs SUPPLY VOLTAGE 11 5 ICC(SD) - Shutdown Current - µA ICC - Supply Current - mA SHUTDOWN = 0.8 V 10 9 8 7 6 4 3 2 1 0 8 10 12 14 16 18 8 VCC - Supply Voltage - V 12 14 16 Figure 3. Figure 4. TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER 10 THD+N − Total Harmonic Distortion + Noise − % VCC = 12 V RL = 8 Ω Gain = +12 dB f = 1 kHz f = 20 Hz 1 f = 20 kHz 0.1 0.1 18 VCC - Supply Voltage - V 10 THD+N − Total Harmonic Distortion + Noise − % 10 1 PO − Output Power − W Figure 5. 10 VCC = 12 V RL = 8 Ω Gain = +36 dB f = 20 Hz 1 f = 20 kHz 0.1 0.01 0.1 f f==11kHz kHz 1 10 PO − Output Power − W Figure 6. 7 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1 PO = 4 W 0.1 PO = 2 W 0.01 20 100 1k 10 k PO = 2 W VCC = 18 V RL = 8 Ω 0.01 20 20 k 100 1k f − Frequency − Hz Figure 7. Figure 8. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY GAIN and PHASE vs FREQUENCY 14 C(Bypass) = 1 µF RL = 8 Ω 10 0 10 -10 -70 ° VCC = 8 V 8 -20 Phase -30 6 VDD = 15 V -40 4 -80 2 -90 20 100 20 k 20 Gain -60 10 k 30 12 Gain - dB kSVR - Supply Voltage Rejection Ratio - dB PO = 5 W 0.1 f − Frequency − Hz -50 1k f - Frequency - Hz Figure 9. 8 PO = 0.5 W PO = 0.5 W 10k 0 20 -50 -60 VCC = 8 V RL = 8 Ω Gain = 12 dB 100 -70 1k 10k f - Frequency - Hz Figure 10. -80 100k Phase - VCC = 12 V RL = 8 Ω THD+N − Total Harmonic Distortion − % THD+N − Total Harmonic Distortion − % 1 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 COMMON-MODE REJECTION RATIO vs FREQUENCY INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 6 VCC = 8 V to 18 V RL = 8 Ω 5 -41 VIO - Input Offset Voltage - mV CMRR - Common-Mode Rejection Ratio - dB -40 -42 -43 -44 VCC = 8 V to 18 V 4 3 2 1 0 -1 -2 -45 -3 -46 20 100 1k f - Frequency - Hz Figure 11. 10 k -4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VIC - Common-Mode Input Voltage - V Figure 12. 9 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 APPLICATION INFORMATION APPLICATION CIRCUIT U1 TPA3007D1 C1 IN− 0.47 µF 1 2 IN+ C2 0.47 µF 3 GAIN SELECT 4 GAIN SELECT 5 SHUTDOWN CONTROL 6 7 C10 1 µF VCC R2 C8 0.22 µF 51 Ω 8 9 10 C7 10 µF C5 1 µF 11 12 VCC INN VCC INP VREF GAIN0 BYPASS GAIN1 COSC SHUTDOWN ROSC PGND AGND VCLAMP AGND 24 23 22 C4 1 µF C3 1 µF 20 C11 1 µF C12 220 pF R1 19 120 kΩ 21 18 BSN BSP PVCC PVCC OUTN OUTP OUTN OUTP PGND PGND 17 R3 16 51 Ω 15 L1 (Ferrite Bead) C15 1 nF C14 1 nF VCC C6 1 µF 14 13 D2 L2 (Ferrite Bead) C9 0.22 µF D1 L1, L2: Fair-Rite, Part Number 2512067007Y3 D1, D2: Diodes, Inc., Part Number B130 Figure 13. Typical Application Circuit CLASS-D OPERATION This section focuses on the class-D operation of the TPA3007D1. TRADITIONAL CLASS-D MODULATION SCHEME The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 14. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss, thus causing a high supply current. 10 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 APPLICATION INFORMATION (continued) OUTP OUTN +12 V Differential Voltage Across Load 0V –12 V Current Figure 14. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an Inductive Load With No Input TPA3007D1 MODULATION SCHEME The TPA3007D1 uses a modulation scheme that still has each output switching from ground to VCC. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load. (See Figure 15). 11 TPA3007D1 SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 www.ti.com APPLICATION INFORMATION (continued) OUTP OUTN Differential Voltage Across Load Output = 0 V +12 V 0V –12 V Current OUTP OUTN Differential Voltage Output > 0 V +12 V 0V Across Load –12 V Current Figure 15. The TPA3007D1 Output Voltage and Current Waveforms Into an Inductive Load DRIVING THE OUTPUT INTO CLIPPING The output of the TPA3007D1 may be driven into clipping to attain a higher output power than is possible with no distortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power into the load may be calculated with Equation 1. P O(10% THD) P O(1% THD) 1.25 (1) OUTPUT FILTER CONSIDERATIONS A ferrite bead filter (shown in Figure 16) should be used in order to pass FCC and/or CE radiated emissions specifications and if a frequency sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies. Use an additional LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires (greater than 11 inches) from the amplifier to the speaker, as shown in Figure 17. 12 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 APPLICATION INFORMATION (continued) Ferrite Chip Bead OUTP 1 nF 7 Ω or Greater Ferrite Chip Bead OUTN 1 nF Figure 16. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3) Ferrite Chip Bead 33 µH OUTP 1 nF Ferrite Chip Bead 0.47 µF 8Ω 33 µH OUTN 1 nF 0.47 µF Figure 17. Typical LC Output Filter for 8-Ω Speaker, Cutoff Frequency of 41 kHz SHORT-CIRCUIT PROTECTION The TPA3007D1 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on the outputs, the part immediately disables the output drive and enters into shutdown mode. This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high state for normal operation. This clears the short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the protection circuitry again activates. Two Schottky diodes are required to provide short-circuit protection. The diodes should be placed as close to the TPA3007D1 as possible, with the anodes connected to PGND and the cathodes connected to OUTP and OUTN as shown in the application circuit schematic. The diodes should have a forward voltage rating of 0.5V at a minimum of 1A output current and a dc blocking voltage rating of at least 30 V. The diodes must also be rated to operate at a junction temperature of 150°C. If short-circuit protection is not required, the Schottky diodes may be omitted. THERMAL PROTECTION Thermal protection on the TPA3007D1 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction. 13 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 THERMAL CONSIDERATION: OUTPUT POWER AND RECOMMENDED AMBIENT TEMPERATURE To calculate the maximum ambient temperature, the following equation may be used: T T θ P A(max) J JA Dissipated where : T 125°C J θ JA 1 1 87.3°CW 0.01145 derating factor (2) (The derating factor for the 24-pin PW package is given in the dissipation rating table.) To estimate the power dissipation, the following equation may be used: P Dissipated P O(average) 1 –1 Efficiency Efficiency 85% for an 8- load (3) Example. What is the maximum ambient temperature for an application that requires the TPA3007D1 to drive 3 W into an 8-Ω speaker? PDissipated = 3 W x ((1 / 0.85) - 1) = 0.529 W TAmax = 125°C - (87.3°C/W x 0.529 W) = 78.8°C This calculation shows that the TPA3007D1 can drive 3 W into an 8-Ω speaker up to the absolute maximum ambient temperature rating of 78.8°C, which must never be exceeded. GAIN SETTING VIA GAIN0 AND GAIN1 INPUTS The gain of the TPA3007D1 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 2 are realized by changing the taps on the input resistors inside the amplifier. This causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance may shift by 30% due to shifts in the actual resistance of the input resistors. For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 23 kΩ, which is the absolute minimum input impedance of the TPA3007D1. At the lower gain settings, the input impedance could increase as high as 313 kΩ. Table 2. Gain Settings AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ) TYP TYP 12 241 1 18 168 1 0 23.6 104 1 1 36 33 GAIN1 GAIN0 0 0 0 INPUT RESISTANCE Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency also changes by over six times. 14 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 Zf Ci IN Input Signal Zi The -3-dB frequency can be calculated using Equation 4. Use Table 2 for Zi values. 1 f 2 Z iCi (4) INPUT CAPACITOR, Ci In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a high-pass filter with the corner frequency determined in Equation 5. -3 dB fc 1 2 Zi C i fc (5) The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider the example where Zi is 241 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 5 is reconfigured as Equation 6. 1 Ci 2 Z i f c (6) In this example, Ci is 33 nF, so one would likely choose a value of 0.1 µF, as this value is commonly used. If the gain is known and will be constant, use Zi from Table 2 to calculate Ci. A further consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. POWER SUPPLY DECOUPLING The TPA3007D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 µF placed as close as possible to the device VCC lead works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio power amplifier is recommended. 15 TPA3007D1 SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 www.ti.com BSN AND BSP CAPACITORS The full H-bridge output stage uses only NMOS transistors. It therefore requires bootstrap capacitors for the high side of each output to turn on correctly. A 0.22-µF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 0.22-µF capacitor must be connected from OUTP to BSP, and one 0.22-µF capacitor must be connected from OUTN to BSN. (See Figure 13.) BSN AND BSP RESISTORS To limit the current when charging the bootstrap capacitors, a resistor with a value of 51 Ω (+/-10% maximum) must be placed in series with each bootstrap capacitor. The current is limited to less than 500 µA. VCLAMP CAPACITOR To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, an internal regulator clamps the gate voltage. A 1-µF capacitor must be connected from VCLAMP (pin 7) to ground and must be rated for at least 25 V. The voltage at VCLAMP (pin 7) varies with VCC and may not be used for powering any other circuitry. MIDRAIL BYPASS CAPACITOR The midrail bypass capacitor (C11 of Figure 13) is the most critical capacitor and serves several important functions. During start-up or recovery from shutdown mode, CBYPASS determines the rate at which the amplifier starts up. The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and THD+N. Bypass capacitor (C11) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for the best THD noise, and depop performance. The bypass capacitor must be a value greater than the input capacitors for optimum depop performance. VREF DECOUPLING CAPACITOR The VREF terminal (pin 23) is the output of an internally-generated 5-V supply, used for the oscillator and gain setting logic. It requires a 0.1-µF to 1-µF capacitor to ground to keep the regulator stable. The regulator may not be used to power any additional circuitry. DIFFERENTIAL INPUT The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3007D1 EVM with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3007D1 with a single-ended source, ac ground the INN input through a capacitor and apply the audio signal to the INP input. In a single-ended input application, the INN input should be ac-grounded at the audio source instead of at the device input for best noise performance. SWITCHING FREQUENCY The switching frequency is determined using the values of the components connected to ROSC (pin 20) and COSC (pin 21) and may be calculated with the following equation: 6.6 fs ROSC C OSC (7) The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for ROSC and COSC. SHUTDOWN OPERATION The TPA3007D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state, ICC(SD) = 1 µA. SHUTDOWN should never be left unconnected, because amplifier operation would be unpredictable. 16 TPA3007D1 www.ti.com SLOS418A – SEPTEMBER 2003 – REVISED DECEMBER 2004 Ideally, the device should be held in shutdown when the system powers up and brought out of shutdown once any digital circuitry has settled. However, if SHUTDOWN is to be left unused, the terminal may be connected directly to VCC. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor. PRINTED-CIRCUIT BOARD (PCB) LAYOUT Because the TPA3007D1 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance. • Decoupling capacitors — As described in the Power Supply Decoupling section, the high-frequency 0.1-uF decoupling capacitors should be placed as close to the PVCC (pin 9 and pin 16) and VCC (pin 24) terminals as possible. The BYPASS (pin 22) capacitor, VREF (pin 23) capacitor, and VCLAMP (pin 7) capacitor should also be placed as close to the device as possible. The large (10 uF or greater) bulk power supply decoupling capacitor should be placed near the TPA3007D1. • Grounding — The VCC (pin 24) decoupling capacitor, VREF (pin 23) capacitor, BYPASS (pin 22) capacitor, COSC (pin 21) capacitor, and ROSC (pin 20) resistor should each be grounded to analog ground (AGND, pin 18 and pin 19). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground (PGND, pin 12 and pin 13). Analog ground and power ground should be connected as a central ground connection or star ground for the TPA3007D1. • Output filter — The ferrite filter (Figure 16) should be placed as close to the output terminals (pins 10, 11, 14, and 15) as possible for the best EMI performance. The LC filter (Figure 17) should be placed close to the ferrite filter. The capacitors used in both the ferrite and LC filters should be grounded to power ground. For an example layout, refer to the TPA3007D1 Evaluation Module (TPA3007D1EVM) User Manual, TI literature number SLOU164, available on the TI web site at http://www.ti.com. For further layout information, refer to Layout Guidelines for TPA300x Series Parts, TI literature number SLOA103, also available on the TI website. 17 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPA3007D1PW ACTIVE TSSOP PW 24 60 TBD CU NIPDAU Level-2-239C-1 YEAR TPA3007D1PWR ACTIVE TSSOP PW 24 2000 TBD CU NIPDAU Level-2-239C-1 YEAR TPA3007D1PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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