CMCPCI102B CompactPCI® Backplane Interface Features • • • • • • • • • Product Description CompactPCI® standards compliant Allows CompactPCI System Cards to be used in any Slot Provides termination for up to ten channels Provides a series switch in each channel Supports hot-swap capability Very low capacitance load on each line Industrial temperature range 28-pin TSSOP package Lead-free version available The CMCPCI102BT/BR is a 10-channel backplane interface/termination IC specifically designed for CompactPCI redundant system-slot cards. The CMCPCI102BT/BR allows CompactPCI boards to interface to the backplane and provides the versatility to use system cards in any slot (system or peripheral). Per the CompactPCI specification, the CMCPCI102BT/ BR provides a 10Ω termination resistor for each channel to terminate the transmission line stub on the board. An integral series switch and associated control signal (SW_EN) permits connection/disconnection of the channel, so that the device side of the circuit may be isolated from the backplane side. The CompactPCI standard requires system boards to be hot-swappable. To accommodate this requirement, the CMCPCI102BT/BR features a switched 10kΩ resistor connected to the 1V Precharge Supply Voltage. If the precharge enable pin (P_EN) is asserted, then the 10kΩ pull-up resistors are connected to precharge the circuits. Applications • • • • • • • Redundant System CompactPCI® cards Hot-swap CompactPCI cards Industrial PCs Telecom/Datacom equipment Instrumentation Computer Telephony Real-time machine control In addition, a system board requirement mandates either a 1.0kΩ pull-up resistor or a 2.7kΩ resistor connected to VIO. CompactPCI slot cards must work in either 3.3V or 5V systems, hence the need for both 2.7kΩ and 1kΩ resistors. If the 3_EN pin is logic high, the 2.7kΩ resistor is used as the pull-up. If the 5_EN pin is logic high, the 1kΩ resistor is used. The CMCPCI102BT/BR integrates all these functions in a low-profile 28-pin TSSOP package and is available with optional lead-free finishing. Simplified Electrical Schematic 1V 3_EN VIO 5_EN For all Enable signals: Logic 0 = switch open Logic 1 = switch closed SW_EN SWPU1 *One of 10 parallel channels is shown. SWPU2 SWPU3 RPU2 2.7kΩ RPU3 1kΩ P_EN RPU1 10kΩ A1-A10* RS Backplane Side SWS 10Ω CompactPCI Device Side B1-B10* © 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 1 CMCPCI102B PACKAGE / PINOUT DIAGRAM Top View A1 1 28 B1 A2 2 27 B2 A3 3 26 B3 A4 4 25 B4 A5 5 24 B5 1V 6 23 VIO P_EN 7 22 5_EN GND 8 21 3_EN CAP 9 20 SW_EN A6 10 19 B6 A7 11 18 B7 A8 12 17 B8 A9 13 16 B9 A10 14 15 B10 28-pin TSSOP Note: This drawing is not to scale. PIN DESCRIPTIONS PIN(S) NAME DESCRIPTION 1-5 A1 - A5 The backplane-side input signals for channels 1 through 5, respectively. 10-14 A6 - A10 The backplane-side input signals for channels 6 through 10, respectively. 24-28 B1 - B5 The device-side connection for channels 1 through 5, respectively. 15-19 B6 - B10 The device-side connection for channels 6 through 10, respectively. 6 1V A precharge supply voltage input for all channels. This voltage can be less than or equal to VIO. 7 P_EN The precharge enable input which controls the precharge pull-up resistors. When this active high control signal is set to ’1’, the precharge of all channels is enabled. 8 GND The ground voltage reference for the CMCPCI102BT/BR. 9 CAP A capacitor must be placed from this pin to GND. The recommended value is 0.01µF,16V. 20 SW_EN The series switch enable input. When this active high control signal is set to ’1’, the series switch between the channel’s backplane-side terminal and device-side terminal is closed. When this signal is cleared to ’0’, the switch is open. 21 3_EN The enable signal for the device-side channel pull-up mechanism when 3.3V is the supply voltage. When this active high control signal is set to ’1’, the 2.7kΩ pull-up resistor which pulls up the channel to the supply rail is engaged. Otherwise, this pin should be set to ’0’. 22 5_EN The enable signal for the device-side channel pull-up mechanism when 5V is the supply voltage. When this active high control signal is set to ’1’, the 1kΩ pull-up resistor which pulls up the channel to the supply rail is engaged. Otherwise, this pin should be set to ’0’. 23 VIO The positive supply voltage for the CMCPCI102BT/BR. Either 3.3V or 5V may be used. © 2005 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 02/28/05 CMCPCI102B Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish Pins Package Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking 28 TSSOP CMCPCI102BT CPCI102B CMCPCI102BR CPCI102BR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VIO (supply voltage) -0.5 to +6 V -0.5 to (VIO+0.5) -0.5 to (VIO+0.5) -0.5 to (VIO+0.5) V V V +2000 V Storage Temperature Range -65 to +150 °C Operating Temperature Range (Ambient) Pin Voltages 1V, P_EN, 3_EN, 5_EN, SW_EN A1-A10 B1-B10 ESD Withstand Voltage Human Body Model, MIL-STD-883D, Method 3015 (Notes 1, 2) -40 to +85 °C DC Power per Resistor 62 mW Package Power Rating 1 W Note 1: ESD is applied to input / output pins with respect to GND, one at a time; unused pins are left open. Note 2: This parameter guaranteed by design. STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS VIO (supply voltage) 3 to 5.5 V Pin Voltages P_EN, 3_EN, 5_EN, SW_EN, 1V A1-A10 B1-B10 0 to VIO 0 to VIO 0 to VIO V V V Ambient Operating Temperature Range -40 to +85 °C © 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 3 CMCPCI102B Specifications (Cont’d) ELECTRICAL OPERATING CHARACTERISTICS(NOTE 1) SYMBOL PARAMETER CONDITIONS RS1 Series Resistance through RS RS2 RPU1 TOLRPU2 TOLRPU3 MIN TYP MAX UNITS A to B; switch SWS closed; TA=25°C 5 10 15 Ω Series Resistance through RS A to B; switch SWS open; TA=25°C 1 Resistance of RPU1 pull-up TA=25°C Resistance Tolerance (RPU2 and RPU3) TA=25°C MΩ 9.5 18 kΩ +5 % TCRPU Temperature Coefficient of Resistance (RPU1, RPU2, RPU3) C1 Capacitance on backplane side (A side) of series resistor RS C2 Capacitance on device side (B side) of series resistor RS and series switch SWS VIL Logic Low Input Voltage to P_EN, 3_EN, 5_EN, SW_EN -0.5 [VIO] x 0.3 V VIH Logic High Input Voltage to P_EN, 3_EN, 5_EN, SW_EN [VIO] x 0.7 [VIO] + 0.5 V ILEAK Leakage Current into P_EN, 3_EN, 5_EN, SW_EN +1 +10 µA IGND Supply Current for internal circuits (measured at GND pin) 0.25 1 mA tPLH Switch SWS closure delay from the low-to-high transition of SW_EN Note 2, ’CAP’ pin capacitor=0.01µF 14 ms tPHL Switch SWS delay from the high-to- Note 2, ’CAP’ pin capacitor=0.01µF low transition of SW_EN 12 µs tPPU Propagation delay for pull-up switches SWPU1, SWPU2, and SWPU3, all transitions -100 ppm/°C Measured @ 66MHz, 0VDC, SW_EN=0V; Note 2 1.9 pF Measured @ 66MHz, 0VDC, VIO=5V, 5_EN=5V SW_EN=0V; Note 2 4.2 pF GND < V < VIO Note 2 10 ns Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Note 2: This parameter is guaranteed by design; it is not tested 100%. © 2005 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 02/28/05 CMCPCI102B Performance Information CAP Pin Capacitance Resistance Variation with Input Voltage The series resistance RS varies with input voltage and supply voltage, as shown in Figure 1. Variation of 10R Resistor with I/O Voltage, T=25'C The time required to open and close the series switch, SWs, varies according to how much capacitance is present on the CAP pin. 15 14 Vcc5.5 13 Vcc3.0 The minimum usable value is 200pF, placed close to the pins. A 0.01uF, 16V capacitor is recommended. See Figure 3 and Figure 4 for variation of switch on/off times vs. capacitance. 12 Resistance [ Ω ] Some external capacitance is necessary to prevent the voltage on the CAP pin from falling during sustained data transfers through the device. This ensures that the logic 1 level does not degrade. 11 10 9 8 Switch ON Time vs. CAP Capacitor Value 7 6 16 5 0 1 2 3 4 5 6 14 I/O Voltage [ V ] Figure 1. Resistance Variation vs. Input Voltage The series resistance RS also varies with temperature, as shown in Figure 2. SWs Closing Tim e [mS] Resistance Variation with Temperature 12 Temperature Variation of 10R Resistor 10 8 6 4 2 15 0 0 2000 4000 6000 8000 10000 12000 Capacitor Value on CAP Pin [pF] 13 VCC5VIN0 12 VCC3VIN0 Figure 3. Switch ON Time vs. CAP Capacitor Value VCC5VIN5 VCC3VIN3 11 Switch OFF Time vs. CAP Capacitor Value 10 14 9 8 12 7 10 6 5 -40 -20 0 20 40 60 80 100 Temperature [ oC ] CONDITIONS: Curve VCC3VIN0: Curve VCC3VIN3: Curve VCC5VIN0: Curve VCC5VIN5: VIO = 3.0V VIO = 3.0V VIO = 5.5V VIO = 5.5V channel voltage = 0.0V channel voltage = 3.0V channel voltage = 0.0V channel voltage = 5.5V SWs Opening Tim e [µS] Resistance [ Ω ] 14 8 6 4 2 0 0 2000 4000 6000 8000 10000 12000 Capacitor Value on CAP Pin [pF] Figure 2. Resistance Variation vs. Temperature Figure 4. Switch OFF Time vs. CAP Capacitor Value © 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 5 CMCPCI102B Performance Information (cont’d) Capacitance Variation with Frequency The A-side and B-side capacitances, C1 and C2, will vary with frequency. The backplane capacitance, C1, is very linear over a wide frequency range. Figure 5 shows a plot of input line A3 (pin 3), measured with SW_EN=0V and VIO=5V. Figure 5. C1 (Backplane-side) Capacitance Variation vs. Frequency The CompactPCI device side of the CMCPCI102BT/ BR has a fairly low capacitance (C2) at 66MHz, but it is higher at lower frequencies. Figure 6 shows a plot of output line B3 (pin 26), measured at the worst-case (for capacitance) conditions of SW_EN=0V, 5_EN=0V, 3_EN=0V and VIO=5V. The increased capacitance at low frequencies is due to the parasitic capacitance of the switches connected to the pull-up resistors. At high frequencies, this parasitic capacitance is decoupled by the pull-up resistors. Figure 6. C2 (Device-side) Capacitance Variation vs. Frequency © 2005 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 02/28/05 CMCPCI102B Application Information Board Layout Recommendations The CMCPCI102BT/BR devices should be located on the board as close as possible to the CompactPCI connector. Whether a signal is terminated or not depends upon application, as shown in the following table: SIGNAL(S) SYSTEM SLOT BOARDS 32-Bit 64-Bit AD0-AD31 terminate terminate C/BE0#-C/BE3# terminate terminate PAR terminate terminate FRAME# terminate terminate IRDY# terminate terminate TRDY# terminate terminate STOP# terminate terminate LOCK# terminate terminate DEVSEL# terminate terminate PERR# terminate terminate SERR# terminate terminate RST# terminate terminate REQ64# terminate terminate ACK64# terminate terminate INTA#, INTB#, INTC#, INTD# (if used) terminate terminate AD32-AD63 N/A terminate C/BE4#-C/BE7 N/A terminate PAR64 N/A terminate * * Figure 7 shows a 64-bit system board connection between the CMCPCI102BT/BR termination and the CompactPCI 5-row connector (2 mm pitch) labeled A to E (row F is Ground). The System slot should have signal lengths not exceeding 63.5 mm (2.5 inches). To minimize trace length, it is recommended that the CMCPCI102BT/BRs be placed on alternate sides of the PC board. The configuration shown illustrates a fully-terminated 64-bit board utilizing 10 CMCPCI102BT/BR devices. Some applications (e.g. 32-bit boards) do not require all lines to be terminated, per the above table. * * The CMCPCI102BT/BR resistors have a very low TCR (typically -100ppm/°C) so that resistance will not fluctuate over temperature. Buffers are implemented on P_EN, 5_EN and 3_EN inputs to ensure that switches turn on and off completely. A typical system slot card may use 10 CMCPCI102BT/ BR devices to replace 10 10-bit FET bus switches and 76 4-resistor packs (0805 form factor), thus providing significant reduction in both component count and assembly costs. At the same time this highly integrated solution improves reliability and manufacturing efficiency, saves board area for space-critical designs, and satisfies CompactPCI height requirements. * Placed on bottom side of PC board * Figure 7. Schematic for 64-bit System Board © 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 7 CMCPCI102B Mechanical Details TSSOP Mechanical Specifications Mechanical Package Diagrams CMCPCI102BT/BR devices are supplied in 28-pin TSSOP packages. Dimensions are shown below. For complete information on the TSSOP-28 package, see the California Micro Devices TSSOP Package Information document. TOP VIEW D 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PACKAGE DIMENSIONS Package H TSSOP Pins 28 Dimensions Millimeters Inches Min Max Min Max A — 1.10 — 0.0433 A1 0.05 0.15 0.002 0.006 B 0.19 0.30 0.0075 0.0118 C 0.09 0.20 0.0035 0.0079 D 9.60 9.80 0.378 0.386 E e E Pin 1 Marking 4.30 4.50 0.169 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SIDE VIEW A SEATING PLANE A1 B 0.177 e 0.0256 BSC H 6.25 6.50 0.246 0.256 L 0.50 0.70 0.020 0.028 # per tube 50 pieces* # per tape and reel 1000 pieces END VIEW C L Controlling dimension: millimeters * This is an approximate number which may vary. Package Dimensions for TSSOP-28 © 2005 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 02/28/05