PACSZ1284 IEEE 1284 Parallel Port ESD/EMI/Termination Network Features Product Description • • The PACSZ1284 combines EMI filtering, ESD protection, and signal termination in a single QSOP package for parallel port interfaces complying to the IEEE 1284 standard. 17 EMI filters 17 ESD protectors yielding protection to 30kV contact discharge, per IEC 61000-4-2 specification 17 terminators with choice of resistor values 28-pin QSOP package Lead-free version available • • • The PACSZ1284 provides a complete parallel port termination solution. It integrates the equivalent of 60 discrete components, making it ideal for space critical applications. The pins of the device which connect to the parallel port are protected to 30kV contact discharge, well beyond Level 4 of the IEC 61000-4-2 specification. All other pins are ESD-protected for contact discharges up to 8kV per IEC 61000-4-2. Applications • Parallel Ports of PCs, printers, peripherals, and Set-Top Boxes There are three available values for pull-up resistor R1. For the PACSZ1284-01, R1 = 1kΩ; for the PACSZ128402, R1 = 2.2kΩ; for the PACSZ1284-04, R1 = 4.7kΩ. P/Active® technology provides high reliability and low cost through manufacturing efficiency. the PACSZ1284 is silicon-based and has the same reliability characteristics as today’s integrated circuits. Electrical Schematic 28 R1 27 R1 R1 PACSZ1284-01 R1 = 1kΩ R2 = 33Ω C = 150pF 26 R1 25 R1 24 R1 R2 C C 1 C C 2 C 23 R1 R2 C 3 4 22 21 R1 R2 C 20 R1 R2 C 5 PACSZ1284-02 R1 = 2.2kΩ R2 = 33Ω C = 150pF R1 18 R1 R2 C 6 19 R1 17 R1 R2 C 7 PACSZ1284-04 R1 = 4.7kΩ R2 = 33Ω C = 150pF C 8 R1 R2 C 9 R1 16 C 10 15 R1 R2 C 11 C 12 R1 R2 C 13 C 14 © 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 1 PACSZ1284 PACKAGE / PINOUT DIAGRAM CAP-FILTERED 1 28 CAP-FILTERED CAP-FILTERED 2 27 CAP-FILTERED SUPERCHIP SIDE SERIES-TERMINATED 3 26 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 4 25 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 5 24 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 6 23 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 7 22 GND CAP-FILTERED 8 21 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 9 20 VCC CAP-FILTERED 10 19 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 11 18 CONNECTOR SIDE SERIES-TERMINATED CAP-FILTERED 12 17 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 13 16 CONNECTOR SIDE SERIES-TERMINATED SUPERCHIP SIDE SERIES-TERMINATED 14 15 CAP-FILTERED Note: This drawing is not to scale. 28-pin QSOP PIN DESCRIPTIONS LEADS NAME DESCRIPTION 1,2,8,10, 12,15, 27,28 Capacitor-filtered 3-7, 9,11, 13,14 Super I/O Chip side series-terminated IEEE 1284 signals on the Super I/O Chip side which require series termination. 16-19, 21, 23-26 Parallel Port connector side series-terminated IEEE 1284 signals on the Parallel Port Connector side which require series termination. 20 VCC Supply rail for the device 22 GND Ground reference for the device IEEE 1284 signals which require no series termination. Ordering Information STANDARD VALUES RC Code R1 (Ω) R2 (Ω) C (pF) 01 1.0k 33 150 02 2.2k 33 150 04 4.7k 33 150 PART NUMBERING INFORMATION Lead-free Finish Standard Finish Ordering Part Ordering Part RC Code Pins Package Number1 Part Marking Number1 Part Marking 01 28 QSOP PACSZ128401Q PACSZ128401Q PACSZ128401QR PACSZ128401QR 02 28 QSOP PACSZ128402Q PACSZ128402Q PACSZ128402QR PACSZ128402QR 28 QSOP PACSZ128404Q PACSZ128404Q PACSZ128404QR PACSZ128404QR 04 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2003 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 09/15/03 PACSZ1284 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS 5.5 V Input Voltage Range, no clamping -0.4 to 5.5 V Storage Temperature Range -40 to +150 °C VCC Voltage Power Dissipation per Resistor 0.1 W Package Power Dissipation 1.0 W RATING UNITS 5.0 V -40 to +85 °C STANDARD OPERATING CONDITIONS PARAMETER VCC Voltage Operating Temperature ELECTRICAL OPERATING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS TOLR Absolute Resistance Tolerance TOLC MAX UNITS Measured at TA=25°C +20 % Absolute Capacitance Tolerance Measured at 1MHz, 2.5VDC, TA=25°C +20 % ILEAK Leakage current to GND Measured at 5.0VDC, TA=25°C 10 µA VESDi ESD protection, input pins Pins 3,4,5,6,7,9,11,13, & 14, per IEC 61000-4-2 specification, Notes 1,2,3 +8 kV VESD ESD protection, connector pins Pins 1,2,8,10,12,15,16,17,18,19, 21,23,24,25,26,27, & 28, per IEC 61000-4-2 specification Notes 1,2,4 +30 kV Clamping voltage under ESD discharge ESD applied to connector pin, measured at corresponding input pin; +8kV discharge, Human Body Model Notes 1,2 8.3 V ESD applied to connector pin, measured at corresponding input pin; -8kV discharge, Human Body Model; Notes 1,2 -2.7 V VCLAMP Note 1: Note 2: Note 3: Note 4: MIN TYP 1 Guaranteed by design and characterization. ESD voltage applied between Input/Connector pins and ground, one pin at a time. Pins 3-7, 9, 11, 13, and 14 typically connect to the I/O pins of a Super I/O chip. Pins 1, 2, 8, 10, 12, 15-19, 21, and 23-28 typically connect to the Parallel Port connector. © 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 3 PACSZ1284 Performance Information Filter Capacitors Filter Insertion Loss The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 lines. Basic filtering is provided through the presence of a capacitor on all signal lines. The filter capacitor is the junction capacitance of an ESD diode. The typical capacitance at a reverse voltage of 2.5V is 150pF. This diode capacitance is somewhat voltage dependent. See Figure 1. Figure 2 shows the typical Insertion Loss graphs of the PACSZ1284 for Data and Strobe signals. The curves are dependent on the physical location of the filter elements with respect to the ground terminal of this device. These graphs are measured in a 50Ω environment on a Hewlett Packard HP 8753C Analyzer. The signal source is introduced at the resistor input and the output is measured at the corresponding protection diode. The actual pins measured are labeled in the Figure 2 graph. Figure 1. Diode Capacitance vs. Reverse Voltage The higher speed Data and Strobe lines (9 in total) require an additional series resistor termination for proper operation, while the eight (8) Status lines do not. See Table 1 on page 5. Frequency (MHz) Figure 2. Typical Filter Insertion Loss © 2003 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 09/15/03 PACSZ1284 Application Information Termination Considerations Interfacing to IEEE 1284 Connectors The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and Status lines (8 in total) only require a pull-up resistor and a filter capacitor. The Data lines and Strobe also require a series termination resistor in addition to the pull-up resistors and filter capacitors. See Table 1, in conjunction with the schematic diagram on page 1. IEEE 1284 defines three interface connectors: • 1284 A is a 25-pin DB series connector which is the de facto PC standard for the host connection. • 1284 B is a 36-pin, 0.085 inch centerline connector used on the peripheral device. • 1284 C is a new 36-pin, 0.050 inch centerline connector which can be used for both host and peripheral. Table 1: IEEE 1284 Termination Requirements Figure 3A shows a possible hook-up between the 1284-A connector on a PC motherboard and the PACSZ1284, illustrating how the pin configuration of the PACSZ1284 allows for easy interconnect between the two. The dotted I/O signals of the PACSZ1284 will typically be connected to a Super I/O chip on the motherboard. SIGNAL TERMINATION REQUIREMENTS Signal Name Series Termination Data1 - Data8 Yes Strobe Yes Init Not Required AutoFeedXT Not Required Selectin Not Required ACK Not Required Busy Not Required Paper Empty Not Required Select Not Required Fault Not Required Figure 3B shows a possible hook-up between the 1284-B connector on a peripheral and the PACSZ1284. Figure 3C shows a possible hook-up between the 1284-C connector and the PACSZ1284. Figure 3A: Figure 3B: Figure 3C: 1284-A Connector Host 1284-B Connector Peripheral 1284-C Connector Host/Peripheral 14 25 19 36 36 20 19 1 13 18 2 1 1 18 PACSZ1284 SUPER 1284 PACSZ1284 SUPER 1284 1 = FLOW THROUGH SIGNALS 1 = GND = GND = VCC PACSZ1284 SUPER 1284 1 = VCC Figure 3. Example Connections of IEEE 1284 Connectors with PACSZ1284 © 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 5 PACSZ1284 Application Information (continued) Table 2 provides the IEEE 1284 signal assignments for the three connectors, and example PACSZ1284 pin connections. When connecting a 1284-A host to a 1284-B peripheral, the “Peripheral Logic High” signal is not used. Similarly, when a 1284-A host is connected to a 1284C peripheral, the “Peripheral Logic High” and “Host Logic High” are not used. These two signals are optionally used to detect a “Power Off” or “Cable Disconnect” state for host and peripheral, respectively. Table 2: IEEE 1284 Connector Pinouts and PACSZ1284 Connection Guidelines PACSZ1284 PIN TYPE 1284-A 25-PIN DSUB 1284-B 36-PIN CHAMP 1284-C 36-PIN HIGH DENSITY SIGNAL PIN SIGNAL PIN SIGNAL PIN P-Port conn. side, series-terminated (16-19, 21, or 23-26) STROBE 1 STROBE 1 STROBE 15 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 1 2 Data 1 2 Data 1 6 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 2 3 Data 2 3 Data 2 7 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 3 4 Data 3 4 Data 3 8 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 4 5 Data 4 5 Data 4 9 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 5 6 Data 5 6 Data 5 10 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 6 7 Data 6 7 Data 6 11 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 7 8 Data 7 8 Data 7 12 P-Port conn. side, series-terminated (16-19, 21, or 23-26) Data 8 9 Data 8 9 Data 8 13 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) ACK 10 ACK 10 ACK 3 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) BUSY 11 BUSY 11 BUSY 1 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) PError 12 PError 12 PError 5 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Select 13 Select 13 Select 2 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) AUTOFD 14 AUTOFD 14 AUTOFD 17 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) FAULT 15 FAULT 32 FAULT 4 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) INIT 16 INIT 31 INIT 14 Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28) Selectin 17 Selectin 36 Selectin 16 Ground 18 Ground 19 Ground 19 Ground 19 Ground 20 Ground 20 Ground 20 Ground 21 Ground 21 Ground 21 Ground 22 Ground 22 Ground 22 Ground 23 Ground 23 Ground 23 Ground 24 Ground 24 Ground 24 Ground 25 Ground 25 Ground 25 Ground 26 Ground 26 Ground 27 Ground 27 Ground 28 Ground 28 Ground 29 Ground 29 Ground 30 Ground 30 Not Defined 33 Ground 31 Not Defined 34 Ground 32 Not Defined 35 Ground 33 Not Defined 15 Ground 34 Logic Ground 16 Ground 35 Chassis GND 17 Not Required 36 Peripheral Logic 18 Host Logic High 18 © 2003 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 09/15/03 PACSZ1284 Mechanical Details QSOP Mechanical Specifications: Mechanical Package Diagrams PACSZ1284 devices are packaged in 28-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-28 package, see the California Micro Devices QSOP Package Information document. TOP VIEW D 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 9.80 9.98 0.386 0.393 e E Pin 1 Marking 28 Dimensions E H 3.81 3.98 0.150 0.64 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SIDE VIEW A A1 SEATING PLANE B 0.157 e 0.025 BSC H 5.79 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 END VIEW # per tube 50 pieces* # per tape and reel 2500 pieces C Controlling Dimensions: inches L * This is an approximate amount which may vary. Package Dimensions for QSOP-28 © 2003 California Micro Devices Corp. All rights reserved. 09/15/03 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 7