TI CD74AC109EE4

CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
D
D
D
D
D
D
CD54AC109 . . . F PACKAGE
CD74AC109 . . . E OR M PACKAGE
(TOP VIEW)
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
description/ordering information
The ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
PDIP – E
Tube
CD74AC109E
CD74AC109E
SOIC – M
Tape and reel
CD74AC109M96
AC109M
CDIP – F
Tube
CD54AC109F3A
CD54AC109F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
↑
L
L
L
H
H
H
↑
H
L
H
H
↑
L
H
H
H
↑
H
H
H
L
H
H
L
X
X
Q0
Q0
Toggle
Q0
Q0
† Unpredictable and unstable condition if both PRE and CLR
go low simultaneously
logic diagram, each flip-flop (positive logic)
PRE
C
J
C
Q
TG
TG
K
C
C
CLK
C
C
TG
TG
C
C
C
C
Q
CLR
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
VCC
VIH
Supply voltage
High-level input voltage
–40°C to
85°C
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
5.5
1.5
5.5
1.5
5.5
VCC = 1.5 V
VCC = 3 V
1.2
1.2
1.2
2.1
2.1
2.1
VCC = 5.5 V
VCC = 1.5 V
3.85
VIL
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
Low-level output current
–55°C to
125°C
VCC = 3 V
VCC = 5.5 V
3.85
V
3.85
0.3
0.3
0.3
0.9
0.9
0.9
1.65
VCC
VCC
1.65
0
0
V
VCC
VCC
V
1.65
0
0
VCC
VCC
V
V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
–24
–24
–24
mA
24
24
24
mA
VCC = 1.5 V to 3 V
VCC = 3.6 V to 5.5 V
50
50
50
20
20
20
ns/V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
IOH = –50 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –24 mA
IOH = –50 mA†
IOH = –75 mA†
IOL = 50 µA
VOL
II
ICC
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
–55°C to
125°C
TA = 25°C
MAX
MIN
–40°C to
85°C
MAX
MIN
1.5 V
1.4
1.4
1.4
2.9
3V
2.9
2.9
4.5 V
4.4
4.4
4.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
UNIT
MAX
V
3.85
5.5 V
3.85
1.5 V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 12 mA
IOL = 24 mA
IOL = 50 mA†
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
IOL = 75 mA†
5.5 V
5.5 V
1.65
1.65
5.5 V
IO = 0
V
±0.1
±1
±1
µA
4
80
40
µA
10
10
10
5.5 V
Ci
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless
otherwise noted)
–55°C to
125°C
MIN
4
fclock
Clock frequency
tw
Pulse duration
tsu
th
trec
–40°C to
85°C
MAX
MIN
8
UNIT
MAX
9
MHz
CLK high or low
63
55
CLR or PRE low
56
49
Setup time, before CLK↑
J or K
69
61
ns
Hold time, after CLK↑
J or K
0
0
ns
Recovery time, before CLK↑
CLR↑ or PRE↑
31
27
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted)
–55°C to
125°C
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
th
trec
–40°C to
85°C
MAX
MIN
71
CLK high or low
UNIT
MAX
81
MHz
7
6
CLR or PRE
6.3
5.5
Setup time, before CLK↑
J or K
7.7
6.8
ns
Hold time, after CLK↑
J or K
0
0
ns
Recovery time, before CLK↑
CLR↑ or PRE↑
3.5
3.1
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted)
–55°C to
125°C
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
th
trec
MAX
–40°C to
85°C
MIN
100
CLK high or low
UNIT
MAX
114
MHz
5
4.4
CLR or PRE
4.5
3.9
Setup time, before CLK↑
J or K
5.5
4.8
ns
Hold time, after CLK↑
J or K
0
0
ns
Recovery time, before CLK↑
CLR↑ or PRE↑
2.5
2.2
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
–55°C to
125°C
MIN
MAX
8
CLK
Q or Q
CLR or PRE
CLK
Q or Q
CLR or PRE
–40°C to
85°C
MIN
UNIT
MAX
9
MHz
129
117
153
139
129
117
153
139
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
–55°C to
125°C
MIN
MAX
MIN
3.6
14.4
3.7
13.1
4.3
17.1
4.4
15.5
3.6
14.4
3.7
13.1
4.3
17.1
4.4
15.5
71
CLK
Q or Q
CLR or PRE
CLK
Q or Q
CLR or PRE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–40°C to
85°C
UNIT
MAX
81
MHz
ns
ns
5
CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
–55°C to
125°C
MIN
MAX
100
CLK
Q or Q
CLR or PRE
CLK
Q or Q
CLR or PRE
–40°C to
85°C
MIN
UNIT
MAX
114
MHz
2.6
10.3
2.7
9.4
3.1
12.2
3.2
11.1
2.6
10.3
2.7
9.4
3.1
12.2
3.2
11.1
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
UNIT
56
pF
CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
S1
R1 = 500 Ω†
From Output
Under Test
2 × VCC
Open
GND
CL = 50 pF
(see Note A)
R2 = 500 Ω†
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
VCC
† When VCC = 1.5 V, R1 = R2 = 1 kΩ
Input
50% VCC
50% VCC
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
VCC
Reference
Input
VCC
50% VCC
50% VCC
0V
0V
tsu
trec
Data
50%
Input 10%
VCC
50% VCC
CLK
90%
VOLTAGE WAVEFORMS
RECOVERY TIME
tf
VCC
50% VCC
50% VCC
tPLH
tPHL
50%
10%
90%
90%
tr
tPHL
Out-of-Phase
Output
VCC
50% VCC
10% 0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
0V
In-Phase
Output
90%
tr
0V
Input
th
90%
VOH
50% VCC
10%
VOL
tf
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
50% VCC
10%
tf
50%
10%
90%
tr
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
Output
Control
50% VCC
50% VCC
0V
tPLZ
tPZL
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
≈VCC
20% VCC
VOL
50% VCC
VOH
80% VCC
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
CD54AC109F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD74AC109E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74AC109EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74AC109M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC109M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Low Power Wireless www.ti.com/lpw
Mailing Address:
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2006, Texas Instruments Incorporated