SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) All Ports Ioff Supports Partial-Power-Down Mode Operation SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 14 4 13 5 12 6 11 7 10 8 9 CLK E F G H QH 1 16 CLK SH/LD NC VCC CLK INH 3 VCC CLK INH D C B A SER QH SN54LV165A . . . FK PACKAGE (TOP VIEW) 15 CLK INH 14 D 2 3 E F NC G H 13 C 12 B 4 5 11 A 10 SER 6 7 8 9 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 D C NC B A GND NC QH SER 15 VCC 16 2 QH 1 SH/LD SH/LD CLK E F G H QH GND SN74LV165A . . . RGY PACKAGE (TOP VIEW) GND D D Latch-Up Performance Exceeds 250 mA Per NC − No internal connection description/ordering information The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation. When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output, QH. ORDERING INFORMATION QFN − RGY SN74LV165ARGYR Tube of 40 SN74LV165AD Reel of 2500 SN74LV165ADR SOP − NS Reel of 2000 SN74LV165ANSR 74LV165A SSOP − DB Reel of 2000 SN74LV165ADBR LV165A Tube of 90 SN74LV165APW Reel of 2000 SN74LV165APWR Reel of 250 SN74LV165APWT TVSOP − DGV Reel of 2000 SN74LV165ADGVR LV165A CDIP − J Tube of 25 SNJ54LV165AJ SNJ54LV165AJ CFP − W Tube of 150 SNJ54LV165AW SNJ54LV165AW LCCC − FK Tube of 55 SNJ54LV165AFK SNJ54LV165AFK TSSOP − PW −55°C to 125°C † TOP-SIDE MARKING Reel of 1000 SOIC − D −40°C 40 C to 85°C 85 C ORDERABLE PART NUMBER PACKAGE† TA LV165A LV165A LV165A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 description/ordering information (continued) Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/ LD is held low, independently of the levels of CLK, CLK INH, or SER. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS OPERATION SH/ LD CLK CLK INH L X X H H X Q0 H X H Q0 H L ↑ Shift H ↑ L Shift Parallel load logic diagram (positive logic) A SH/LD CLK INH CLK SER 1 B 11 C 12 D 13 E 14 F 3 H 5 6 15 2 10 S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. 2 G 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 S C1 1D R S C1 1D R S C1 1D R 9 7 QH QH SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 typical shift, load, and inhibit sequences CLK CLK INH SER L SH/LD Data Inputs A H B L C H D L E H F L G H H H QH H H L H L H L H QH L L H L H L H L Inhibit Serial Shift Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 recommended operating conditions (see Note 5) VCC SN54LV165A SN74LV165A MIN MAX MIN MAX 2 5.5 2 5.5 Supply voltage VCC = 2 V VIH High level input voltage High-level 1.5 UNIT V 1.5 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC = 2 V V 0.5 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VIL Low level input voltage Low-level VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V −50 −50 µA −2 −2 VCC × 0.3 VCC = 4.5 V to 5.5 V VCC = 2 V IOH VCC = 2.3 V to 2.7 V High level output current High-level VCC = 3 V to 3.6 V −6 −6 −12 50 50 VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 6 6 VCC = 4.5 V to 5.5 V 12 12 VCC = 2.3 V to 2.7 V 200 200 VCC = 3 V to 3.6 V 100 100 20 20 VCC = 2 V IOL ∆t/∆v Low level output current Low-level Input transition rise or fall rate VCC = 4.5 V to 5.5 V TA VCC × 0.3 −12 VCC = 4.5 V to 5.5 V Operating free-air temperature −55 125 V −40 mA µA mA ns/V °C 85 NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV165A PARAMETER VOH TEST CONDITIONS MIN TYP SN74LV165A MAX MIN IOH = −50 µA 2 V to 5.5 V IOH = −2 mA 2.3 V 2 2 IOH = −6 mA 3V 2.48 2.48 4.5 V 3.8 IOH = −12 mA VOL VCC VCC−0.1 TYP MAX VCC−0.1 V 3.8 IOL = 50 µA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 IOL = 6 mA 3V 0.44 0.44 4.5 V IOL = 12 mA II VI = 5.5 V or GND ICC VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND IO = 0 UNIT V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V POST OFFICE BOX 655303 1.7 • DALLAS, TEXAS 75265 1.7 pF 5 SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN CLK high or low tw Pulse duration SH/LD low SH/LD high before CLK↑ SER before CLK↑ tsu Setup time CLK INH before CLK↑ Data before SH/LD↑ SER data after CLK↑ th Hold time MAX SN54LV165A MIN MAX SN74LV165A MIN 8.5 9 9 11 13 13 7 8.5 8.5 8.5 9.5 9.5 7 7 7 11.5 12 12 −1 0 0 Parallel data after SH/LD↑ 0 0.5 0.5 SH/LD high after CLK↑ 0 0 0 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN CLK high or low tw tsu Pulse duration Setup time MAX MIN 6 7 7 9 9 SH/LD high before CLK↑ 5 6 6 SER before CLK↑ 5 6 6 CLK INH before CLK↑ 5 5 5 7.5 8.5 8.5 0 0 0 0.5 0.5 0.5 0 0 0 SER data after CLK↑ Hold time MIN SN74LV165A 7.5 SH/LD low Data before SH/LD↑ th MAX SN54LV165A Parallel data after SH/LD↑ SH/LD high after CLK↑ MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw tsu Pulse duration Setup time MAX SN74LV165A MIN 4 4 SH/LD low 5 6 6 SH/LD high before CLK↑ 4 4 4 SER before CLK↑ 4 4 4 3.5 3.5 3.5 CLK INH before CLK↑ Parallel data after SH/LD↑ SH/LD high after CLK↑ 6 MIN 4 SER data after CLK↑ Hold time SN54LV165A CLK high or low Data before SH/LD↑ th MAX POST OFFICE BOX 655303 5 5 5 0.5 0.5 0.5 1 1 1 0.5 0.5 0.5 • DALLAS, TEXAS 75265 MAX UNIT ns ns ns SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C SH/LD QH or QH CL = 15 pF 50* 80* 45* 45 CL = 50 pF 40 65 35 35 CL = 15 pF QH or QH MAX MIN MAX MIN MAX 19.8* 1* 22* 1 22 13.1* 21.5* 1* 23.5* 1 23.5 12.9* 21.7* 1* 24* 1 24 15.3 23.3 1 26 1 26 16.1 25.1 1 28 1 28 15.9 25.3 1 28 1 28 H UNIT MHz 12.2* CL = 50 pF range, SN74LV165A TYP CLK SH/LD SN54LV165A MIN H tpd temperature LOAD CAPACITANCE CLK tpd free-air ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd tpd free-air TA = 25°C temperature SN54LV165A SN74LV165A LOAD CAPACITANCE MIN TYP CL = 15 pF 65* 115* 55* 55 CL = 50 pF 60 90 50 50 MAX MIN MAX MIN MAX CLK 8.6* 15.4* 1* 18* 1 18 9.1* 15.8* 1* 18.5* 1 18.5 H 8.9* 14.1* 1* 16.5* 1 16.5 CLK 10.9 14.9 1 16.9 1 16.9 SH/LD 11.3 19.3 1 22 1 22 11.1 17.6 1 20 1 20 CL = 15 pF QH or QH CL = 50 pF H UNIT MHz SH/LD QH or QH range, ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C SH/LD QH or QH CL = 15 pF 110* 165* 90* 90 CL = 50 pF 95 125 85 85 CL = 15 pF QH or QH CL = 50 pF H MAX MIN MAX range, SN74LV165A TYP CLK SH/LD SN54LV165A MIN H tpd temperature LOAD CAPACITANCE CLK tpd free-air MIN MAX UNIT MHz 6* 9.9* 1* 11.5* 1 6* 9.9* 1* 11.5* 1 11.5 11.5 6* 9* 1* 10.5* 1 10.5 7.7 11.9 1 13.5 1 13.5 7.7 11.9 1 13.5 1 13.5 7.6 11 1 12.5 1 12.5 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz VCC TYP 3.3 V 36.1 5V 37.5 UNIT pF 7 SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH tPHL 50% VCC tPHL 50% VCC VOL VOH 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC 50% VCC tPZL VOH In-Phase Output Out-of-Phase Output 0V VCC Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 27-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LV165AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ADBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ADBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ADBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165ADRG3 PREVIEW SOIC D 16 2500 TBD Call TI Samples Not Available SN74LV165ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples Addendum-Page 1 Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 27-May-2010 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LV165APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74LV165APWRG3 PREVIEW TSSOP PW 16 2000 TBD Call TI Samples Not Available SN74LV165APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples SN74LV165APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74LV165ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples SN74LV165ARGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com (3) 27-May-2010 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN74LV165A : • Enhanced Product: SN74LV165A-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LV165ADBR SSOP DB 16 2000 330.0 16.4 8.2 SN74LV165ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV165ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV165ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV165APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV165APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV165ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV165ADBR SSOP DB 16 2000 346.0 346.0 33.0 SN74LV165ADGVR TVSOP DGV 16 2000 346.0 346.0 29.0 SN74LV165ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV165ANSR SO NS 16 2000 346.0 346.0 33.0 SN74LV165APWR TSSOP PW 16 2000 346.0 346.0 29.0 SN74LV165APWT TSSOP PW 16 250 346.0 346.0 29.0 SN74LV165ARGYR VQFN RGY 16 3000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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