CS4461
Multi-Bit A/D for Class-D Real-Time PSR Feedback
Features
General Description
z Advanced Multi-bit Delta-Sigma Architecture
The CS4461 is a complete analog-to-digital converter
for class-D real-time power supply rejection (PSR) feedback. It performs sampling and analog-to-digital
conversion, generating digital data for input to a
class-D modulator with real-time PSR feedback
capabilities.
z Real-time Feedback of Power Supply
Conditions (AC and DC)
z Filterless Digital Output Resulting in Very Low
Signal Delay
z 135 mW Power Consumption
z Supports Logic Levels Between 3.3 V and
5.0 V
z Differential Analog Architecture
z Modulator Overflow Detection
z Interfaces Directly to the CS44800/CS44600
Class-D PWM Modulator
z Multi-bit Conversion at up to 7.5 MHz
z Delivers Modulated Data Over 2-Wire Interface
VQ
FILT+
The CS4461 uses a 5th-order, multi-bit delta-sigma
modulator followed by output data formatting. The ADC
uses a differential architecture which provides excellent
noise rejection.
The CS4461 feeds back the AC and DC voltage components and is ideal for class-D audio systems requiring
high power supply rejection.
The CS4461 is available in a 24-pin TSSOP package in
both Commercial (-10° to +70° C) and Automotive
grade (-40° to +85° C). The CDB44800 Customer Demonstration board is also available for device evaluation
and implementation suggestions. Please see “Ordering
Information” on page 11 for complete details.
PSR_RESET
REFGND
PSR_EN
Voltage Reference
OVERFLOW
PSR_MCLK
+
AIN+
∆Σ
LP Filter
AIN-
S/H
Output Data
Formatting
-
PSR_SYNC
PSR_DATA
DAC
5.0 V
(VA)
http://www.cirrus.com
GND
3.3 V to 5.0 V
(VDP)
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
SEPTEMBER '05
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CS4461
TABLE OF CONTENTS
1.
2.
3.
4.
CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 3
PIN DESCRIPTIONS ............................................................................................................................. 6
TYPICAL CONNECTION DIAGRAM .................................................................................................... 7
APPLICATIONS .................................................................................................................................... 8
4.1 Digital Connections ......................................................................................................................... 8
4.2 Analog Connections ....................................................................................................................... 8
4.3 Power-Up Sequence ...................................................................................................................... 9
4.4 Overflow Detection ......................................................................................................................... 9
4.5 Grounding and Power Supply Decoupling ...................................................................................... 9
5. PACKAGE DIMENSIONS ................................................................................................................. 10
6. ORDERING INFORMATION ............................................................................................................... 11
7. REVISION HISTORY ........................................................................................................................... 11
LIST OF FIGURES
Figure 1. Typical Connection Diagram......................................................................................................... 7
Figure 2. CS4461 Recommended Analog Input Buffer................................................................................ 8
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1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Parameter
Symbol
Min
Typ
Max
Unit
Positive Analog
Positive Digital
VA
VDP
4.75
3.1
5.0
3.3
5.25
5.25
V
V
Commercial (-CZZ)
Automotive (-DZZ)
TAC
TAA
-10
-40
-
+70
+85
°C
°C
DC Power Supplies:
Ambient Operating Temperature
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 1)
Parameter
Symbol
Min
Max
Units
Analog
Digital
VA
VDP
-0.3
-0.3
+6.0
+6.0
V
V
Input Current
(Note 2)
Iin
-
±10
mA
Analog Input Voltage
(Note 3)
VIN
GND - 0.7
VA + 0.7
V
Digital Input Voltage
(Note 3)
VIND
-0.7
VDP + 0.7
V
Ambient Operating Temperature (Power Applied)
TA
-50
+95
°C
Storage Temperature
Tstg
-65
+150
°C
DC Power Supplies:
Notes:
1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
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CS4461
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground.
PSR_MCLK=12.288 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Current
(Normal Operation)
VA
VDP = 5.0 V
VDP = 3.3 V
IA
ID
ID
-
17.5
22
14.5
21
26
17
mA
mA
mA
Power Supply Current
(Power-Down Mode) (Note 4)
VA
VDP = 5.0 V
IA
ID
-
2
2
-
mA
mA
-
198
135
20
235
161
-
mW
mW
mW
mW
-
65
-
dB
VQ Nominal Voltage
-
2.5
25
0.01
-
V
kΩ
mA
FILT+ Nominal Voltage
-
5
18
0.01
-
V
kΩ
mA
Power Consumption
(Normal Operation)
VDP = 5.0 V
VDP = 3.3 V
VDP = 5.0 V
(Power-Down Mode)
ADC Power Supply Rejection Ratio (1 kHz)
(Note 5)
PSRR
Output Impedance
Maximum allowable DC current source/sink
Output Impedance
Maximum allowable DC current source/sink
Notes:
4. Power Down Mode is defined as PSR_RESET = Low with all clocks and data lines held static.
5. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
Parameter
High-Level Input Voltage
Symbol
Min
Typ
Max
Units
VIH
70%
-
-
V
(% of VDP)
Low-Level Input Voltage
(% of VDP)
VIL
-
-
30%
V
High-Level Output Voltage at Io = 100 µA
(% of VDP)
VOH
70%
-
-
V
Low-Level Output Voltage at Io = 100 µA
(% of VDP)
VOL
-
-
15%
V
IOVERFLOW
-
-
4.0
mA
Iin
-
-
±10
µA
OVERFLOW Current Sink
Input Leakage Current
THERMAL CHARACTERISTICS
Parameter
Symbol
Allowable Junction Temperature
Junction to Ambient Thermal Impedance
4
θJA
Min
Typ
Max
Unit
-
-
135
°C
-
70
-
°C/W
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CS4461
ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.)
Parameter
Symbol
Min
Typ
Max
Unit
±5
-
±100
-
%
ppm/°C
1.1
1.1
18
-
1.13*VA
1.13*VA
82
3.9
3.9
-
VPP
VPP
V
V
kΩ
dB
DC Accuracy
Gain Error
Gain Drift
Analog Input Characteristics
Full-scale Differential Input Voltage
AIN+/AIN- Input Range
(VA = 5.0 V)
Input Impedance (Differential)
Common Mode Rejection Ratio
-CZZ
-DZZ
-CZZ
-DZZ
(Note 6)
CMRR
Notes:
6. Measured between AIN+ and AIN-
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CS4461
2. PIN DESCRIPTIONS
Pin Name
PSR_RESET
1
24
FILT+
GND
2
23
REFGND
PSR_SYNC
3
22
VQ
PSR_DATA
4
21
GND
PSR_MCLK
5
20
GND
VDP
6
19
VA
GND
7
18
GND
VDP
8
17
AIN-
TEST
9
16
AIN+
GND
10
15
OVERFLOW
PSR_EN
11
14
VDP
GND
12
13
VDP
Top-Down View
24-pin TSSOP Package
#
Pin Descriprion
VDP
6
8
13
14
Digital Logic Power (Input) – Digital core and input/output power supply. Nominally +3.3 V or +5.0 V.
Supply decoupling should placed as close as possible to pin 6.
VA
19
Analog Power (Input) - Analog power supply. Nominally +5.0 V.
GND
2
7
10
12
18
20
21
Ground (Input) - Ground reference for both analog and digital.
PSR_RESET
1
Reset (Input) - When PSR_RESET is low, the CS4461 enters a low power mode and all internal states
are reset. On initial power up, PSR_RESET must be held low until the power supply is stable, and all
input clocks are stable in frequency and phase.
VQ
22
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
REFGND
23
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
24
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuit.
AIN+
AIN-
16
17
Differential PSR Analog Input (Input) - Signals are presented differentially to the delta-sigma modulator via the AIN+/- pins.
PSR_MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and output data.
PSR_SYNC
3
Synchronization Data Output (Output) - Used to synchronize the serial data in the PWM modulator.
PSR_DATA
4
PSR Serial Data Output (Output) - Power supply modulated and formatted serial data.
PSR_EN
11
PSR Enable (Input) - A high to low transition on this pin will enable the PSR feedback circuit.
OVERFLOW
15
Overflow (Output, open drain) - Indicates a modulator overflow condition.
TEST
9
Test (Output) - This pin may toggle during normal operation and should be pulled low through a 47 kΩ
resistor to GND in order to minimize noise.
6
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CS4461
3. TYPICAL CONNECTION DIAGRAM
+3.3 V or +5.0 V
0.1 µF
VDP
VDP
VDP
VDP
+5.0 V
VA
47 µF
PSR_MCLK
PSR_SYNC
0.1 µF
PSR_DATA
22.1 Ω
22.1 Ω
22.1 Ω
PWM
Modulator
with PSR
Processing
PSR_EN
See “CS4461 Recommended Analog Input
Buffer” on page 8.
AIN+
AIN-
PSR_RESET
VDP
CS4461
47 kΩ
OVERFLOW
VQ
1 µF
TEST
0.1 µF
47 kΩ
GND
GND
GND
FILT+
47 µF
GND
GND
0.1 µF
REFGND
GND
GND
Figure 1. Typical Connection Diagram
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CS4461
4. APPLICATIONS
4.1
Digital Connections
PSR_MCLK provides the system clock for the CS4461. PSR_SYNC and PSR_DATA provide the output of
the modulator to the class-D modulator with feedback capabilities. Series damping resistors should be used
on PSR_MCLK, PSR_SYNC, and PSR_DATA to minimize noise. These should be placed as close as possible to their signal source. The pin labeled TEST should also be pulled low to GND through a 47 kΩ resistor
to minimize noise coupling into the ADC modulator.
4.2
Analog Connections
The analog modulator samples the input at PSR_MCLK/4 (6.144 MHz with PSR_MCLK=24.576 MHz).
Figure 2 shows the suggested analog input filter. This filter topology will correctly buffer the power supply’s
AC and DC components for PSR processing by the class-D modulator. The use of capacitors which have a
large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. C0G dielectrics should be used wherever possible. R1 and R2 should be used to scale VP
(class-D amplifier high voltage power supply) to less than the CS4461 maximum AIN+/AIN- input voltage
(3.9 V).
2 kΩ
2 kΩ
120 pF
VP
+5.0 V
+5.0 V
R1
-
+
R2
90.9 Ω
649 Ω
-
90.9 Ω
AIN+
+
2200 pF
C0G
CS4461
120 pF
649 Ω
AIN-
Figure 2. CS4461 Recommended Analog Input Buffer
The following equation can be used to scale R1 and R2:
2 * (VP * (1 + %VP_Ripple)) * (R2 / (R1 + R2)) < 3.9 V
Example (VP = 40 V, %VP_Ripple = 4%):
2 * (40 * (1 + 0.04)) * (1.96 kΩ / (40.2 kΩ + 1.96 kΩ) = 3.87 V
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CS4461
4.3
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies and clocks
are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.
4.4
Overflow Detection
The CS4461 includes modulator overflow detection, indicated on pin 15, OVERFLOW (open drain, active
low). OVERFLOW will go to a logical low as soon as an overrange condition is detected. The data will remain low until the condition is cleared.
4.5
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4461 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA and VDP connected to clean supplies. VDP, which powers the digital logic, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VDP. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulator. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ to GND. The CDB44800 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
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CS4461
5. PACKAGE DIMENSIONS
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
e
b2
SIDE VIEW
A
∝
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
DIM
A
A1
A2
b
D
E
E1
e
L
µ
MIN
-0.002
0.03346
0.00748
0.303
0.248
0.169
-0.020
0°
NOM
-0.004
0.0354
0.0096
0.307
0.2519
0.1732
0.026 BSC
0.024
4°
MILLIMETERS
MAX
0.043
0.006
0.037
0.012
0.311
0.256
0.177
-0.028
8°
MIN
-0.05
0.85
0.19
7.70
6.30
4.30
-0.50
0°
NOM
--0.90
0.245
7.80
6.40
4.40
0.65 BSC
0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
7.90
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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6. ORDERING INFORMATION
Product
CS4461
CDB44800
Description
Package Pb-Free
Multi-bit A/D for
Class-D Real-time
PSR Feedback
24-TSSOP
Evaluation board for
the CS44800/600
and the CS4461
-
Grade
Temp Range
Commercial
-10° to +70° C
Automotive
-40° to +85° C
-
-
YES
-
Container
Order #
Rail
Tape & Reel
Rail
Tape & Reel
CS4461-CZZ
CS4461-CZZR
CS4461-DZZ
CS4461-DZZR
-
CDB44800
7. REVISION HISTORY
Release
Date
A1
May 2004
F1
September 2005
Changes
1st Advance Release
Updated ordering information
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
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