LXT334 & LXT304A — Low Cost & High Performance Quad E1 Interface Solution Application Note January 2001 Order Number: 249171-001 As of January 15, 2001, this document replaces the Level One document known as AN070. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT334 & LXT304A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Application Note LXT334 & LXT304A — Low Cost & High Performance Quad E1 Interface Solution Contents 1.0 Introduction .................................................................................................................. 5 1.1 1.2 1.3 ETSI CTR12/13 Requirements..............................................................................5 Design Considerations .......................................................................................... 5 Test Results .......................................................................................................... 7 1 2 3 4 CTR12/13 Compliant Quad Port Solution ............................................................. 6 LXT304A Configuration as a Stand-alone E1 Jitter Attenuator ............................. 7 CTR12/13 Jitter Performance Evaluation.............................................................. 8 Combined Jitter Attenuation Performance (LXT304A and LXT334) ..................... 9 1 LXT304A Crystal Specifications ............................................................................ 8 Figures Tables Application Note 3 LXT334 & LXT304A — Low Cost & High Performance Quad E1 Interface Solution 1.0 Introduction This application note shows how to design a CTR12/13 compliant quad port solution using the LXT334 quad E1 transceiver. In order to obtain the jitter attenuation performance required by this specification, the LXT304A is used as a stand-alone jitter attenuator to obtain the transmit timing source. 1.1 ETSI CTR12/13 Requirements The European Telecommunications Standards Institute (ETSI) drafted two types of standards that define harmonized requirements. The first, for which compliance is voluntary, is the European Telecommunications Standard (ETS). The ETS completely describes all details of the specified interface or equipment. The Technical Basis for Regulation (TBR) requirements are combined with regulatory provisions to form a Common Technical Regulation, or CTR. In Europe there are two categories of 2.048 Mbps leased line service: unstructured and structured. Unstructured service provides a usable bit rate of 2048 kbps with no network-provided timing or framing support. CTR-12 defines the necessary technical requirements for unstructured service. Structured service provides a usable bit rate of 1984 kbps with network framing support. CTR-13 defines the technical requirements for structured leased line service. CTR-12 and CTR-13 include a common Output Jitter section (5.2.1.4). For terminal equipment, this section defines a maximum output jitter of 0.11 UIpp for frequencies from 20 Hz to 100 kHz when measured with a bandpass filter (40 Hz -100 kHz). The input jitter is limited to 1.5 UIpp. The output jitter limit applies to equipment in configurations where output timing is derived locally as well as configurations where output timing is derived from one or more leased lines. These requirements also apply with a data rate offset of up to ±50 ppm from 2.048 MHz. Not all the equipment designed for the E1 market has to meet CTR12/13. The designer must check with the product specification to determine if such performance is needed. 1.2 Design Considerations Figure 1 shows a block diagram of a quad port solution using the LXT334 LIU. The LXT334 provides the data and clock recovery functions with optional HDB3 encoding/decoding. On the transmit side, the pulse shaping feature on the LXT334 provides a stable pulse meeting G.703 E1 templates. A high performance transmit driver provides excellent transmit return loss exceeding ETSI 300166 requirements. The LXT334 will typically interface with a quad E1 framer. Most industry standard framers provide elastic stores for adaptation between backplane timing and receive timing. These are two frame wide fifos capable of performing controlled slips (frame discarding or repetition). They also accommodate some of the low frequency jitter (wander). An important block in these designs is the system synchronizer. Typically, the system synchronizer must be able to extract backplane and transmit timing from an internal source or from one of the tributary inputs. The synchronizer’s jitter attenuation performance will determine the amount of jitter in the transmit clock and consequently, the output jitter conveyed to the network. Many designs rely on external VCXO-based PLL circuits added to the transceiver to make the jitter Application Note 5 LXT334 & LXT304A — Low Cost & High Performance Quad E1 Interface Solution attenuation performance CTR12/13 compliant. This application note shows how to design a CTR12/13 compliant solution using the LXT334 as the line interface and the LXT304A as a jitter attenuator. Figure 1. CTR12/13 Compliant Quad Port Solution Quad Framer LXT334 TX Line Driver TDATA1 Pulse Shaping Tx RX RDATA1 HDB3 decoder RCLK1 Elastic Store CH1 CH2 CH3 CH4 Backplane Clock HDB3 encoder TCLK1 F R A M I N G System Backplane Elastic Store Data Recovery Clock Recovery Peak Detect and Data Slicers Rx RCLK1 RCLK2 RCLK3 RCLK4 Transmit Clock Optional Rate Conversion PLL OUT XN XTAL IN RCLK LXT304A 4:1 MUX TCLK LLOOP "on" System Synchronizer A four to one multiplexer allows the synchronizer to choose any one of the tributary recovered clocks as the source for backplane/transmit timing. This clock is then delivered to the LXT304A jitter attenuator. The combined jitter attenuation performance of the LXT334 clock recovery circuit and the LXT304A jitter attenuator provides a good margin for CTR12/13 compliance. In the following section we present experimental results supporting this statement. The 2.048 MHz clock obtained from the LXT304A is used for transmission. An additional frequency multiplier PLL might be necessary in the cases where the backplane clock runs at a different frequency. When used as a single chip jitter attenuator, the LXT304A provides more than 50% cost savings, as well as board space savings, compared to VCXO based solutions. The LXT304A incorporates an on-chip crystal oscillator, using an external pullable quartz crystal. A specification for the crystal is provided in Table 1. Figure 2 shows the appropriate pin configuration for the LXT304A when used as a stand-alone jitter attenuator for CTR12/13 compliant designs. 6 Application Note LXT334 & LXT304A — Low Cost & High Performance Quad E1 Interface Solution Figure 2. LXT304A Configuration as a Stand-alone E1 Jitter Attenuator n/c n/c 8.192 MHz XTAL n/c n/c TCLK 3 TPOS 4 TNEG 5 MODE 6 RNEG 7 RPOS 8 RCLK n/c 1.3 XTALIN 10 XTALOUT 11 DPM 12 Vcc 28 10 kΩ 2 9 TAOS MCLK LOS 13 TTIP 14 TGND LXT304A 1 LLOOP 27 RLOOP 26 EC3 25 EC2 24 EC1 23 RGND 22 RV+ 21 RRING 20 RTIP 19 MRING 18 MTIP 17 TRING 16 TV+ 15 0.1 µF n/c n/c Vcc n/c n/c n/c Test Results Figure 3 represents a test setup used to evaluate the performance of the LXT334 and LXT304A in this kind of application. The pattern generator was set to a 215 - 1 pseudo random pattern. A function generator was used to get a 2.048MHz clock output adjustable within ± 50 ppm. The HP3785A jitter generator adds jitter to this clock. The jittered clock is then applied to the pattern generator’s external clock input of. CTR12/13 defines the amount of jitter added to this clock. The jittered line signal is then applied to the LXT334 receiver. The jitter present in the recovered clock and data is attenuated by the LXT304A. The signals are then looped back to the network through the LXT334 transmitter. The HP3785A was used to measure the output jitter in the 40Hz to 100KHz frequency band. Please refer to AN-44 Jitter Performance Requirements for E1 Leased Lines for a description of how to setup the HP3785A jitter measurement filters. Figure 4 shows typical results obtained using this configuration. The results were taken over a ± 50 ppm frequency offset range. Figure 4 demonstrates that the combined jitter attenuation performance of the LXT334 and the LXT304A provides very good margins within CTR12/13 requirements. Application Note 7 LXT334 & LXT304A — Low Cost & High Performance Quad E1 Interface Solution Figure 3. CTR12/13 Jitter Performance Evaluation LXT334 F R A M I N G Quad Framer System Backplane Elastic Store TX Line Driver TDATA1 HDB3 encoder Pulse Shaping Tx TCLK1 RX RDATA1 HDB3 decoder Data Recovery RCLK1 Elastic Store CH1 Clock Recovery Peak Detect and Data Slicers Rx RCLK1 CH2 RCLK2 CH3 CH4 Backplane Clock RCLK3 RCLK4 Transmit Clock Optional Rate Conversion PLL OUT X N XTAL RCLK IN LXT304A 4:1 MUX TCLK LLOOP "on" System Synchronizer Table 1. LXT304A Crystal Specifications Parameter Frequency Specification 8.192 MHz ±20 ppm @ 25 °C Frequency Stability ±25 ppm @ -40 to +85 °C (ref 25 °C reading) Pullability CL = 19 pF to 37 pF, crystal should pull -95 ppm to -115 ppm from nominal frequency. (Pull range may be slightly asymmetrical) CL = 19 pF to 11.6 pF, crystal should pull +95 ppm to +130 ppm from nominal frequency. Effective series resistance 30 Ω maximum Crystal cut AT Resonance Parallel Drive level 2.0 mW maximum Mode of operation Fundamental Crystal holder HC49 (R3W), CO = 7 pF maximum CM = 17 fF typical Recommendation: CXT8192 crystal manufactured by CTS Corporation, Tel: (815)786-8411 8 Application Note LXT334 & LXT304A — Low Cost & High Performance Quad E1 Interface Solution Figure 4. Combined Jitter Attenuation Performance (LXT304A and LXT334) 0.12 Output Jitter [UI] 0.1 0.08 Output Jitter -50ppm 0.06 Output Jitter 0ppm 0.04 TBR12/13 Limit Output Jitter +50ppm 0.02 0 10 100 1000 10000 100000 Frequency [Hz] Application Note 9