TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 D Open Drain Power-On Reset With 220-ms TPS773xx DGK Package (TOP VIEW) Delay (TPS773xx) D Open Drain Power-Good (PG) Status D D D D D D D D D D Output (TPS774xx) 250-mA Low-Dropout Voltage Regulator Available in 1.5-V, 1.6-V (TPS77316 Only), 1.8-V, 2.7-V, 2.8-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions Dropout Voltage Typically 200 mV at 250 mA (TPS77333, TPS77433) Ultralow 92-µA Quiescent Current (Typ) 8-Pin MSOP (DGK) Package Low Noise (55 µVrms) Without an External Filter (Bypass) Capacitor (TPS77318, TPS77418) 2% Tolerance Over Specified Conditions For Fixed-Output Versions Fast Transient Response Thermal Shutdown Protection See the TPS779xx Family of Devices for Active High Enable FB/SENSE RESET EN GND FB/SENSE PG EN GND 7 3 6 4 5 OUT OUT IN IN 1 8 2 7 3 6 4 5 OUT OUT IN IN TPS77x33 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 VDO – Dropout Voltage – mV The TPS773xx and TPS774xx are low-dropout regulators with integrated power-on reset and power good (PG) function respectively. These devices are capable of supplying 250 mA of output current with a dropout of 200 mV (TPS77333, TPS77433). Quiescent current is 92 µA at full load dropping down to 1 µA when device is disabled. These devices are optimized to be stable with a wide range of output capacitors including low ESR ceramic (10 µF) or low capacitance (1 µF) tantalum capacitors. These devices have extremely low noise output performance (55 µVrms) without using any added filter capacitors. TPS773xx and TPS774xx are designed to have fast transient response for larger load current changes. 8 2 TPS774xx DGK Package (TOP VIEW) 250 description 1 IO = 250 mA 200 150 100 IO = 10 mA 50 IO = 0 A 0 –50 –40 0 40 80 120 TJ – Junction Temperature – °C 160 The TPS773xx or TPS774xx is offered in 1.5-V, 1.6 V (TPS77316 only), 1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS773xx and TPS774xx families are available in 8-pin MSOP (DGK) packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 description (continued) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV at an output current of 250 mA for 3.3-volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 µA over the full range of output current, 0 mA to 250 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = 25°C. The TPS773xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS), or reset output voltage. The RESET output of the TPS773xx initiates a reset in DSP, microcomputer or microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in the TPS773xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after a 220-ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage. For the TPS774xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS774xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage. AVAILABLE OPTIONS OUTPUT VOLTAGE (V) TJ PACKAGED DEVICES MSOP (DGK) TPS773xx SYMBOL TYP TPS774xx SYMBOL 5.0 TPS77350DGK AGN TPS77450DGK AGW 3.3 TPS77333DGK AGM TPS77433DGK AGV 2.8 TPS77328DGK AGK TPS77428DGK AGT 2.7 TPS77327DGK AGJ TPS77427DGK AGS 1.8 TPS77318DGK AGH TPS77418DGK AGQ 1.6 TPS77316DGK AWF — — 1.5 TPS77315DGK AGG TPS77415DGK AGP Adjustable 1.5 V to 5.5 V TPS77301DGK AGF TPS77401DGK AGO – 40°C to 125°C NOTE: The TPS77301 and TPS77401 are programmable using an external resistor divider (see application information). The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77301DGKR). VI 5 IN OUT 6 OUT IN SENSE 0.1 µF 3 PG or RESET EN 7 VO 8 1 2 GND PG or RESET Output + 10 µF 4 Figure 1. Typical Application Configuration (For Fixed Output Options) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 functional block diagrams adjustable version IN EN PG or RESET _ + OUT + _ 220 ms Delay (for TPS773xx Option) Vref = 1.183 V R1 FB/SENSE R2 External to the Device GND fixed-voltage version IN EN PG or RESET _ + OUT + _ 220 ms Delay (for TPS773xx Option) SENSE R1 Vref = 1.183 V R2 GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION TPS773XX FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) RESET 2 O Reset output EN 3 I Enable input GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) PG 2 O Power good EN 3 I Enable input TPS774XX GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage TPS773xx RESET timing diagram VI Vres† Vres† t VO VIT +‡ VIT +‡ Threshold Voltage VIT –‡ VIT –‡ t RESET Output Output Undefined ÎÎ ÎÎ ÎÎ ÎÎ 220 ms Delay 220 ms Delay ÎÎ ÎÎ ÎÎ ÎÎ Output Undefined t † Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡ VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 TPS774xx PG timing diagram VI Vres† Vres† t VO VIT +‡ VIT +‡ Threshold Voltage VIT –‡ VIT –‡ t PG Output ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Output Undefined Output Undefined t † Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡ VIT – Trip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Input voltage range‡, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 13.5 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V Maximum RESET voltage (TPS773xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Maximum PG voltage (TPS774xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES PACKAGE AIR FLOW (CFM) θJA (°C/W) θJC (°C/W) TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 0 266.2 3.84 376 mW 3.76 mW/°C 207 mW 150 mW DGK 150 255.2 3.92 392 mW 3.92 mW/°C 216 mW 157 mW 250 242.8 4.21 412 mW 4.12 mW/°C 227 mW 165 mW recommended operating conditions MIN MAX Input voltage, VI§ 2.7 10 Output voltage range, VO 1.5 5.5 V 0 250 mA Output current, IO (see Note 1) UNIT V Operating virtual junction temperature, TJ (see Note 1) – 40 125 °C § To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 electrical characteristics over recommended operating junction temperature range (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) PARAMETER TEST CONDITIONS 1.5 V ≤ VO ≤ 5.5 V, Adjustable voltage TJ = 25°C 1.5 V ≤ VO ≤ 5.5 V TJ = 25°C, 2.7 V < VIN < 10 V 2.7 V < VIN < 10 V 1 6 V Output 1.6-V TJ = 25°C, 2.7 V < VIN < 10 V 2.7 V < VIN < 10 V 1 8 V Output 1.8-V TJ = 25°C, 2.8 V < VIN < 10 V 2.8 V < VIN < 10 V 2 7 V Output 2.7-V TJ = 25°C, 3.7 V < VIN < 10 V 3.7 V < VIN < 10 V 2 8 V Output 2.8-V TJ = 25°C, 3.8 V < VIN < 10 V 3.8 V < VIN < 10 V 3 3 V Output 3.3-V TJ = 25°C, 4.3 V < VIN < 10 V 4.3 V < VIN < 10 V 5 0 V Output 5.0-V TJ = 25°C, 6.0 V < VIN < 10 V 6.0 V < VIN < 10 V 1.02VO 1.470 1.530 1.632 Output current limit Peak output current 2.7 2.646 2.754 V 2.8 2.744 2.856 3.3 3.234 3.366 5.0 4.900 5.100 0.005 55 µVrms 1.3 400 A mA °C 1 µA EN = VI 3 µA FB = 1.5 V 1 µA EN = VI, TJ = 25°C High level enable input voltage 2 Low level enable input voltage Enable input current –1 Power supply ripple rejection (TPS77318, TPS77418) %/V mV 144 Adjustable voltage µA A 1 0.9 50% duty cycle V %/V 0.05 Thermal shutdown junction temperature Standby current V 1.836 92 VO = 0 V 2 ms pulse width, V 1.8 1.764 TJ = 25°C BW = 300 Hz to 100 kHz, TJ = 25°C, TPS77318, TPS77418 Output noise voltage V 1.6 1.568 VO + 1 V < VI ≤ 10 V, TJ = 25°C VO + 1 V < VI ≤ 10 V Load regulation UNIT 1.5 125 Output voltage line regulation (∆VO/VO)(see Note 3) FB input current MAX VO TJ = 25°C Quiescent current (GND current) (see Notes 2 and 4) TYP 0.98VO 1 5 V Output 1.5-V Output voltage (see Notes 2 and 4) MIN V 0.7 V 1 µA TJ = 25°C 55 dB NOTES: 2. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output current 1 mA. 3. If VO < 1.8 V then VI(max) = 10 V, VI(min) = 2.7 V: Line regulation (mV) + ǒ%ńVǓ f = 1 kHz, V O ǒVI(max) * 2.7 VǓ 100 1000 If VO > 2.5 V then VI(max) = 10 V, VI(min) = VO + 1 V: Line regulation (mV) + ǒ%ńVǓ V O ǒVI(max) * ǒVO ) 1ǓǓ 100 1000 4. IO = 1 mA to 250 mA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 electrical characteristics over recommended operating junction temperature range (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Trip threshold voltage I(PG) = 300 µA, VO decreasing Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, V(PG) = 5 V Minimum input voltage for valid PG PG (TPS774xx) Leakage current Reset (TPS773xx) V(PG) ≤ 0.8 V VDO UNIT 85 %VO %VO 1.1 I(PG) = 1 mA V Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, V(RESET) = 5 V 0.15 0.4 V 1 µA 1.1 92 V 98 %VO %VO 0.5 I(RESET) = 1 mA RESET time-out delay VDO MAX 0.5 Trip threshold voltage Leakage current TYP 79 I(RESET) = 300 µA VO decreasing Minimum input voltage for valid RESET MIN 0.15 0.4 V 1 µA 220 IO = 250 mA, IO = 250 mA TJ = 25°C 270 2 8 V Output 2.8-V TJ = 25°C 200 3 3 V Output 3.3-V IO = 250 mA, IO = 250 mA 5 0 V Output 5.0-V IO = 250 mA, IO = 250 mA TJ = 25°C Dropout voltage (see Note 5) Dropout voltage (see Note 5) ms 475 mV 330 125 190 NOTE 5: IN voltage equals VO(typ) – 100 mV; 1.5 V, 1.6 V, 1.8-V, and 2.7-V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input voltage needs to drop to 3.2 V for purpose of this test). TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 2, 3 vs Junction temperature 4, 5 Ground current vs Junction temperature 6 Power supply rejection ratio vs Frequency 7 Output spectral noise density vs Frequency 8 Zo Output impedance vs Frequency 9 vs Input voltage 10 VDO Dropout voltage vs Junction temperature 11 VO Output voltage Line transient response 12, 14 Load transient response 8 13, 15 Output voltage and enable pulse vs Time Equivalent series resistance (ESR) vs Output current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 18 – 21 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 TPS77x33 TPS77x18 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 3.302 1.802 3.301 1.801 VO – Output Voltage – V VO – Output Voltage – V TYPICAL CHARACTERISTICS 3.3 1.800 1.799 3.299 3.298 1.798 0 50 100 150 200 IO – Output Current – mA 0 250 50 100 150 200 IO – Output Current – mA Figure 2 Figure 3 TPS77x33 TPS77x18 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1.86 3.35 VI = 2.8 V VI = 4.3 V 1.84 VO – Output Voltage – V VO – Output Voltage – V 3.33 IO = 250 mA 3.31 3.29 1.82 1.80 IO = 1 mA IO = 50 mA IO = 250 mA 1.78 3.27 3.25 –40 250 0 40 80 120 TJ – Junction Temperature – °C 160 1.76 –40 0 40 80 120 160 TJ – Junction Temperature – °C Figure 5 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 TYPICAL CHARACTERISTICS TPS77xxx GROUND CURRENT vs JUNCTION TEMPERATURE 115 110 Ground Current – µ A 105 100 IO = 1 mA 95 90 85 IO = 250 mA 80 –40 10 60 110 160 TJ – Junction Temperature – °C Figure 6 TPS77x33 TPS77x33 POWER SUPPLY REJECTION RATIO vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 90 IO = 1 mA CO = 10 µF TJ = 25 °C Output Spectral Noise Density – µV Hz PSRR – Power Supply Rejection Ratio – dB 100 80 70 60 50 40 30 IO = 250 mA 20 10 0 10 100 1k 10k 100k 1M 10M CO = 10 µF TJ = 25 °C IO = 250 mA 1 IO = 1 mA 0.1 0.01 100 f – Frequency – Hz Figure 8 POST OFFICE BOX 655303 10k f – Frequency – Hz Figure 7 10 1k • DALLAS, TEXAS 75265 100k TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 TYPICAL CHARACTERISTICS TPS77x33 OUTPUT IMPEDANCE vs FREQUENCY 10 TJ = 25 °C Zo – Output Impedance – Ω IO = 1 mA 1 0.1 IO = 250 mA 0.01 10 100 1k 10k 100k f – Frequency – Hz 1M 10M Figure 9 TPS77x01 TPS77x33 DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 400 300 IO = 250 mA TJ = 125 °C 250 TJ = 25 °C 300 VDO – Dropout Voltage – mV VDO – Dropout Voltage – mV 350 TJ = –40 °C 250 200 150 100 200 150 100 IO = 10 mA 50 IO = 0 A 0 50 0 2.7 IO = 250 mA 3.2 3.7 4.2 VI – Input Voltage – V 4.7 –50 –40 0 40 80 120 TJ – Junction Temperature – °C 160 Figure 11 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 TPS77x18 TPS77x18 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE IO – Output Current – mA VI – Input Voltage – V TYPICAL CHARACTERISTICS 3.8 2.8 250 0 +50 ∆ VO – Change in Output Voltage – mV ∆ VO – Change in Output Voltage – mV 10 0 –10 CO = 10 µF TJ = 25 °C IO = 250 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t – Time – ms 0.9 0 –50 CO = 10 µF TJ = 25 °C IO = 250 mA 0 1 0.2 0.8 1 1.2 1.4 1.6 t – Time – ms 1.8 2 Figure 13 Figure 12 TPS77x33 TPS77x33 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE IO – Output Current – mA VI – Input Voltage – V 0.4 0.6 5.3 4.3 250 0 ∆ VO – Change in Output Voltage – mV ∆ VO – Change in Output Voltage – mV 10 0 –10 CO = 10 µF TJ = 25 °C IO = 250 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t – Time – ms 0.9 1 0 –50 CO = 10 µF TJ = 25 °C IO = 250 mA –100 0 0.1 0.4 0.5 0.6 0.7 0.8 t – Time – ms Figure 15 Figure 14 12 0.2 0.3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.9 1 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 TYPICAL CHARACTERISTICS TPS77x33 VO – Output Voltage – V Enable Pulse – V OUTPUT VOLTAGE AND ENABLE PULSE vs TIME (AT STARTUP) CO = 10 µF TJ = 25 °C EN 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t – Time – ms 1.6 1.8 2.0 Figure 16 VI To Load IN OUT + EN RL CO GND ESR Figure 17. Test Circuit for Typical Regions of Stability (Figures 18 through 21) (Fixed Output Options) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 Region of Instability ESR – Equivalent Series Resistance – Ω ESR – Equivalent Series Resistance – Ω 10 Region of Instability VO = 3.3 V CO = 1 µF VI = 4.3 V TJ = 25°C 1 Region of Stability 1 Region of Stability 0.1 VO = 3.3 V CO = 10 µF VI = 4.3 V TJ = 25°C Region of Instability Region of Instability 0.1 0 50 100 150 200 250 0.01 0 50 100 150 200 250 IO – Output Current – mA IO – Output Current – mA Figure 18 Figure 19 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 10 ESR – Equivalent Series Resistance – Ω ESR – Equivalent Series Resistance – Ω Region of Instability Region of Instability VO = 3.3 V CO = 1 µF VI = 4.3 V TJ = 125 °C 1 Region of Stability 1 Region of Stability 0.1 VO = 3.3 V CO = 10 µF VI = 4.3 V TJ = 125°C Region of Instability Region of Instability 0.01 0.1 0 50 100 150 200 250 0 50 100 150 200 250 IO – Output Current – mA IO – Output Current – mA Figure 20 Figure 21 † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 APPLICATION INFORMATION pin functions enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, then the device will be enabled. power good (PG) (TPS774xx) The PG terminal is an open drain, active high output that indicates the status of Vout (output of the LDO). When Vout reaches 82% of the regulated voltage, PG will go to a high-impedance state. It will go to a low-impedance state when Vout falls below 82% (i.e. over load condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. feedback (FB) FB is an input terminal used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. reset (RESET) (TPS773xx) The RESET terminal is an open drain, active low output that indicates the status of Vout. When Vout reaches 95% of the regulated voltage, RESET will go to a high-impedance state after a 220-ms delay. RESET will go to a low-impedance state when Vout is below 95% of the regulated voltage. The open-drain output of the RESET terminal requires a pullup resistor. external capacitor requirements An input capacitor is not usually required; however, a bypass capacitor (0.047 µF or larger) improves load transient response and noise rejection if the TPS773xx or TPS774xx is located more than a few inches from the power supply. A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Most low noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board space. The TPS773xx and TPS774xx have very low noise specification requirements without using any external components. Like all low dropout regulators, the TPS773xx or TPS774xx requires an output capacitor connected between OUT (output of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum recommended capacitance value is 1 µF provided the ESR meets the requirement in Figures 19 and 21. In addition, a low-ESR capacitor can be used if the capacitance is at least 10 µF and the ESR meets the requirements in Figures 18 and 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described previously. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 APPLICATION INFORMATION external capacitor requirements (continued) Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature; therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the requirement specified in Figures 18 – 21. Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage. IO LDO – VESR RESR + + VI RLOAD VO – CO Figure 22. LDO Output Stage With Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (VCout = Vout). This means no current is flowing into the Cout branch. If Iout suddenly increases (transient condition), the following occurs: D The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 23). Therefore, capacitor Cout provides the current for the new load condition (dashed arrow). Cout now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR. This voltage is shown as VESR in Figure 22. D When Cout is conducting current to the load, initial voltage at the load will be Vout = VCout – VESR. Due to the discharge of Cout, the output voltage Vout will drop continuously until the response time t1 of the LDO is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 23. The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: D The higher the ESR, the larger the droop at the beginning of load transient. D The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 APPLICATION INFORMATION conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. Iout Vout 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of Vout at a Load Step From Low-to-High Output Current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 APPLICATION INFORMATION programming the TPS77x01 adjustable LDO regulator The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as shown in Figure 24. The output voltage is calculated using: V O +V ǒ1 ) R1 Ǔ R2 ref (1) Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using: R1 + ǒ V V Ǔ O *1 ref (2) R2 OUTPUT VOLTAGE PROGRAMMING GUIDE TPS77x01 VI 0.1 µF PG or RESET IN PG or RESET Output 250 kΩ EN OUT VO R1 FB/SENSE GND CO R2 OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 33.5 30.1 kΩ 3.3 V 53.8 30.1 kΩ 3.6 V 61.5 30.1 kΩ NOTE: To reduce noise and prevent oscillation, R1 and R2 need to be as close as possible to the FB/SENSE terminal. Figure 24. TPS77x01 Adjustable LDO Regulator Programming 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 APPLICATION INFORMATION regulator protection The TPS773xx or TPS774xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS773xx or TPS774xx also features internal current limiting and thermal protection. During normal operation, the TPS773xx or TPS774xx limits output current to approximately 0.9 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P D(max) T max * T A + J R qJA Where: TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package, i.e., 266.2°C/W for the 8-terminal MSOP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: P D ǒ Ǔ + V *V I O I O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS281E – FEBRUARY 2000 – REVISED JULY 2001 MECHANICAL DATA DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°–ā6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/B 04/98 NOTES: A. B. C. D. 20 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS77301DGK ACTIVE MSOP DGK 8 TPS77301DGKR ACTIVE MSOP DGK TPS77301DGKRG4 ACTIVE MSOP TPS77315DGK ACTIVE TPS77315DGKR 80 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSOP DGK 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77315DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77316DGK ACTIVE MSOP DGK 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77316DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77316DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77318DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77318DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77318DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77318DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77327DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77327DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77327DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77327DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77328DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77328DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77328DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77328DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77333DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77333DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77333DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77333DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 80 80 Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS77350DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77350DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77350DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77350DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77401DGK ACTIVE MSOP DGK 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77401DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77401DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77415DGK ACTIVE MSOP DGK 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77415DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77415DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77418DGK ACTIVE MSOP DGK 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77418DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77418DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77427DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77427DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77427DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77427DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77428DGK ACTIVE MSOP DGK 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77428DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77428DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77433DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77433DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77433DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77433DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77450DGK ACTIVE MSOP DGK 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS77450DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 80 80 80 80 80 Addendum-Page 2 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Orderable Device Status (1) Package Type Package Drawing TPS77450DGKRG4 ACTIVE MSOP DGK Pins Package Eco Plan (2) Qty 8 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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