TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 D Open Drain Power-On Reset With 220-ms D D D D D D D D D D TPS771xx DGK Package (TOP VIEW) Delay (TPS771xx) Open Drain Power-Good (PG) Status Output (TPS772xx) 150-mA Low-Dropout Voltage Regulator Available in 1.5-V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions Dropout Voltage Typically 115 mV at 150 mA (TPS77133, TPS77233) Ultralow 92-µA Quiescent Current (Typ) 8-Pin MSOP (DGK) Package Low Noise (55 µVrms) Without External Filter (Bypass) Capacitor (TPS77118, TPS77218) 2% Tolerance Over Specified Conditions for Fixed-Output Versions Fast Transient Response Thermal Shutdown Protection FB/SENSE RESET EN GND 1 8 2 7 3 6 4 5 OUT OUT IN IN TPS772xx DGK Package (TOP VIEW) FB/SENSE PG EN GND 1 8 2 7 3 6 4 5 OUT OUT IN IN TPS77x33 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 description 250 VDO – Dropout Voltage – mV The TPS771xx and TPS772xx are low-dropout regulators with integrated power-on reset and power good (PG) function respectively. These devices are capable of supplying 150 mA of output current with a dropout of 115 mV (TPS77133, TPS77233). Quiescent current is 92 µA at full load dropping down to 1 µA when device is disabled. These devices are optimized to be stable with a wide range of output capacitors including low ESR ceramic (10 µF) or low capacitance (1 µF) tantalum capacitors. These devices have extremely low noise output performance (55 µVrms) without using any added filter capacitors. TPS771xx and TPS772xx are designed to have fast transient response for larger load current changes. 200 IO = 150 mA 150 100 IO = 10 mA 50 IO = 0 A 0 –50 –40 0 40 80 120 TJ – Junction Temperature – °C 160 The TPS771xx or TPS772xx is offered in 1.5 V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS771xx and TPS772xx families are available in 8-pin MSOP (DGK) packages. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 115 mV at an output current of 150 mA for 3.3 volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 µA over the full range of output current, 0 mA to 150 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 description (continued) The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = 25°C. The TPS771xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS) or reset output voltage. The RESET output of the TPS771xx initiates a reset in DSP, microcomputer or microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in the TPS771xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after a 220 ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage. For the TPS772xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS772xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage. AVAILABLE OPTIONS OUTPUT VOLTAGE (V) PACKAGED DEVICES MSOP (DGK) TJ TPS771xx SYMBOL TYP TPS772xx SYMBOL 5.0 TPS77150DGK AFV TPS77250DGK AGE 3.3 TPS77133DGK AFU TPS77233DGK AGD 2.8 TPS77128DGK AFS TPS77228DGK AGB 2.7 TPS77127DGK AFR TPS77227DGK AGA 1.8 TPS77118DGK AFP TPS77218DGK AFY 1.5 TPS77115DGK AFO TPS77215DGK AFX Adjustable 1.5 V to 5.5 V TPS77101DGK AFN TPS77201DGK AFW – 40°C to 125°C NOTE: The TPS77101 and TPS77201 are programmable using an external resistor divider (see application information). The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77101DGKR). VI 5 IN OUT 6 OUT IN SENSE 0.1 µF 3 PG or RESET EN 7 VO 8 1 2 GND PG or RESET + 10 µF 4 Figure 1. Typical Application Configuration (For Fixed Output Options) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 functional block diagrams adjustable version IN EN PG or RESET _ + OUT + _ 220 ms Delay (for TPS771xx Option) Vref = 1.1834 V R1 FB/SENSE R2 GND External to the Device fixed-voltage version IN EN PG or RESET _ + OUT + _ 220 ms Delay (for TPS771xx Option) SENSE R1 Vref = 1.1834 V R2 GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION TPS771XX FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) RESET 2 O Reset output EN 3 I Enable input GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) PG 2 O Power good EN 3 I Enable input TPS772XX GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage TPS771xx RESET timing diagram VI Vres† Vres† t VO VIT +‡ VIT +‡ Threshold Voltage VIT –‡ VIT –‡ t RESET Output Output Undefined ÎÎ ÎÎ ÎÎ ÎÎ 220 ms Delay 220 ms Delay ÎÎ ÎÎ ÎÎ ÎÎ Output Undefined t † Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡ VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TPS772xx PG timing diagram VI Vres† Vres† t VO VIT +‡ VIT +‡ Threshold Voltage VIT –‡ VIT –‡ t PG Output ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Output Undefined Output Undefined t † Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡ VIT – Trip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage. absolute maximum ratings over operating junction temperature range (unless otherwise noted)Ĕ Input voltage range, VI, (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 13.5 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V Maximum RESET voltage (TPS771xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Maximum PG voltage (TPS772xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network terminal ground. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES PACKAGE AIR FLOW (CFM) θJA (°C/W) θJC (°C/W) TA < 25°C POWER RATING 0 266.2 3.84 DGK 150 255.2 3.92 250 242.8 4.21 DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 376 mW 3.76 mW/°C 207 mW 150 mW 392 mW 3.92 mW/°C 216 mW 157 mW 412 mW 4.12 mW/°C 227 mW 165 mW recommended operating conditions MIN Input voltage, VI† Output voltage range, VO Output current, IO (see Note 2) MAX UNIT 2.7 10 V 1.5 5.5 V 0 150 mA Operating virtual junction temperature, TJ (see Note 2) – 40 125 °C † To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 2: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 electrical characteristics over recommended operating junction temperature range (–40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) PARAMETER TEST CONDITIONS 1.5 V ≤ VO ≤ 5.5 V, Adjustable voltage Out ut voltage Output (see Notes 3 and 4) MIN TJ = 25°C 1.5 V ≤ VO ≤ 5.5 V TJ = 25°C, 2.7 V < VIN < 10 V 2.7 V < VIN < 10 V 1 8 V Output 1.8-V TJ = 25°C, 2.8 V < VIN < 10 V 2.8 V < VIN < 10 V 2 7 V Output 2.7-V TJ = 25°C, 3.7 V < VIN < 10 V 3.7 V < VIN < 10 V 2 8 V Output 2.8-V TJ = 25°C, 3.8 V < VIN < 10 V 3.8 V < VIN < 10 V 3 3 V Output 3.3-V TJ = 25°C, 4.3 V < VIN < 10 V 4.3 V < VIN < 10 V 5 0 V Output 5.0-V TJ = 25°C, 6 V < VIN < 10 V 6 V < VIN < 10 V 1.02VO 1.470 1.530 1.764 1.836 2.7 2.646 2.754 Output current Limit 2.856 3.3 3.234 3.366 5.0 4.900 5.100 92 VO + 1 V < VI ≤ 10 V, TJ = 25°C VO + 1 V < VI ≤ 10 V VO = 0 V 2 ms pulse width, Peak output current 0.005 EN = VI, TJ = 25°C EN = VI Adjustable voltage FB = 1.5 V High level enable input voltage Enable input current –1 Power supply ripple rejection (TPS77118, TPS77218) %/V mV 55 µVrms 1.3 A 400 mA 144 °C 1 µA 3 µA 1 µA 2 Low level enable input voltage µA A 1 0.9 50% duty cycle V %/V 0.05 Thermal shutdown junction temperature Standby current V 2.8 2.744 TJ = 25°C BW = 300 Hz to 100 kHz, TJ = 25°C, TPS77118, TPS77218 Output noise voltage V 1.8 125 Load regulation UNIT 1.5 TJ = 25°C Output voltage line regulation (∆VO/VO) (see Note 5) FB input current MAX VO 0.98VO 1 5 V Output 1.5-V Quiescent current (GND current) (see Notes 3 and 4) TYP V 0.7 V 1 µA TJ = 25°C 55 dB NOTES: 3. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output current 1 mA. 4. If VO < 1.8 V then VI(max) = 10 V, VI(min) = 2.7 V: Line regulation (mV) + ǒ%ńVǓ f = 1 KHz, V O ǒVI(max) * 2.7 VǓ 100 1000 If VO > 2.5 V then VI(max) = 10 V, VI(min) = Vo + 1 V: Line regulation (mV) + ǒ%ńVǓ V O ǒVI(max) * ǒVO ) 1ǓǓ 100 1000 5. IO = 1 mA to 150 mA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 electrical characteristics over recommended operating junction temperature range (–40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Minimum input voltage for valid PG PG (TPS772xx) Trip threshold voltage I(PG) = 300µA VO decreasing Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, V(PG) = 5 V Leakage current Reset (TPS771xx) V(PG) ≤ 0.8 V UNIT 85 %VO %VO 1.1 I(PG) = 1mA V Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, V(RESET) = 5 V 0.15 0.4 V 1 µA 1.1 92 V 98 %VO %VO 0.5 I(RESET) = 1 mA RESET time-out delay VDO MAX 0.5 Trip threshold voltage Leakage current TYP 79 I(RESET) = 300 µA VO decreasing Minimum input voltage for valid RESET MIN 0.15 0.4 V 1 µA 220 Dropout voltage (see Note 6) IO = 150 mA, IO = 150 mA, TJ = 25°C 150 2 8 V Output 2.8-V TJ = 25°C 115 3 3 V Output 3.3-V IO = 150 mA, IO = 150 mA 5 0 V Output 5.0-V IO = 150 mA, IO = 150 mA TJ = 25°C ms 265 mV 200 75 115 NOTE 6: IN voltage equals VO(typ) – 100 mV; 1.5 V, 1.8 V, and 2.7 V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input voltage needs to drop to 3.2 V for purpose of this test). TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 2, 3 vs Junction temperature 4, 5 Ground current vs Junction temperature 6 Power supply rejection ratio vs Frequency 7 Output spectral noise density vs Frequency 8 Zo Output impedance vs Frequency 9 vs Input voltage 10 VDO Dropout voltage vs Junction temperature 11 VO Output voltage Line transient response 12, 14 Load transient response 8 13, 15 Output voltage and enable pulse vs Time Equivalent series resistance (ESR) vs Output current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 18 – 21 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TPS77x33 TPS77x18 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 3.302 1.802 3.301 1.801 VO – Output Voltage – V VO – Output Voltage – V TYPICAL CHARACTERISTICS 3.3 1.800 1.799 3.299 3.298 1.798 0 50 100 IO – Output Current – mA 0 150 50 100 IO – Output Current – mA Figure 2 Figure 3 TPS77x33 TPS77x18 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1.86 3.35 VI = 2.8 V VI = 4.3 V 1.84 VO – Output Voltage – V VO – Output Voltage – V 3.33 IO = 150 mA 3.31 3.29 1.82 IO = 150 mA 1.80 1.78 3.27 3.25 –40 150 0 40 80 120 TJ – Junction Temperature – °C 160 1.76 –40 0 40 80 120 160 TJ – Junction Temperature – °C Figure 5 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77xxx GROUND CURRENT vs JUNCTION TEMPERATURE 115 110 Ground Current – µ A IO = 150 mA 105 100 95 IO = 1 mA 90 85 80 –40 10 60 110 160 TJ – Junction Temperature – °C Figure 6 TPS77x33 TPS77x33 POWER SUPPLY REJECTION RATIO vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 CO = 10 µF TJ = 25°C IO = 1 mA 90 Output Spectral Noise Density – µV Hz PSRR – Power Supply Rejection Ratio – dB 100 80 70 60 50 40 30 IO = 150 mA 20 10 0 10 100 1k 10k 100k 1M 10M IO = 150 mA 1 IO = 1 mA 0.1 0.01 100 f – Frequency – Hz 1k 10k f – Frequency – Hz Figure 7 10 CO = 10 µF TJ = 25°C Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100k TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77x33 OUTPUT IMPEDANCE vs FREQUENCY 10 Zo – Output Impedance – Ω IO = 1 mA 1 0.1 IO = 150 mA 0.01 10 100 1k 10k 100k f – Frequency – Hz 1M 10M Figure 9 TPS77x01 TPS77x33 DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 250 250 TJ = 125 °C 200 VDO – Dropout Voltage – mV VDO – Dropout Voltage – mV IO = 150 mA TJ = 25 °C TJ = –40 °C 150 100 50 200 IO = 150 mA 150 100 IO = 10 mA 50 IO = 0 A 0 0 2.7 3.2 3.7 4.2 VI – Input Voltage – V 4.7 –50 –40 0 40 80 120 TJ – Junction Temperature – °C 160 Figure 11 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77x18 I O – Output Current – mA TPS77x18 VI – Input Voltage – V LINE TRANSIENT RESPONSE 3.8 2.8 ∆ VO – Change in Output Voltage – mV ∆ VO – Change in Output Voltage – mV 10 0 –10 IO = 150 mA CO = 10 µF TJ = 25°C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t – Time – ms 0.9 LOAD TRANSIENT RESPONSE 150 0 0 –50 IO = 150 mA CO = 10 µF TJ = 25°C –100 0 1 0.1 TPS77x33 LOAD TRANSIENT RESPONSE I O – Output Current – mA TPS77x33 LINE TRANSIENT RESPONSE 5.3 4.3 0.9 1 150 0 +10 ∆ VO – Change in Output Voltage – mV ∆ VO – Change in VI – Input Voltage – V Output Voltage – mV 0.4 0.5 0.6 0.7 0.8 t – Time – ms Figure 13 Figure 12 0 –10 IO = 150 mA CO = 10 µF TJ = 25°C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t – Time – ms 0.9 1 0 –50 IO = 150 mA CO = 10 µF TJ = 25°C –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t – Time – ms Figure 15 Figure 14 12 0.2 0.3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.9 1 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77x33 VO – Output Voltage – V Enable Pulse – V OUTPUT VOLTAGE AND ENABLE PULSE vs TIME (AT STARTUP) CO = 10 µF TJ = 25°C EN 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t – Time – ms 1.6 1.8 2.0 Figure 16 VI To Load IN OUT + EN RL CO GND ESR Figure 17. Test Circuit for Typical Regions of Stability (Figures 18 through 21) (Fixed Output Options) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 10 ESR – Equivalent Series Resistance – Ω ESR – Equivalent Series Resistance – Ω Region of Instability Region of Instability VO = 3.3 V CO = 1 µF VI = 4.3 V TJ = 25°C 1 Region of Stability 1 Region of Stability 0.1 VO = 3.3 V CO = 10 µF VI = 4.3 V TJ = 25°C Region of Instability 0.1 0 50 100 0.01 150 Region of Instability 0 50 IO – Output Current – mA Figure 18 150 Figure 19 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 10 Region of Instability Region of Instability ESR – Equivalent Series Resistance – Ω ESR – Equivalent Series Resistance – Ω 100 IO – Output Current – mA VO = 3.3 V CO = 1 µF VI = 4.3 V TJ = 125 °C 1 Region of Stability 1 Region of Stability 0.1 VO = 3.3 V CO = 10 µF VI = 4.3 V TJ = 125°C Region of Instability 0.1 0 50 100 150 Region of Instability 0.01 0 IO – Output Current – mA 50 100 150 IO – Output Current – mA Figure 20 Figure 21 † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION pin functions enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, then the device will be enabled. power good (PG) (TPS772xx) The PG terminal is an open drain, active high output that indicates the status of Vout (output of the LDO). When Vout reaches 82% of the regulated voltage, PG will go to a high-impedance state. It will go to a low-impedance state when Vout falls below 82% (i.e. over load condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. feedback (FB) FB is an input terminal used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. reset (RESET) (TPS771xx) The RESET terminal is an open drain, active low output that indicates the status of Vout. When Vout reaches 95% of the regulated voltage, RESET will go to a high-impedance state after a 220-ms delay. RESET will go to a low-impedance state when Vout is below 95% of the regulated voltage. The open-drain output of the RESET terminal requires a pullup resistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION external capacitor requirements An input capacitor is not usually required; however, a bypass capacitor (0.047 µF or larger) improves load transient response and noise rejection if the TPS771xx or TPS772xx is located more than a few inches from the power supply. A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Most low noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board space. The TPS771xx and TPS772xx have very low noise specification requirements without using any external components. Like all low dropout regulators, the TPS771xx or TPS772xx requires an output capacitor connected between OUT (output of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum recommended capacitance value is 1 µF provided the ESR meets the requirement in Figures 19 and 21. In addition, a low-ESR capacitor can be used if the capacitance is at least 10 µF and the ESR meets the requirements in Figures 18 and 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described previously. Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature; therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the requirement specified in Figures 18 – 21. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage. IO LDO – VESR RESR + + VI RLOAD VO – CO Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (VCout = Vout). This means no current is flowing into the Cout branch. If Iout suddenly increases (transient condition), the following occurs: D The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 23). Therefore, capacitor Cout provides the current for the new load condition (dashed arrow). Cout now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR. This voltage is shown as VESR in Figure 22. D When Cout is conducting current to the load, initial voltage at the load will be Vout = VCout – VESR. Due to the discharge of Cout, the output voltage Vout will drop continuously until the response time t1 of the LDO is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 23. The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: D The higher the ESR, the larger the droop at the beginning of load transient. D The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. Iout Vout 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of Vout at a Load Step From Low-to-High Output Current 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION programming the TPS77x01 adjustable LDO regulator The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as shown in Figure 24. The output voltage is calculated using: V O +V ǒ1 ) R1 Ǔ R2 ref (1) Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using: R1 + ǒ V V Ǔ O *1 ref (2) R2 OUTPUT VOLTAGE PROGRAMMING GUIDE TPS77x01 VI 0.1 µF PG or RESET IN PG or RESET Output 250 kΩ EN OUT VO R1 FB/SENSE GND CO R2 OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 33.5 30.1 kΩ 3.3 V 53.8 30.1 kΩ 3.6 V 61.5 30.1 kΩ NOTE: To reduce noise and prevent oscillation, R1 and R2 need to be as close as possible to the FB/SENSE terminal. Figure 24. TPS77x01 Adjustable LDO Regulator Programming POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION regulator protection The TPS771xx or TPS772xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS771xx or TPS772xx also features internal current limiting and thermal protection. During normal operation, the TPS771xx or TPS772xx limits output current to approximately 0.9 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P D(max) T max * T A + J R qJA Where: TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package, i.e., 266.2°C/W for the 8-terminal MSOP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: P D ǒ Ǔ + V *V I O I O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 MECHANICAL DATA DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°–ā6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. 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