TI TS12A44514PWR

TS12A44513,, TS12A44514,, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
LOW ON-STATE RESISTANCE
QUAD SPST CMOS ANALOG SWITCHES
FEATURES
1
•
•
•
•
2-V to 12-V Single-Supply Operation
Specified ON-State Resistance:
– 15 Ω Max With 12-V Supply
– 20 Ω Max With 5-V Supply
– 50 Ω Max With 3.3-V Supply
RDSON Matching
– 2.5 Ω (Max) at 12 V
– 3 Ω (Max) at 5 V
– 3.5 Ω (Max) at 3.3 V
D OR PW PACKAGE...TS12A44513
(TOP VIEW)
NO1 1
COM1 2
NC2
3
12 IN4
COM2
4
11 NC4
IN2
5
•
•
•
•
•
D OR PW PACKAGE...TS12A44514
(TOP VIEW)
14 V+
13 IN1
•
Specified Low OFF-Leakage Currents:
– 1 nA at 25°C
– 10 nA at 85°C
Specified Low ON-Leakage Currents:
– 1 nA at 25°C
– 10 nA at 85°C
Low Charge Injection: 11.5 pC (12-V Supply)
Fast Switching Speed:
tON = 80 ns, tOFF = 50 ns (12-V Supply)
Break-Before-Make Operation (tON > tOFF)
TTL/CMOS-Logic Compatible With 5-V Supply
Available in TSSOP-14 Package, SOIC-14
NO1 1
COM1 2
14 V+
13 IN1
NO2
3
12 IN4
COM2
4
11 NO4
10 COM4
IN2
5
IN3
6
GND
7
IN3
6
9
COM3
GND
7
8
NO3
D OR PW PACKAGE...TS12A44515
(TOP VIEW)
NC1 1
COM1 2
14 V+
13 IN1
NC2
3
12 IN4
COM2
4
11 NC4
10 COM4
IN2
5
10 COM4
9
COM3
IN3
6
9
COM3
8
NO3
GND
7
8
NC3
DESCRIPTION/ORDERING INFORMATION
The TS12A44513/TS12A44514/TS12A44515 are quad single pole/single throw (SPST), low-voltage / wide range,
single-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A44513 has two
switches normally closed (NC) and two switches normally open (NO), the TS12A44514 switches are normally
open (NO), the TS12A44515 switches are normally closed (NC).
These CMOS switches can operate continuously with a single supply between 2 V and 12 V. Each switch can
handle rail-to-rail analog signals. The OFF-leakage current maximum is only 1 nA at 25°C or 10 nA at 85°C.
All digital inputs have 0.8-V to 2.4-V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a 5-V
supply.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TS12A44513,, TS12A44514,, TS12A44515
SCDS247 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com
ORDERING INFORMATION
TA
PACKAGE
SOIC – D
–40°C to 85°C
TSSOP – PW
(1)
(2)
(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Reel of 2500
TS12A44513DR
TS12A44513
Reel of 2500
TS12A44514DR
TS12A44514
Reel of 2500
TS12A44515DR
TS12A44515
Reel of 2000
TS12A44513PWR
YD4513
Reel of 2000
TS12A44514PWR
YD4514
Reel of 2000
TS12A44515PWR
YD4515
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MINIMUM AND MAXIMUM RATINGS (1) (2)
voltages referenced to GND
V+
Supply voltage range
VNC
VNO Analog voltage range (3)
VCOM
INC
INO
ICOM
Analog Current range
MIN
MAX
–0.3
13
V
–0.3 V+ + 0.3
V
-20
20
mA
Continuous current into any terminal
±20
mA
Peak current, NO or COM (pulsed at 1 ms, 10% duty cycle)
±30
mA
2000
V
85
°C
ESD per method 3015.7
TA
Operating temperature range
PD
Power dissipation
Tstg
Storage temperature range
–40
Mounted on JEDEC 4-layer board (JESD
51-7), No airflow, TA = 25°C, TJ = 125°C
D package
1.15
PW package
0.88
–65
Lead temperature (soldering, 10 s)
(1)
(2)
(3)
UNIT
W
150
°C
300
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
Voltages exceeding V+ or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current
rating.
THERMAL IMPEDANCE
UNIT
θJA
2
Thermal impedance,
junction to free air
Mounted on JEDEC 1-layer board (JESD 51-3),
No airflow
D package
133
PW package
167
Mounted on JEDEC 4-layer board (JESD 51-7),
No airflow
D package
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PW package
86
°C/W
112
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515
TS12A44513,, TS12A44514,, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
ELECTRICAL CHARACTERISTICS FOR 5-V SUPPLY (1)
V+ = 4.5 V to 5.5 V, VINH = 2.4 V, VINL = 0.8 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP (2)
TA
MAX
UNIT
Analog Switch
Analog signal range
VCOM, VNO, VNC
0
ON-state resistance
ron
ON-state resistance
flatness
ron(flat)
ON-state resistance
matching between
channels (3)
Δron
V+ = 4.5 V, ICOM = 5 mA,
VNO or VNC = 3 V
NO, NC
OFF leakage current (4)
INO(OFF),
INC(OFF)
V+ = 5.5 V, VCOM = 1 V,
VNO or VNC = 4.5 V
25°C
1
Full
10
COM
OFF leakage current (4)
ICOM(OFF)
V+ = 5.5 V, VCOM = 1 V,
VNO or VNC = 4.5 V
25°C
1
Full
10
COM
ON leakage current (4)
ICOM(ON)
V+ = 5.5 V, VCOM = 4.5 V,
VNO or VNC = 4.5 V
25°C
1
Full
10
V+ = 4.5 V, VCOM = 3.5 V,
ICOM = 1 mA
25°C
VCOM = 1 V, 2 V, 3 V,
ICOM = 1 mA
25°C
V+
12
Full
20
30
1
3
Full
4
25°C
3
TMIN to TMAX
4
V
Ω
Ω
Ω
nA
nA
nA
Digital Control Input (IN)
Input logic high
VIH
Full
2.4
V+
Input logic low
VIL
Full
0
0.8
V
0.01
µA
Input leakage current
Full
V
IIH, IIL
VIN = V+, 0 V
Turn-on time
tON
see Figure 6
Turn-off time
tOFF
see Figure 6
Charge injection (5)
QC
CL = 1 nF, VNO = 0 V,
RS = 0 Ω, See Figure 5
25°C
–1.5
pC
NO, NC
OFF capacitance
CNO(OFF),
CNC(OFF)
f = 1 MHz, See Figure 8
25°C
8
pF
COM
OFF capacitance
CCOM(OFF)
f = 1 MHz, See Figure 8
25°C
8
pF
COM
ON capacitance
CCOM(ON)
f = 1 MHz, See Figure 8
25°C
19
pF
VIN = V+, 0 V
25°C
2
pF
Dynamic
Digital input capacitance
CI
25°C
45
Full
100
125
25°C
35
Full
50
70
ns
ns
Bandwidth
BW
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
530
MHz
OFF isolation
OISO
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
–94
dB
Total harmonic distortion
THD
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
0.09
%
Supply
V+ supply current
(1)
(2)
(3)
(4)
(5)
I+
VIN = 0 V or V+
25°C
0.05
Full
0.1
µA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Typical values are at TA = 25°C.
ΔrON = rON(MAX) – rON(MIN)
Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
Specified by design, not production tested
Copyright © 2008, Texas Instruments Incorporated
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3
TS12A44513,, TS12A44514,, TS12A44515
SCDS247 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS FOR 12-V SUPPLY (1)
V+ = 11.4 V to 12.6 V, VINH = 5 V, VINL = 0.8 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP (2)
TA
MAX
UNIT
Analog Switch
Analog signal range
VCOM, VNO, VNC
0
ON-state resistance
ron
ON-state resistance
flatness
ron(flat)
ON-state resistance
matching between
channels (3)
Δron
V+ = 11.4 V, ICOM = 5 mA,
VNO or VNC = 10 V
NO, NC
OFF leakage current (4)
INO(OFF),
INC(OFF)
V+ = 12.6 V, VCOM = 1 V,
VNO or VNC = 10 V
25°C
1
Full
10
COM
OFF leakage current (4)
ICOM(OFF)
V+ = 12.6 V, VCOM = 1 V,
VNO or VNC = 10 V
25°C
1
Full
10
COM
ON leakage current (4)
ICOM(ON)
V+ = 12.6 V, VCOM = 10 V,
VNO or VNC = 10 V
25°C
1
Full
10
V+ = 11.4 V, VCOM = 10 V,
ICOM = 1 mA
25°C
V+ = 11.4 V,
VCOM = 2 V, 5 V, 10 V,
ICOM = 1 mA
25°C
V+
6.5
Full
10
15
1.5
V
Ω
3
Full
4
25°C
2.5
TMIN to TMAX
3
Ω
Ω
nA
nA
nA
Digital Control Input (IN)
Input logic high
VIH
Full
5
V+
V
Input logic low
VIL
Full
0
0.8
V
0.001
µA
Input leakage current
IIH, IIL
VIN = V+, 0 V
Full
Turn-on time
tON
See Figure 6
Turn-off time
tOFF
See Figure 6
Charge injection (5)
QC
CL = 1 nF, VNO = 0 V,
RS = 0 Ω, See Figure 5
25°C
–10.5
pC
NO, NC
OFF capacitance
CNO(OFF),
CNC(OFF)
f = 1 MHz, See Figure 8
25°C
8
pF
COM
OFF capacitance
CCOM(OFF)
f = 1 MHz, See Figure 8
25°C
8
pF
COM
ON capacitance
CCOM(ON)
f = 1 MHz, See Figure 8
25°C
21.5
pF
VIN = V+, 0 V
25°C
2
pF
25°C
530
MHz
Dynamic
Digital input capacitance
CI
25°C
25
Full
75
80
25°C
20
Full
45
50
ns
ns
Bandwidth
BW
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
OFF isolation
OISO
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
–95
dB
Total harmonic distortion
THD
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
0.07
%
Supply
V+ supply current
(1)
(2)
(3)
(4)
(5)
4
I+
VIN = 0 V or V+
25°C
0.05
Full
0.2
µA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Typical values are at TA = 25°C.
ΔrON = rON(MAX) – rON(MIN)
Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
Specified by design, not production tested
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515
TS12A44513,, TS12A44514,, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
ELECTRICAL CHARACTERISTICS FOR 3-V SUPPLY (1)
V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP (2)
TA
MAX
UNIT
Analog Switch
Analog signal range
VCOM, VNO, VNC
0
V+
ON-state resistance
ron
V+ = 3 V, VCOM = 1.5 V,
INO = 1 mA,
25°C
ON-state resistance
flatness
V+ = 3 V,
VCOM = 1 V, 1.5 V, 2 V,
ICOM = 1 mA
25°C
ron(flat)
ON-state resistance
matching between
channels (3)
Δron
V+ = 2.7 V, ICOM = 5 mA,
VNO or VNC = 1.5 V
NO, NC
OFF leakage current (4)
INO(OFF),
INC(OFF)
V+ = 3.6 V, VCOM = 1 V,
VNO or VNC = 3 V
25°C
1
Full
10
COM
OFF leakage current (4)
ICOM(OFF)
V+ = 3.6 V, VCOM = 1 V,
VNO or VNC = 3 V
25°C
1
Full
10
COM
ON leakage current (4)
ICOM(ON)
V+ = 3.6 V, VCOM = 3 V,
VNO or VNC = 3 V
25°C
1
Full
10
20
Full
40
50
1
V
Ω
3
Full
4
25°C
3.5
TMIN to TMAX
4.5
Ω
Ω
nA
nA
nA
Digital Control Input (IN)
Input logic high
VIH
Full
2.4
V+
V
Input logic low
VIL
Full
0
0.8
V
0.01
µA
Input leakage current
IIH, IIL
VIN = V+, 0 V
Full
Turn-on time (5)
tON
See Figure 6
Turn-off time (5)
tOFF
See Figure 6
Charge injection (5)
QC
CL = 1 nF, See Figure 5
25°C
–0.5
pC
NO, NC
OFF capacitance
CNO(OFF),
CNC(OFF)
f = 1 MHz, See Figure 8
25°C
8
pF
COM
OFF capacitance
CCOM(OFF)
f = 1 MHz, See Figure 8
25°C
8
pF
COM
ON capacitance
CCOM(ON)
f = 1 MHz, See Figure 8
25°C
17
pF
VIN = V+, 0 V
25°C
2
pF
Dynamic
Digital input capacitance
CI
25°C
70
Full
120
175
25°C
50
Full
80
120
ns
ns
Bandwidth
BW
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
510
MHz
OFF isolation
OISO
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
–94
dB
Total harmonic distortion
THD
RL = 50 Ω, CL = 15 pF,
VNO = 1 VRMS, f = 100 kHz
25°C
0.27
%
Supply
V+ supply current
(1)
(2)
(3)
(4)
(5)
I+
VIN = 0 V or V+
25°C
0.03
Full
0.05
µA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Typical values are at TA = 25°C.
ΔrON = rON(MAX) – rON(MIN)
Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25°C.
Specified by design, not production tested
Copyright © 2008, Texas Instruments Incorporated
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TS12A44513,, TS12A44514,, TS12A44515
SCDS247 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com
TYPICAL PERFORMANCE
25
30
TA = 85°C
25
20
15
ON-State Resistance, rON (Ω)
ON-State Resistance, rON (Ω)
V+ = 3 V
V+ = 4.5 V
10
V+ = 11.4 V
5
0
TA = 25°C
20
TA = –40°C
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
Analog Signal, VCOM (V)
20
20
TA = 85°C
TA = 25°C
TA = –40°C
10
3
4
Figure 2. rON vs VCOM (V+ = 3 V)
25
ON-State Resistance, rON (Ω)
ON-State Resistance, rON (Ω)
Figure 1. rON vs VCOM (TA = 25°C)
25
15
2
Analog Signal, VCOM (V)
5
TA = 85°C
15
TA = 25°C
TA = –40°C
10
5
VDD = 5.5 V
0
0
0
6
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10 11 12
Analog Signal, VCOM (V)
Analog Signal, VCOM (V)
Figure 3. rON vs VCOM (V+ = 4.5 V)
Figure 4. rON vs VCOM (V+ = 11.4 V)
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Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515
TS12A44513,, TS12A44514,, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
PIN DESCRIPTION (1)
PIN NO.
TS12A44513
TS12A44514
TS12A44515
NAME
DESCRIPTION
TSSOP-14
(1)
2, 4, 9, 10
2, 4, 9, 10
2, 4, 9, 10
COM
14
14
14
V+
Common
Power supply
5, 6, 12, 13
5, 6, 12, 13
5, 6, 12, 13
IN
Digital control to connect COM to NO or NC
7
7
7
GND
Digital ground
1, 8
1, 3, 8, 11
–
NO
Normally open
3, 11
–
1, 3, 8, 11
NC
Normally closed
NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in both
directions.
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TS12A44513,, TS12A44514,, TS12A44515
SCDS247 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com
APPLICATION INFORMATION
Power-Supply Considerations
The TS12A44513/TS12A44514/TS12A44515 construction is typical of most CMOS analog switches, except that
they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog
voltage limits. Reverse ESD-protection diodes connected in series are internally connected between each
analog-signal pin and both V+ and GND. If an analog signal exceeds V+ or GND, one of the diodes will be
forward biased, but the other will be reverse biased preventing current flow.
Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a
given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is
biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The
difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current.
All analog leakage current flows between each pin and one of the supply terminals, not to the other switch
terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity.
There is no connection between the analog-signal paths and V+ or GND.
V+ and GND also power the internal logic and logic-level translators. The logic-level translators convert the logic
levels to switched V+ and GND signals to drive the analog signal gates.
Logic-Level Thresholds
The logic-level thresholds are CMOS/TTL compatible when V+ is 5 V. As V+ is raised, the level threshold
increases slightly. When V+ reaches 12 V, the level threshold is about 3 V – above the TTL-specified high-level
minimum of 2.8 V, but still compatible with CMOS outputs.
CAUTION:
Do not connect the TS12A44513/TS12A44514/MAS4515 V+ to 3 V and then
connect the logic-level pins to logic-level signals that operate from 5-V supply.
Output levels can exceed 3 V and violate the absolute maximum ratings,
damaging the part and/or external circuits.
High-Frequency Performance
In 50-Ω systems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics).
Above 20 MHz, the on response has several minor peaks that are highly layout dependent. The problem is not in
turning the switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencies
with less attenuation. At 10 MHz, OFF isolation is about –45 dB in 50-Ω systems, decreasing (approximately 20
dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFF
isolation is about 3 dB above that of a bare IC socket, and is due entirely to capacitive coupling.
Test Circuits/Timing Diagrams
V+
V+
NO
TS12A44513
TS12A44514
TS12A44515
VIN
IN
COM
GND
50 Ω
VNO or VNC = 0 V
V+
VIN
0V
TS12A44514
TS12A44515
VOUT
VOUT
∆VOUT
CL
1000 pF
∆VOUT is the measured voltage due to charge
transfer error Q when the channel turns off.
Q = VOUT x CL
Figure 5. Charge Injection
8
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TS12A44513,, TS12A44514,, TS12A44515
www.ti.com ............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
V+
V+
V+
NO
0V
VNO
TS12A44513
TS12A44514
VIN
IN
50%
VIN
VNOPEAK
COM
90%
90%
VOUT
VOUT
GND
50 Ω
35 pF
300 Ω
0V
tON
V+
V+
0V
VNO
NC
TS12A44513
TS12A44515
VNOPEAK
COM
IN
50%
VIN
V+
VIN
tOFF
GND
50 Ω
90%
VOUT
VOUT
35 pF
300 Ω
90%
0V
tOFF
tON
Figure 6. Switching Times
V+
10 nF
V+
NO
VIN
50 Ω
50 Ω
TS12A44513/14/15
VOUT
V+
MEAS
REF
COM
IN
GND
50 Ω 50 Ω
Measurements are standardized against short at socket
terminals. OFF isolation is measured between COM and OFF
terminals on each switch. ON loss is measured between COM
and ON terminals on each switch. Signal direction through
switch is reversed; worst values are recorded.
OFF Isolation = 20log
VOUT
VIN
ON Loss = 20log
VOUT
VIN
Figure 7. OFF Isolation and ON Loss
V+
V+
NO
or
NC
TS12A44513/14/15
As
Required
IN
COM
GND
1-MHz
Capacitance
Analyzer
Figure 8. NO, NC, and COM Capacitance
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9
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TS12A44513DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44513DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44513PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44513PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44514DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44514DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44514PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44514PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44515DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44515DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44515PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS12A44515PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2008
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TS12A44513DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TS12A44513PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TS12A44514DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TS12A44514PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TS12A44515DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TS12A44515PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS12A44513DR
SOIC
D
14
2500
346.0
346.0
33.0
TS12A44513PWR
TSSOP
PW
14
2000
346.0
346.0
29.0
TS12A44514DR
SOIC
D
14
2500
346.0
346.0
33.0
TS12A44514PWR
TSSOP
PW
14
2000
346.0
346.0
29.0
TS12A44515DR
SOIC
D
14
2500
346.0
346.0
33.0
TS12A44515PWR
TSSOP
PW
14
2000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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