TLC5923 www.ti.com SLVS550 – DECEMBER 2004 LED DRIVER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 16 Channels Drive Capability – 0 to 80 mA (Constant-Current Sink) Constant Current Accuracy – ±1% (typical) Serial Data Interface Fast Switching Output: Tr / Tf = 10ns (typical) CMOS Level Input/Output 30 MHz Data Transfer Rate VCC = 3.0 V to 5.5 V Operating Temperature = -20°C to 85 °C LED Supply Voltage up to 17 V 32-pin HTSSOP (PowerPAD™) Package Dot Correction – 7 bit (128 Steps) – individual adjustable for each channel Controlled In-Rush Current Error Information – LOD: LED Open Detection – TEF: Thermal Error Flag VCC GND PGND SCLK SIN Monocolor, Multicolor, Fullcolor LED Display Monocolor, Multicolor LED Signboard Display Backlighting Multicolor LED lighting applications DESCRIPTION The TLC5923 is a 16 channel constant-current sink driver. Each channel has a On/Off state and a 128-step adjustable constant current sink (dot correction). The dot correction adjusts the brightness variations between LED, LED channels and other LED drivers. Both dot correction and On/Off state are accessible via a serial data interface. A single external resistor sets the maximum current of all 16 channels. The TLC5923 features two error information circuits. The LED open detection (LOD) indicates a broken or disconnected LED at an output terminal. The thermal error flag (TEF) indicates an overtemperature condition. MODE XLAT BLANK MODE 0 1 1 LOD 0 0 On/Off Register 0 IREF 0 Max. OUTn Current Constant Current Driver Delay x0 OUT0 0 7−bit DC Register 6 On/Off Input Shift Register BLANK 16 LOD 1 16 1 On/Off Register 15 0 LED Open Detection (LOD) Constant Current Driver Delay x1 OUT1 112 7 7−bit DC Register 13 DC Input Shift Register BLANK Temperature Error Flag (TEF) BLANK 1 0 LOD 111 XERR 0 1 MODE 15 15 On/Off Register Constant Current Driver Delay x15 OUT15 105 7−bit DC Register 111 SOUT Figure 1. Function Block Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated TLC5923 www.ti.com SLVS550 – DECEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) TA Package Part Number (1) -20 °C to 85 °C 4 mm x 4 mm, 32-pin HTSSOP TLC5923DAP The DAP package is available in tape and reel. Add R suffix (TLC5923DAPR) to order quantities of 2000 parts per reel. ABSOLUTE MAXIMUM RATINGS (1) (2) TLC5923 UNIT - 0.3 to 6 V 90 mA - 0.3 to VCC + 0.3 V VCC Supply voltage (2) IO Output current (dc) IL(LC) VI Input voltage range (2) V(BLANK), V(XLAT), V(SCLK), V(SIN), V(MODE) V(SOUT), V(XDOWN) - 0.3 to VCC + 0.3 V V(OUT0) - V(OUT15) -0.3 to 18 V 2 kV 500 V VO Output voltage range (2) ESD rating Tstg (1) (2) HBM (JEDEC JESD22-A114, Human Body Model) CDM (JEDEC JESD22-C101, Charged Device Model) -40 to 150 °C Continuous total power dissipation at (or below) TA = 25°C 3.9 W Power dissipation rating at (or above) TA = 25°C 31.4 mW/°C Storage temperature range Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS DC Characteristics MIN MAX UNIT Supply voltage VO Voltage applied to output, (Out0 - Out15) VIH High-level input voltage VIL Low-level input voltage IOH High-level output current VCC = 5 V at SOUT -1 mA IOL Low-level output current VCC = 5 V at SOUT, XDOWN 1 mA IOLC Constant output current OUT0 to OUT15 80 mA 85 °C TA (1) 2 Operating free-air temperature 3 NOM VCC range (1) Please contact TI sales for slightly extended temperature range. 5.5 V 17 V 0.8 VCC VCC V GND 0.2 VCC -20 V TLC5923 www.ti.com SLVS550 – DECEMBER 2004 AC Characteristics VCC = 3 V to 5.5 V, TA = -20°C to 85°C (unless otherwise noted) MIN TYP MAX UNIT 30 MHz fSCLK Clock frequency SCLK twh0/twl0 CLK pulse duration SCLK=H/L 16 ns twh1 XLAT pulse duration XLAT=H 20 ns tsu0 SIN - SCLK↑ 10 ns tsu1 SCLK↑-XLAT↓ 10 ns Setup time tsu2 MODE↑↓-SCLK↑ 10 ns tsu3 MODE↑↓-XLAT↓ 10 ns th0 SCLK↑-SIN 10 ns XLAT↓-SCLK↑ 10 ns SCLK↑-MODE↑↓ 10 ns XLAT↓-MODE↑↓ 10 ns th1 Hold time th2 th3 ELECTRICAL CHARACTERISTICS VCC = 3 V to 5.5 V, TA = - 20°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH High-level output voltage IOH = - 1 mA, SOUT VCC -0.5 VOL Low-level output voltage IOL = 1 mA, SOUT Input current VI = VCC or GND, BLANK, XLAT, SCLK, SIN, MODE II ICC Supply current TYP MAX UNIT V -1 0.5 V 1 µA No data transfer, All output OFF, VO = 1 V, R(IREF) = 10 kΩ 6 No data transfer, All output OFF, VO = 1 V, R(IREF) = 1.3 kΩ 12 Data transfer 30 MHz, All output ON, VO = 1 V, R(IREF) = 1.3 kΩ 25 mA Data transfer 30 MHz, All output ON, VO = 1 V, R(IREF) = 600 kΩ 36 65 (1) 80 Constant output current All output ON, VO = 1 V, R(IREF) = 600 Ω 90 mA Leakage output current All output OFF, VO = 15 V, R(IREF) = 600 Ω , OUT0 to OUT15 0.1 µA ILO1 VXERR = 5.5 V, No TEF and LOD 10 µA ∆IOLC0 Constant current error All output ON, VO = 1 V, R(IREF) = 600 Ω, OUT0 to OUT15 ±1 ± 4 % ∆IOLC1 Constant current error device to device, averaged current from OUT0 to OUT15, R(IREF) = 600 Ω ±4 ± 8.5 % ∆IOLC2 Power supply rejection ratio All output ON, VO = 1 V, R(IREF) = 600 Ω, OUT0 to OUT15 ±1 ±4 %/V ∆IOLC3 Load regulation All output ON, VO = 1 V to 3 V, R(IREF) = 600 Ω, OUT0 to OUT15 ±2 ±6 %/V T(TEF) Thermal error flag threshold Junction temperature, rising temperature (2) 160 180 °C V(LOD) LED open detection threshold 0.3 0.4 V V(IREF) Reference voltage output 1.24 1.28 V IOLC ILO0 (1) (2) R(IREF) = 600 Ω 70 150 1.20 Measured at device start-up temperature. Once the IC is operating (self heating), lower ICC values will be seen. See Figure 15. Not tested. Specified by design. 3 TLC5923 www.ti.com SLVS550 – DECEMBER 2004 SWITCHING CHARACTERISTICS PARAMETER TEST CONDITIONS tr0 SOUT(see Rise time tr1 tf0 tf1 10 (1)) SCLK↑ - SOUT↑↓ (see 10 (3)) tpd1 MODE↑↓ - SOUT↑↓ (see tpd2 BLANK↓ - OUT0↑↓ (see Propagation delay time MAX 30 30 60 60 tpd4 OUTx↑↓-XERR↑↓ (see (5)) 1000 tpd5 XLAT↑-IOUT(dot-correction) (see (6)) (1) (2) (3) (4) (5) (6) Output delay time OUTn↑↓-OUT(n+1)↑↓ (see (4)) ns 300 (4)) (4)) td ns 300 (3)) XLAT↑ - OUT0↑↓ (see tpd3 UNIT 16 OUTx, VCC = 5 V, TA = 60°C, DCx = 7F (see (2)) tpd0 TYP 16 OUTx, VCC = 5 V, TA = 60°C, DCx = 7F (see (2) ) SOUT (see Fall time MIN (1)) ns 1000 14 22 30 ns See Figure 5. Defined as from 10% to 90% See Figure 6. Defined as from 10% to 90% See Figure 5, Figure 13 See Figure 6 and Figure 13 See Figure 6, Figure 7, and Figure 13 See Figure 6 DAP PACKAGE (TOP VIEW) GND BLANK XLAT SCLK SIN PGND OUT0 OUT1 PGND OUT2 OUT3 OUT4 OUT5 PGND OUT6 OUT7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC IREF MODE XERR SOUT PGND OUT15 OUT14 PGND OUT13 OUT12 OUT11 OUT10 PGND OUT9 OUT8 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. BLANK 2 GND 1 IREF 31 I/O MODE 30 I Mode select. When MODE=L, SIN, SOUT, SCLK, XLAT are connected to ON/OFF control logic. When MODE=H, SIN, SOUT, SCLK, XLAT are connected to dot-correction logic. OUT0 7 O Constant current output 4 2 Blank (Light OFF). When BLANK=H, All OUTx outputs are forced OFF. When BLANK=L, ON/OFF of OUTx outputs are controlled by input data. Ground Reference current terminal TLC5923 www.ti.com SLVS550 – DECEMBER 2004 Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION OUT1 8 O Constant current output OUT2 10 O Constant current output OUT3 11 O Constant current output OUT4 12 O Constant current output OUT5 13 O Constant current output OUT6 15 O Constant current output OUT7 16 O Constant current output OUT8 17 O Constant current output OUT9 18 O Constant current output OUT10 20 O Constant current output OUT11 21 O Constant current output OUT12 22 O Constant current output OUT13 23 O Constant current output OUT14 25 O Constant current output OUT15 26 O Constant current output PGND 6, 14, 19, 24, 27 SCLK 4 Power ground I Data shift clock. Note that the internal connections are switched by MODE (pin #30). At SCLK↑, the shift-registers selected by MODE shift the data. SIN 5 I Data input of serial I/F SOUT 28 O Data output of serial I/F VCC 32 XERR 29 O Error output. XERR is open drain terminal. XERR gets L when LOD or TEF detected. XLAT 3 I Data latch. Note that the internal connections are switched by MODE (pin #30). At XLAT↑, the latches selected by MODE get new data. Power supply voltage PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS (Note: Resistor values are equivalent resistance and not tested). VCC INPUT 400 GND Figure 2. Input Equivalent Circuit (BLANK, XLAT, SCLK, SIN, MODE) 10 SOUT GND Figure 3. Output Equivalent Circuit 5 TLC5923 www.ti.com SLVS550 – DECEMBER 2004 PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS (continued) 20 XERR GND Figure 4. Output Equivalent Circuit (XERR) PARAMETER MEASUREMENT INFORMATION SOUT 15 pF Figure 5. Test Circuit for tr0, tf0, td0, td1 51 Ω OUTn 15 pF Figure 6. Test Circuit for tr1, tf1, tpd2, tpd3, tpd5, tpd6 470 kΩ XDOWN Figure 7. Test Circuit for tpd4 6 TLC5923 www.ti.com SLVS550 – DECEMBER 2004 PRINCIPLES OF OPERATION Setting Maximum Channel Current The maximum output current per channel is set by a single external resistor, R(IREF), which is placed between IREF and GND. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of 1.24V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of 40. The maximum output current can be calculated by Equation 1: V I IREF 40 MAX R IREF (1) where: VIREF = 1.24V typ. RIREF = User selected external resistor (RIREF should not be smaller than 600 Ω) Figure 8 shows the maximum output current, IO(LC), versus R(IREF) . In Figure 8, R(IREF) is the value of the resistor between IREF terminal to ground, and IO(LC) is the constant output current of OUT0,.....OUT15. 100 k 48.8 k 10 k 9.76 k 4.88 k 2.44 k 1.63 k 1.22 k 976 1k IREF − Reference Resistor − Ω VOutn = 1 V DC = 127 813 R 697 100 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 IOLC − Output Current − mA Figure 8. Reference Resistor vs Output Current Setting Dot-Correction The TLC5923 has the capability to fine adjust the current of each channel, OUT0 to OUT15 independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LED connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 7-bit word. The channel output can be adjusted in 128 steps from 0% to 100% of the maximum output current IMAX. Equation 2 determines the output current for each OUTn: I DCn I MAX Outn 127 (2) where: IMax = the maximum programmable current of each output DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127) n = 0, 1, 2 ... 15 7 TLC5923 www.ti.com SLVS550 – DECEMBER 2004 PRINCIPLES OF OPERATION (continued) Dot correction data are entered for all channels at the same time. The complete dot correction data format consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after another. All data is clocked in with MSB first. Figure 9 shows the DC data format. LSB MSB 0 6 7 104 105 111 DC 0.0 DC 0.6 DC 1.0 DC 14.6 DC 15.0 DC 15.6 DC OUT0 DC OUT15 DC OUT2 − DC OUT14 Figure 9. DC Data Format To input data into dot correction register, MODE must be set to high. The internal input shift register is then set to 112 bit width. After all serial data is clocked in, a rising edge of XLAT latch the data to the dot correction register (Figure 13). Output Enable All OUTn channels of TLC5923 can switched off with one signal. When BLANK signal is set to high, all OUTn are disabled, regardless of On/Off status of each OUTn. When BLANK is the to low, all OUTn work under normal conditions. Table 1. BLANK Signal Truth Table BLANK OUT0 - OUT15 LOW Normal condition HIGH Disabled Setting Channel On/Off Status All OUTn channels of TLC5923 can be switched on or off independently. Each of the channels can be programmed with a 1-bit word. On/Off data are entered for all channels at the same time. The complete On/Off data format consists of 16 x 1-bit words, which form a 16-bit wide data packet. The channel data is put one after another. All data is clocked in with MSB first. Figure 10 shows the On/Off data format. LSB 0 On/Off OUT0 MSB 15 On/Off OUT1 On/Off OUT2 On/Off OUT3 On/Off OUT4 On/Off OUT5 On/Off OUT6 On/Off OUT7 On/Off OUT8 On/Off OUT9 On/Off OUT10 On/Off OUT11 On/Off OUT12 On/Off OUT13 On/Off OUT14 On/Off OUT15 On/Off Data Figure 10. On/Off Data To input On/Off data into On/Off register MODE must be set to low. The internal input shift register is then set to 16 bit width. After all serial data is clocked in, a rising edge of XLAT during BLANK = high is used to latch data into the On/Off register. Figure 13 shows the On/Off data input timing chart. With the falling edge of XLAT signal all data in input shift register is replaced with LOD channel data. These data is clocked out to SOUT when new On/Off data is clocked in. Delay Between Outputs The TLC5923 has graduated delay circuits between outputs. These delay circuits can be found in the constant current block of the device (see Figure 1). The fixed delay time is 20 ns (typical), OUT0 has no delay, OUT1 has 20 ns delay, OUT2 has 40 ns delay, etc. This delay prevents large inrush currents, which reduce power supply bypass capacitor requirements when the outputs turn on. 8 TLC5923 www.ti.com SLVS550 – DECEMBER 2004 Serial Interface Data Transfer Rate The TLC5923 includes a flexible serial interface, which can be connected to microcontroller or digital signal processor. Only 3 pins are in required to input data into the device. The rising edge of SCLK signal shifts the data from SIN pin to internal shift register. After all data is clocked in, a rising edge of XLAT latches the serial data to the internal registers. All data is clocked in with MSB first. Multiple TLC5923 devices can be cascaded by connecting SOUT pin of one device with SIN pin of following device. The SOUT pin can also be connected to controller to receive LOD information from TLC5923. VCC V(LED) V(LED) V(LED) V(LED) 100 k OUT0 Controller OUT15 SIN SIN OUT0 SOUT XERR XERR SCLK SCLK XLAT XLAT MODE MODE BLANK BLANK VCC OUT15 SIN SOUT XERR VCC SCLK 100 nF TLC5923 IREF SOUT 100 nF XLAT MODE TLC5923 BLANK IC 0 IREF IC n 5 Figure 11. Cascading Devices Figure 11 shows a example application with n cascaded TLC5923 devices connected to a controller. The maximum number of cascaded TLC5923 devices depends on application system and data transfer rate. Equation 3 calculates the minimum data input frequency needed. f_(SCLK) 112 f_(update) n (3) where: f_(SCLK): The minimum data input frequency for SCLK and SIN. f_(update): The update rate of the whole cascaded system. n: The number of cascaded TLC5923 devices. Operating Modes The TLC5923 has different operating modes depending on MODE signal. Table 2 shows the available operating modes. Table 2. TLC5923 Operating Modes Truth Table MODE SIGNAL INPUT SHIFT REGISTER MODE LOW 16 bit On/Off Mode HIGH 112 bit Dot Correction Data Input Mode 9 TLC5923 www.ti.com SLVS550 – DECEMBER 2004 Error Information Output The open-drain output XERR is used to report both of the TLC5923 error flags, TEF and LOD. During normal operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to VCC through a external pullup resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error. To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH. Table 3. XERR Truth Table ERROR CONDITION ERROR INFORMATION SIGNALS TEMPERATURE OUNTn VOLTAGE TEF LOD BLANK XERR TJ < T(TEF) Don't Care L X H H TJ > T(TEF) Don't Care H X TJ < T(TEF) OUTn > V(LOD) L L OUTn < V(LOD) L H L OUTn > V(LOD) H L L OUTn < V(LOD) H H L TJ > T(TEF) L L H TEF: Thermal Error Flag The TLC5923 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If the junction temperature exceeds the threshold temperature T(TEF) (160°C typical), the TEF circuit trips and pulls XERR to ground. LOD: LED Open Detection The TLC5923 provides an LED open-detection circuit (LOD). This circuit reports an error if any one of the 16 LEDs is open or disconnected from the circuit. The LOD circuit trips when the following two conditions are met simultaneously: 1. BLANK is set to LOW 2. When the voltage at OUTn is less than V(LOD) (0.3 V typ.) (Note: the voltage at each OUTn is sampled 1 µs after being turned on). The LOD circuit also pulls XERR to GND when tripped. The LOD status of each channel can also be read out from the TLC5923 SOUT pin. When MODE is low and On/Off data is latched with rising edge of XLAT, LOD data is written to the input shift register with the falling edge of XLAT. These LOD data is clocked out to SOUT when new On/Off data is clocked in. These allow to control the LOD status of each OUTn channel. Figure 12 shows the LOD data format. LSB 0 LOD OUT0 MSB 15 LOD OUT1 LOD OUT2 LOD OUT3 LOD OUT4 LOD OUT5 LOD OUT6 LOD OUT7 LOD OUT8 LOD OUT9 LOD Data Figure 12. LOD Data 10 LOD OUT10 LOD OUT11 LOD OUT12 LOD OUT13 LOD OUT14 LOD OUT15 t h3 tpd2 On/Off MSB On/Off LSB t pd3 t wh1 td t pd2 DC MSB t pd1 t wl0 t wh0 DC MSB t su3 DC LSB f CLK DC MSB t su0 DC LSB DC Mode Data Input Cycle h1 t h2 DC LSB t su1 t h0 t pd0 t pd5 t DC MSB t h3 DC Mode Data Input Cycle DC MSB DC LSB t pd5 On/Off MSB t pd1 t su2 On/Off MSB tsu3 On/Off LSB On/Off MSB On/Off LSB On/Off Mode Data Input Cycle On/Off MSB−1 t pd4 On/Off MSB On/Off MSB On/Off Mode Data Input Cycle www.ti.com OUT1 (current) OUT0 (current) XERR BLANK SOUT SCLK SIN XLAT MODE On/Off Mode Data Input Cycle TLC5923 SLVS550 – DECEMBER 2004 Figure 13. Timing Chart Example for ON/OFF Setting to Dot-Correction 11 TLC5923 www.ti.com SLVS550 – DECEMBER 2004 Power Rating - Free-Air Temperature Figure 14 shows total power dissipation. Figure 15 shows supply current versus free-air temperature. 3.9 3.2 1.48 2 −20 0 25 85 TA − Free-Air Temperature − °C Figure 14. Supply Current(A) vs Free-Air Temperature 70 ICC − Supply Current − mA 60 50 40 30 20 10 0 −50 −30 −10 10 30 50 70 90 110 130 150 TA − Free-Air Temperature − °C A. 12 Data Transfer = 30 MHz / All Outputs, ON/VO = 1 V / RIREF = 600 Ω / AVDD = 5 V Figure 15. VO − Output Voltage − V PD − Power Dissipation − W Power Dissipation vs Temperature PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5923DAP ACTIVE HTSSOP DAP 32 46 TBD CU NIPDAU Level-2-220C-1 YEAR TLC5923DAPR ACTIVE HTSSOP DAP 32 2000 TBD CU NIPDAU Level-2-220C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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