TPIC9201N www.ti.com SLIS115 – JULY 2005 MICROCONTROLLER POWER SUPPLY AND MULTIPLE LOW SIDE DRIVER IC FEATURES • • • • • Eight Low-Side Drivers With Internal Clamp for Inductive Loads and Current Limiting for Self Protection – Seven Outputs are Rated at 150 mA and Controlled Through the Serial Interface – One Output Rated at 150 mA and is Controlled Through Serial and/or Parallel Input 5-V ±5% Regulated Power Supply With 200-mA Load Capability at VIN Max of 18 V Internal Voltage Supervisory for the Regulated Output Serial Communications for Control of Eight, Low Side Drivers Enable/Disable Input for Out1 5 V or 3.3 V, I/O Tolerant for Interface to • • • • Microcontroller Programmable Power On Reset Delay Before RST is Asserted High, Once the 5 V is Within Specified Range (Typically 6 ms) Programmable De-glitch Timer Before nRST is Asserted Low (typically 40 µs) Zero Voltage Detection Signal With Built in Filter of 20 µs Thermal Shutdown for Self Protection APPLICATIONS • • • AC Unit Washing Machines Refrigeration Systems DESCRIPTION The ac-unit power supply with low side drive output provides regulated 5-V output to power the system microcontroller and drive up to eight inductive and/or resistive loads. The ac zero detect circuitry is monitoring the cross-over voltage of the mains ac supply. The resultant signal is a low frequency clock output on the ZVS terminal based on the ac line cycle. This information allows the microcontroller to reduce inrush current by powering loads on the ac-line peak voltage. A serial communications interface controls the eight low side outputs; each output has an internal snubber circuit to absorb the energy in the inductor at turn OFF. Alternatively, the system can place a fly-back diode to VIN to help recirculate the energy in an inductive load at turn OFF. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2005, Texas Instruments Incorporated PRODUCT PREVIEW • TPIC9201N www.ti.com SLIS115 – JULY 2005 PIN OUT CONFIGURATION PIN NO. PRODUCT PREVIEW (1) 2 PIN LABEL I/O DESCRIPTION 1 ZVS O Zero Voltage Synchronization 2 Out1 O Low side Output #1 3 Out2 O Low side Output #2 4 Out3 O Low side Output #3 5 Out4 O Low side Output #4 6 Out5 O Low side Output #5 7 Out6 O Low side Output #6 8 Out7 O Low side Output #7 9 Out8 O Low side Output #8 10 (1) GND I IC Ground 11 (1) GND I IC Ground 12 EN1 I Enable/disable for Out1 13 Rdelay O Power up reset delay 14 RST O Power On Reset output (open drain, active low) 15 MOSI I Sesrial data input 16 NCS I Chip select 17 SCLK I Serial clock for data synchronization 18 5Vout O Regulated output 19 VIN I Unregulated Input voltage source 20 SYN I AC zero detect input Terminals 10 and 11 are internally fused in the lead frame for the 20-pin PDIP package. TPIC9201N www.ti.com SLIS115 – JULY 2005 IC FUNCTIONAL BLOCK Out1 EN1 Out1 Enables Out1 Enable Out1 @ 150 mA Gate Control for Outputs 1 Through 8 Out2 Out2 Out2 @150 mA Out3 NCS Out3 @150 mA Out3 Out4 NCS Out4 @150 mA Parallel Register Out4 Out5 Out5 @150 mA Out5 Out6 Out6 @150 mA SCLK Out7 @150 mA Out7 Out8 MOSI Out8 @150 mA MOSI R 10 V PRODUCT PREVIEW SCLK Out6 Out7 Serial Register Out8 VIN 7V-18V PMOS Optional, dependent on heat management implementation 5Vout Gate Drive and Control Bandgap Ref Comp GND 5V – + GND Vref GND GND Vref Voltage Supervisor RST 5 kÙ Iconst Rdelay Rdelay 20 ìs filter SYN 25 kÙ S 500 kÙ Q Syn i/p 10 kÙ 100 kÙ ZVS ZVS R B0036-01 The value R is chosen based on maximum 5-V out load and minimum operating voltage desired. The Zener on the VIN line helps limit the excess power dissipation within the IC when the operating voltage exceeds 10 V (starts conducting). For 12-V to 7-V operating input, the resistor and Zener are NOT required. 3 TPIC9201N www.ti.com SLIS115 – JULY 2005 DESCRIPTION OF THE FUNCTION The 5-V regulator is powered from the VIN line; the regulated output will be within 5 V ±5% over the operating conditions. The power on reset line (open drain) remains low until the regulator exceeds the set threshold and the timer value set by the capacitor on reset delay line expires. If both of these conditions are satisfied the POR line is asserted high. This signifies to the microcontroller that serial communications can be initiated to the IC. The serial communications will be an 8-bit format; with data transfer synchronized using a serial clock from the microcontroller. A single register controls ALL the outputs (1-bit per output). The default value will be zero (OFF). If an output requires PWM function the register will have to be update at a rate faster than the desired PWM frequency. Out1 can be controlled by serial input bit OR the parallel input signal from EN1. The terminal will have an internal pulldown for disabling the output (Out1) in the event there is an open on this terminal. The SYN input translates the image of the mains voltage through the secondary of the transformer. The SYN input has a resistor to protect from high currents into the IC. The zero voltage synchronization output translates the ac-line cycle frequency into a low frequency clock, which can be used for a timing reference and help power loads on the ac-line peak voltage (to reduce inrush currents). If reset is asserted ALL outputs are turned OFF internally and the input register is reset to ALL zeroes. The microcontroller will have to write to the register to turn the outputs ON again. ABSOLUTE MAXIMUM RATINGS (1) (2) PRODUCT PREVIEW VIN Unregulated input (3) (4) 24 V SYN Unregulated input (3) (4) 24 V EN1, MOSI, SCLK, and NCS Logic inputs (3) (4) 7V RST and Rdelay See OUT(1:8) Low side outputs θJC Thermal impedance junction-to-case (5) 67°C/W θJA Thermal impedance junction-to-ambient (5) 137°C/W PD Continuous power dissipation 0.912 W ESD Electrostatic discharge (6) TOP Operating ambient temperature range –40°C to 85°C TS Storage temperature range –65°C to 125°C TLEAD Lead temperature (Soldering, 10 sec) (1) (2) (3) (4) (5) (6) (3) and (4) 7V 20 V 2 kV 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute negative voltage on these pins not to go below -1 V All voltage values are with respect to GND. Absolute negative voltage on these pins not to go below -0.5 V The thermal data is based on using 2 oz copper trace with at least four square inches of copper footprint for heat dissipation. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. DISSIPATION RATINGS PACKAGE TC ≤ 25°C POWER RATING DERATING FACTOR ABOVE TC = 25°C TC = 85°C POWER RATING N 912.4 mW 7.3 mW/°C 474 mW RECOMMENDED OPERATING CONDITIONS MIN VIN SYN EN1, RST, and Rdelay MOSI, SCLK, and NCS TOP 4 Unregulated input Logic level (I/O) Operating ambient temperature range NOM MAX 7 18 0 15 0 5.25 0 5.25 –40 85 UNIT V V °C TPIC9201N www.ti.com SLIS115 – JULY 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 7 V to 18 V (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT VIN Input voltage IVIN Input supply current (1)7 18 Enable = ON, Out1–8 = OFF 3 Enable = ON, Out1–8 = ON 5 V mA LOGIC INPUT (MOSI, NCS, SCLK, and ENS) VIL Logic input low level IIL = 100 mA VIH Logic input high level IIL = 100 mA VOL Logic level output IOL = 1.6 mA VOH Logic level output 5-kΩ pullup to VCC VH Disabling reset threshold 5-V reg ramps up VL Enabling reset threshold 5-V ramps down VHYS Threshold hysteresis 0.8 V 2.4 RESET (RST) 0.4 V VCC– 0.8 V 4.25 4.5 V 3.3 3.75 V 0.3 0.5 V 28 µA 6 ms 45 µs IOUT TDW Reset delay timer C = 47 nF TUP Reset capacitor to low level C = 47 nF 1 PRODUCT PREVIEW RESET DELAY (Rdelay) OUTPUT (OUT1 through OUT8) VOL Output ON IOUT(x) = 150 mA IOH Output leakage VOH = VIN ILIMIT Output current limit OUT(X) = ON and shorted to VIN with low impedance 350 0.7 V 2 µA mA REGULATOR OUTPUT (5Vout) 5Vout Output supply I5Vout = 5 mA to 200 mA, VIN = 7 V to 18 V C5Vout = 1 µF 4.75 I5Vout limit Output short circuit current 5V=0V 200 5 5.25 V mA THERMAL SHUTDOWN ISD Thermal shutdown tHYS Hysteresis 170 °C 20 °C ZERO VOLTAGE SYNCHRONIZATION (ZVS) VSYNTH Transition threshold ISYN Input activating current RZV = 10 kΩ and VSYN = 24 V tD Transition filtering time VTF = VCC rising and falling step (1) 0.4 0.6 10 30 0.9 V 2 mA 70 µs There will be external high frequency noise suppression capacitors and filter capacitor on the VIN. OUTPUT CONTROL REGISTER MSB LSB IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 0 0 0 0 0 0 0 0 INX = 0; Output OFF INX = 1; Output ON 5 TPIC9201N www.ti.com SLIS115 – JULY 2005 To operate the output in a PWM mode the output control register has to be updated at a rate 2X the desired PWM frequency of the output. Maximum PWM frequency is 5 kHz. The register is updated every 100 ms. SERIAL COMMUNICATIONS INTERFACE The serial communications will be an 8-bit format; with data transfer synchronized using a serial clock from the microcontroller. A single register controls all the outputs. The signal gives the instruction to control the output of TPIC9201N. Signal NCS enables the SCLK and MOSI data when it is low. After NCS is set to low for T1, synchronization clock and data begin to transmit and after the 8-bit data has been transmitted, NCS will be set to high again to disable SCLK and MOSI and transfer the serial data to the control register. SCLK must be held low when NCS is in the high state. T2 T3 T8 T1 T4 T5 T1 PRODUCT PREVIEW NCS SCLK 1 2 3 4 5 6 7 LSB MSB MOSI XXX IN8 8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 T6 T7 T0054-01 6 TPIC9201N www.ti.com SLIS115 – JULY 2005 TIMING REQUIREMENTS TA = –40°C to 85°C, VIN = 7 V to 18 V (unless otherwise stated) PARAMETER MIN TYP 4 MAX UNIT FSPI SPI frequency T1 Time from NCS falling edge to CLK rising edge 10 mHz ns T2 Time from NCS falling edge to CLK falling edge 80 ns T3 Time for CLK to go high 60 ns T4 Time for CLK to go low 60 ns T5 Time from last CLK falling edge to NCS rising edge 80 ns T6 SDI setup time before CLK edge 10 ns T7 SDI hold time after CLK edge 10 ns T8 Time between two words for transmitting 170 ns THe RDELAY output provides a constant current source to charge an external capacitor to approximately 6.5 V. The external capacitor is selected to provide a delay time based on the current equation for a capacitor, I = C dv/dt and a 28 µA typical output current. Therefore, the user should select a 47-nF capacitor to provide a 6 ms delay at 3.55 V. I = C dv/dt 28 µA = C × (3.55 V / 6 ms) C = 47 nF 7 PRODUCT PREVIEW RDELAY TPIC9201N www.ti.com SLIS115 – JULY 2005 APPLICATION INFORMATION APPLICATIONS 1. Buzzer Driver 2. Relay Driver 3. Relay Driver 4. Relay Driver 5. Relay Driver 6. Fan Driver 7. Fan Driver 8. Fan Driver MOSI SCLK MCU/DSP NCS 8 Outputs ZVS TPIC9201N 20-Pin PDIP RST 5Vout ±5% @ 150 mA SYN, (AC Zero-Cross Detect Input) EN1 Reset Delay PRODUCT PREVIEW DC Input 7 V to 18 V GND (2´) B0037-01 WASHING MACHINE APPLICATION Display (LED/LCD/VFD) Key Pad AC Water Supply Valve Filters Water Outlet Softener Supply Volume Sensor M Power Switch Controller Water Level Sensor Driver Optical Sensor SYN Vout Regulator + ~ SYN Zero-Cross Detection ~ POR/SYS - Temperature Sensor (Optional) RST Cover Switch Appliance IC B0038-01 8 PACKAGE OPTION ADDENDUM www.ti.com 29-Jul-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPIC9201N PREVIEW PDIP N Pins Package Eco Plan (2) Qty 20 20 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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