TLC5940 PWP www.ti.com RHB NT SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL FEATURES APPLICATIONS • • • • • • • • • • • • • • • 16 Channels 12 bit (4096 Steps) Grayscale PWM Control Dot Correction – 6 bit (64 Steps) – Storable in Integrated EEPROM Drive Capability (Constant Current Sink) – 0 mA to 60 mA (VCC < 3.6 V) – 0 mA to 120 mA (VCC > 3.6 V) LED Power Supply Voltage up to 17 V VCC = 3 V to 5.5 V Serial Data Interface, SPI comp. Controlled In-Rush Current 30-MHz Data Transfer Rate CMOS Level I/O Error Information – LOD: LED Open Detection – TEF: Thermal Error Flag VCC GND SCLK SIN Max. OUTn Current VREF =1.24 V VPRG 1 DESCRIPTION The TLC5940 is a 16-channel constant-current sink LED driver. Each channel has an individually adjustable 4096-step grayscale PWM brightness control and a 64-step constant-current sink (dot correction). The dot correction adjusts the brightness variations between LED channels and other LED drivers. The dot correction data is stored in an integrated EEPROM. Both grayscale control and dot correction are accessible via a serial interface. A single external resistor sets the maximum current value of all 16 channels. The TLC5940 features two error information circuits. The LED open detection (LOD) indicates a broken or disconnected LED at an output terminal. The thermal error flag (TEF) indicates an overtemperature condition. XLAT VPRG IREF DCPRG CNT 1 0 GS Register 0 DCPRG 1 DC Register 0 GS Counter CNT 5 LED Open Detection CNT 192 12 95 12−Bit Grayscale PWM Control GS Register 23 DCPRG 1 96 1 0 OUT0 Delay x0 VPRG 96 192 Constant Current Driver 6−Bit Dot Correction 0 0 DC EEPROM 5 Input Shift Register Status 0 Information: LOD, TED, DC DATA 191 12−Bit Grayscale PWM Control 11 0 0 GSCLK BLANK Monocolor, Multicolor, Fullcolor LED Displays LED Signboards Display Backlighting General, High-Current LED Drive 96 6−Bit Dot Correction DC Register 11 0 6 Constant Current Driver OUT1 Delay x1 VPRG 6 DC EEPROM11 96 LED Open Detection (LOD) Temperature Error Flag (TEF) LED Open Detection VPRG CNT Blank 1 0 Input Shift Register 12−Bit Grayscale PWM Control GS Register 180 191 DCPRG 1 XERR 90 191 90 SOUT DC Register 95 0 DC EEPROM 95 Constant Current Driver OUT15 Delay x15 6−Bit Dot Correction LED Open Detection VPRG Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA PACKAGE (1) PART NUMBER -40°C to 85°C 28-pin HTSSOP PowerPAD™ TLC5940PWP -40°C to 85°C 32-pin 5 mm x 5 mm QFN TLC5940RHB -40°C to 85°C 28-pin PDIP TLC5940NT For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS. over operating free-air temperature range (unless otherwise noted) (1) UNIT VI Input voltage range (2) IO Output current (dc) VI Input voltage range VO Output voltage range EEPROM program range VCC 130 mA V(BLANK), V(DCPRG), V(SCLK), V(XLAT) –0.3 V to VCC +0.3 V V(SOUT), V(XERR) –0.3 V to VCC +0.3 V V(OUT0) to V(OUT15) –0.3 V to 18 V V(PRG) –0.3 V to 24 V EEPROM write cycles 50 HBM (JEDEC JESD22-A114, Human Body Model) ESD rating CBM (JEDEC JESD22-C101, Charged Device Model) Tstg Storage temperature range TA Operating ambient temperature range Package thermal (1) (2) (3) (4) 2 impedance (3) –0.3 V to 6 V 2 kV 500 V –55°C to 150°C –40°C to 85°C HTSSOP (PWP) (4) 31.58°C/W QFN (RHB) 35.9°C/W PDIP (NP) 48°C/W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The package thermal impedance is calculated in accordance with JESD 51-7. With PowerPAD soldered on PCB with 2 oz. trace of copper. See SLMA002 for further information. TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT DC CHARACTERISTICS VCC Supply Voltage VO Voltage applied to output (OUT0–OUT15) 3 VIH High-level input voltage VIL Low-level input voltage IOH High-level output current VCC = 5 V at SOUT IOL Low-level output current VCC = 5 V at SOUT, XERR 5.5 V 17 V 0.8 VCC VCC V GND 0.2 VCC V –1 mA 1 mA OUT0 to OUT15, VCC < 3.6 V 60 mA OUT0 to OUT15, VCC > 3.6 V 120 mA 23 V 85 °C 30 MHz 30 MHz IOLC Constant output current V(PRG) EEPROM program voltage TA Operating free-air temperature range 20 -40 22 AC CHARACTERISTICS VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted) f(SCLK) Data shift clock frequency SCLK f(GSCLK) Grayscale clock frequency GSCLK twh0/twl0 SCLK pulse duration SCLK = H/L (see Figure 8) 16 ns twh1/twl1 GSCLK pulse duration GSCLK = H/L (see Figure 13) 16 ns twh2 XLAT pulse duration XLAT = H (see Figure 11) 20 ns twh3 BLANK pulse duration BLANK = H (see Figure 13) 20 ns tsu0 SIN–SCLK (see Figure 11) 10 ns tsu1 SCLK–XLAT (see Figure 11) 10 ns VPRG–SCLK (see Figure 6) 10 ns VPRG–XLAT (see Figure 6) 10 ns tsu4 BLANK–GSCLK (see Figure 13) 10 ns tsu5 VPRG–DCPRG 1 ms th0 SCLK–SIN (see Figure 11) 10 ns th1 XLA–SCLK (see Figure 11) 10 ns SCLK–VPRG (see Figure 6) 10 ns XLAT–VPRG (see Figure 6) 10 ns th4 BLANK–GSCLK (see Figure 13) 10 ns th5 DCPRG–VPRG 1 ms tprog Programming time for EEPROM 20 ms tsu2 tsu3 th2 th3 Setup time Hold Time DISSIPATION RATINGS PACKAGE POWER RATING TA < 25°C DERATING FACTOR ABOVE TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C 28-pin HTSSOP with PowerPAD™ (1)soldered 3958 mW 31.67 mW/°C 2533 mW 2058 mW 28-pin HTSSOP with PowerPAD™ unsoldered 2026 mW 16.21 mW/°C 1296 mW 1053 mW 32-pin QFN (1) 3482 mW 27.86 mW/°C 2228 mW 1811 mW 28-pin PDIP 2456 mW 19.65 mW/°C 1572 mW 1277 mW (1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information. 3 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = -1 mA, SOUT VOL Low-level output voltage IOL = 1 mA, SOUT II Input current MIN TYP Supply current VI = VCC or GND; BLANK, DCPRG, GSCLK, SCLK, SIN, XLAT –1 1 VI = GND; VPRG –1 1 µA 50 4 10 No data transfer, all output OFF, VO = 1 V, R(IREF) = 10 kΩ 0.9 6 No data transfer, all output OFF, VO = 1 V, R(IREF) = 1.3 kΩ 5.2 12 Data transfer 30 MHz, all output ON, VO = 1 V, R(IREF) = 1.3 kΩ 16 25 Data transfer 30 MHz, all output ON, VO = 1 V, R(IREF) = 640 Ω 30 60 61 69 mA 0.1 µA Constant output current All output ON, VO = 1 V, R(IREF) = 640 Ω Ilkg Leakage output current All output OFF, VO = 15 V, R(IREF) = 640 Ω, OUT0 to OUT15 Constant current error V VI = 22 V; VPRG; DCPRG = VCC IO(LC) ∆IO(LC0) UNIT V 0.5 VI = VCC; VPRG ICC MAX VCC– 0.5 mA mA 54 All output ON, VO = 1 V, R(IREF) = 640 Ω, OUT0 to OUT15, –20°C to 85°C ±1 ±4 All output ON, VO = 1 V, R(IREF) = 640 Ω, OUT0 to OUT15 ±1 ±8 All output ON, VO = 1 V, R(IREF) = 320 Ω, OUT0 to OUT15, –20°C to 85°C ±1 ±6 All output ON, VO = 1 V, R(IREF) = 320 Ω, VCC = 4.5 V to 5.5 V, OUT0 to OUT15 ±1 ±8 % ∆IO(LC1) Constant current error Device to device, Averaged current from OUT0 to OUT15, R(IREF) = 1920 Ω (20 mA) –2 +0.4 ±4 % ∆IO(LC2) Constant current error Device to device, Averaged current from OUT0 to OUT15, R(IREF) = 480 Ω (80 mA) –2.7 +2 ±4 % Power supply rejection ratio, PSRR All output ON, VO = 1 V, R(IREF) = 640 Ω OUT0 to OUT15 ±1 ±4 %/V ∆IO(LC3) All output ON, VO = 1 V, R(IREF) = 320 Ω , OUT0 to OUT15 ±1 ±6 %/V All output ON, VO = 1 V to 3 V, R(IREF) = 640 Ω, OUT0 to OUT15 ±2 ±6 %/V All output ON, VO = 1 V to 3 V, R(IREF) = 320 Ω, OUT0 to OUT15 ±2 ±8 %/V ∆IO(LC4) Load regulation T(TEF) Thermal error flag threshold V(LED) LED open detection threshold V(IREF) Reference voltage output (1) 4 Not tested. Specified by design Junction temperature (1) RI(REF) = 640 Ω 170 °C 0.3 0.4 V 1.24 1.28 V 150 1.20 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 SWITCHING CHARACTERISTICS VCC = 3 V to 5.5 V, TA = -40°C to 85°C (unless otherwise noted) PARAMETER tr0 tr1 tf0 tf1 Rise time Fall time TEST CONDITIONS MIN TYP SOUT OUTn, VCC = 5 V, TA = 60°C, DCx = 3F 16 10 SOUT OUTn, VCC = 5 V, TA = 60°C, DCx = 3F MAX 30 16 10 30 UNIT ns ns tpd0 SCLK–SOUT (see Figure 11) 30 ns tpd1 DCPRG–OUT0 30 ns tpd2 BLANK–OUT0 (see Figure 13 ) 60 ns OUTn - XERR (see Figure 13 ) 1000 ns tpd3 Propagation delay time tpd4 GSCLK–OUT0 (see Figure 13 ) tpd5 XLAT–IOUT (dot correction) td Output delay time OUTn–OUT(n+1) (see Figure 13 ) 20 60 ns 1000 ns 30 ns 5 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 DEVICE INFORMATION PWP PACKAGE (TOP VIEW) GND BLANK XLAT SCLK SIN VPRG OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Thermal PAD NT PACKAGE (TOP VIEW) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC IREF DCPRG GSCLK SOUT XERR OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT1 1 28 OUT0 OUT2 2 27 VPRG OUT3 3 26 SIN OUT4 4 25 SCLK OUT5 5 24 XLAT OUT6 6 23 BLANK OUT7 7 22 GND OUT8 8 21 VCC OUT9 9 20 IREF OUT10 10 19 DCPRG OUT11 11 18 GSCLK OUT12 12 17 SOUT OUT13 13 16 XERR OUT14 14 15 OUT15 GSCLK SOUT XERR OUT15 OUT14 OUT13 OUT12 OUT11 24 23 22 21 20 19 18 17 RHB PACKAGE (TOP VIEW) DCPRG 25 16 OUT10 IREF 26 15 OUT9 VCC 27 14 OUT8 NC 28 13 NC NC 29 12 NC GND 30 11 OUT7 BLANK 31 10 OUT6 XLAT 32 9 OUT5 NC − No internal connection 6 OUT4 8 OUT3 7 OUT2 6 OUT1 5 OUT0 4 SIN 2 VPRG 3 SCLK 1 THERMAL PAD TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTION TERMINAL NAME NO. I/O DESCRIPTION DIP PWP RHB BLANK 23 2 31 I Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also reset. When BLANK = L, OUTn are controlled by grayscale PWM control. DCPRG 19 26 25 I Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H, DC is connected to the DC register. DCPRG is also controls EEPROM writing, when VPRG = V(PRG) GND 22 1 30 G Ground GSCLK 18 25 24 I Reference clock for grayscale PWM control IREF 20 27 26 I Reference current terminal NC – – 12, 13, 28, 29 OUT0 28 7 4 O Constant current output OUT1 1 8 5 O Constant current output OUT2 2 9 6 O Constant current output OUT3 3 10 7 O Constant current output OUT4 4 11 8 O Constant current output OUT5 5 12 9 O Constant current output OUT6 6 13 10 O Constant current output OUT7 7 14 11 O Constant current output OUT8 8 15 14 O Constant current output OUT9 9 16 15 O Constant current output OUT10 10 17 16 O Constant current output OUT11 11 18 17 O Constant current output OUT12 12 19 18 O Constant current output OUT13 13 20 19 O Constant current output OUT14 14 21 20 O Constant current output OUT15 15 22 21 O Constant current output SCLK 25 4 1 I Serial data shift clock SIN 26 5 2 I Serial data input SOUT 17 24 23 O Serial data output VCC 21 28 27 I Power supply voltage VPRG 27 6 3 I Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the device is in DC mode. When VPRG = V(PRG), DC register data can programmed into DC EEPROM with DCPRG=HIGH. XERR 16 23 22 O Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected. XLAT 24 3 32 I Data latch. Note that the internal connections are switched by VPRG. At XLAT↑ (VPRG = GND), GS register gets new data. At XLAT↑ (VPRG = VCC), DC register gets new data. No connection 7 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Resistor values are equivalent resistances, and they are not tested. INPUT EQUIVALENT CIRCUIT (BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG) OUTPUT EQUIVALENT CIRCUIT (SOUT) VCC 23 W 400 W INPUT SOUT 23 W GND GND INPUT EQUIVALENT CIRCUIT (IREF) VCC _ 400 W INPUT Amp OUTPUT EQUIVALENT CIRCUIT (XERR) 23 W XERR + 100 W GND GND INPUT EQUIVALENT CIRCUIT (VCC) OUTPUT EQUIVALENT CIRCUIT (OUT) INPUT OUT GND INPUT EQUIVALENT CIRCUIT (VPRG) INPUT GND GND Figure 1. Input and Output Equivalent Circuits 8 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION (continued) twho, twIO, twh1, twl1, tsu0 tsu4, th4 V(LED) = 4 V SOUT Testpoint RL = 51 CL = 15 pF OUTn Testpoint CL = 15 pF IOLC, IOLC3, IOLC4, IOUT/IREF V(LED) = 1 V OUT0 VCC = 0 V ~ 7 V OUTn + _ OUT15 IREF Testpoint RIREF = 640 Figure 2. Parameter Measurement Circuits 9 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS REFERENCE RESISTOR vs OUTPUT CURRENT POWER DISSIPATION RATE vs FREE-AIR TEMPERATURE 4k Power Dissipation Rate - mA Reference Resistor, R(IREF) - W 100 k 10 k 1k TLC5940RHB 3k TLC5940NT 2k TLC5940PWP PowerPAD Unsoldered 1k 0 -40 100 0 20 40 80 60 100 TLC5940PWP PowerPAD Soldered 120 -20 0 20 Figure 4. OUTPUT CURRENT vs OUTPUT VOLTAGE 100 90 IO - Output Current - mA 80 70 Imax = 60 mA 60 50 40 Imax = 30 mA 30 20 Imax = 5 mA 10 0 0 0.3 80 60 TA − Free-Air Temperature − C Figure 3. 0.6 0.9 1.2 1.5 1.8 2.1 2.4 VO − Output Voltage − V Figure 5. 10 40 o IO − Output Current − mA 2.7 3 100 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 PRINCIPLES OF OPERATION SERIAL INTERFACE The TLC5940 includes a flexible serial interface, which can be connected to microcontrollers or digital signal processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a rising edge of XLAT latches the serial data to the internal registers. All data are clocked in with the MSB first. Multiple TLC5940 devices can be cascaded by connecting the SOUT pin of one device with the SIN pin of the following device. The SOUT pin can also be connected to the controller to receive status information from TLC5940. The serial data format is 96-bit or 192-bit wide, depending on programming mode of the device. DC Mode Data Input Cycle Vcc GS Mode Data Input Cycle DC Mode Data Input Cycle VPRG th3 tsu3 th3 XLAT DC n MSB SIN DC n LSB th2 1 SCLK 96 DC n MSB SOUT DC n LSB GS MSB GS LSB tsu2 th2 192 1 DC MSB DC n+1 MSB X X tsu2 193 GS MSB DC n+1 MSB−1 1 SID MSB 2 X Figure 6. Serial Data Input Timing Chart ERROR INFORMATION OUTPUT The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error (see Figure 14). To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH. Table 1. XERR Truth Table ERROR CONDITION ERROR INFORMATION TEMPERATURE OUTn VOLTAGE TJ < T(TEF) TJ > T(TEF) TJ < T(TEF) TJ > T(TEF) SIGNALS TEF LOD BLANK XERR Don't Care L X H H Don't Care H X L OUTn > V(LED) L L H OUTn < V(LED) L H OUTn > V(LED) H L OUTn < V(LED) H H L L L L 11 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 TEF: THERMAL ERROR FLAG The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If the junction temperature exceeds the threshold temperature (160°C typical), the TEF circuit trips and pulls XERR to ground. TEF status can also be read out from the TLC5940 status register. LOD: LED OPEN DETECTION The TLC5940 provides an LED open-detection circuit (LOD). This circuit reports an error if any one of the 16 LEDs is open or disconnected from the circuit. The LOD circuit trips when the following two conditions are met simultaneously: 1. BLANK is set to LOW 2. When the voltage at OUTn is less than V(LED) of 0.3 V (typical) (Note: the voltage at each OUTn is sampled 1 µs after being turned on). The LOD circuit also pulls XERR to GND when tripped. The LOD status of each channel can also be read out from the TLC5940 status information data (SID) in GS data input cycle. DELAY BETWEEN OUTPUTS The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current driver block of the device (see the functional block diagram). The fixed-delay time is 20 ns (typical), OUT0 has no delay, OUT1 has 20 ns delay, and OUT2 has 40 ns delay, etc. The maximum delay is 300 ns from OUT0 to OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large inrush currents which reduces the bypass capacitors when the outputs turn on. OUTPUT ENABLE All OUTn channels of TLC5940 can switched off with one signal. When BLANK is set to high, all OUTn are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When BLANK is set to low, all OUTn work under normal conditions. Table 2. BLANK Signal Truth Table BLANK OUT0 - OUT15 LOW Normal condition HIGH Disabled SETTING MAXIMUM CHANNEL CURRENT The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of 1.24 V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of 31.5. The maximum output current can be calculated by Equation 1: V (IREF) I max 31.5 R (IREF) (1) where: V(IREF) = 1.24 V R(IREF) = User selected external resistor. Figure 3 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF terminal to GND, and IO is the constant output current of OUT0 to OUT15. 12 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 POWER DISSIPATION CALCULATION The device power dissipation needs to be below the power dissipation rate of the device package to ensure correct operation. Equation 2 calculates the power dissipation of device: DC n x dPWM x N PD = VCC x ICC + VOUT x IMAX x 63 (2) ( ) ( ) where: VCC: device supply voltage ICC: device supply current VOUT: TLC5940 OUTn voltage when driving LED current IMAX: LED current adjusted by R(IREF) Resistor DCn: maximum dot correction value for OUTn N: number of OUTn driving LED at the same time dPWM: duty cycle defined by BLANK pin or GS PWM value OPERATING MODES The TLC5940 has different operating modes depending on the signals VPRG and DCPRG. Table 3 shows the available operating modes. The TLC5940 GS operating mode (see Figure 11) and shift register values are not defined after power up. One solution to solve this is to set dot correction data after TLC5940 power up and switch back to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch it while TLC5940 is in GS PWM mode. Table 3. TLC5940 Operating Modes Truth Table SIGNAL DCPRG L H L H L H INPUT SHIFT REGISTER MODE GND 192 bit Grayscale PWM Mode VCC 96 bit Dot Correction Data Input Mode V(PRG) X EEPROM Programming Mode VCPRG DC VALUE EEPROM DC Register EEPROM DC Register EEPROM Write dc register value to EEPROM SETTING DOT CORRECTION The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. Equation 3 determines the output current for each output n: I I max DCn OUTn 63 (3) where: Imax = the maximum programmable output current for each output. DCn = the programmed dot correction value for output n (DCn = 0 to 63). n = 0 to 15 Dot correction data are entered for all channels at the same time. The complete dot correction data format consists of 16 x 6-bit words, which forms a 96-bit wide serial data packet. The channel data is put one after another. All data is clocked in with MSB first. Figure 7 shows the DC data format. 13 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 LSB MSB 0 5 6 79 90 95 DC 0.0 DC 0.5 DC 1.0 DC 14.5 DC 15.0 DC 15.5 DC OUT0 DC OUT15 DC OUT2 − DC OUT14 Figure 7. Dot Correction Data Packet Format To input data into the dot correction register, VPRG must be set to VCC. The internal input shift register is then set to 96-bit width. After all serial data are clocked in, a rising edge of XLAT is used to latch the data into the dot correction register. Figure 8 shows the dc data input timing chart. DC Mode Data Input Cycle n DC Mode Data Input Cycle n+1 VCC MODE SIN DC n MSB DC n MSB−1 DC n MSB−2 DC n LSB+1 DC n LSB DC n+1 MSB DC n+1 MSB−1 twh0 SCLK 1 2 3 95 96 1 2 twl0 SOUT DC n−1 MSB DC n−1 MSB−1 DC n−1 MSB−2 DC n−1 LSB+1 DC n MSB DC n−1 LSB DC n MSB−1 DC n MSB−2 twh2 tsu1 th1 XLAT Figure 8. Dot Correction Data Input Timing Chart The TLC5940 has also an EEPROM to store dot correction data. To store data from the dot correction register to EEPROM, DCPRG is set to high after applying VPRG to VPRG pin. Figure 9 shows the EEPROM programming timings. DC EEPROM Write Timing V(PRG) VPRG 0 V or VCC tsu5 tprog th5 DCPRG Figure 9. EEPROM Programming Timing Chart 14 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 SETTING GRAYSCALE The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12-bit per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 4 determines the brightness level for each output n: Brightness in % GSn 100 4095 (4) where: GSn = the programmed grayscale value for output n (GSn = 0 to 4095) n = 0 to 15 Grayscale data for all OUTn The input shift register enters grayscale data into grayscale register for all channels simultaneously. The complete grayscale data format consists of 16 x 12 bit words, which forms a 192-bit wide data packet (see Figure 10). The data packet must be clocked in with the MSB first. LSB 0 11 12 GS 0.0 GS 0.11 GS 0.0 178 MSB 191 180 GS 14.11 GS15.0 GS OUT0 GS 15.11 GS OUT2 − GS OUT14 GS OUT15 Figure 10. Grayscale Data Packet Format When VPRG is set to GND, TLC5940 enters the grayscale data input mode. The device switches the input shift register to 192-bit width. After all data is clocked in, a rising edge of XLAT signal latches the data into the grayscale register (see Figure 11). The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register is replaced with status information data (SID) after latching into grayscale register. First GS Mode Data Input Cycle After DC Data Input Cycle DC Mode Data Input Cycle Following GS Mode Data Input Cycle MODE tsu3 th3 th3 XLAT twh2 tsu2 th2 SCLK GS LSB GS MSB DC LSB SIN 96 GS + 1 MSB th1 tsu1 192 1 GS + 1 LSB 193 1 192 tpd0 n SOUT DC LSB DC MSB X X GS MSB SID MSB SID MSB−1 SID LSB SID n + 1 MSB Figure 11. Grayscale Data Input Timing Chart 15 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 STATUS INFORMATION OUTPUT The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG = GND). After the XLAT signal latches the data into GS register the input shift register data will be replaced with status information data (SID) of the device (see Figure 11). LOD, TEF and dot correction EEPROM data (DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at the SOUT pin. The status information data packet is 192-bit wide. Bit 176 - bit 191 contains the LOD status of each channel. Bit 175 contains the TEF status. If DCPRG is low, bit 72 - bit 167 contains the value of the dot correction EEPROM. If DCPRG is high, bit 72 - bit 167 contains the data of the dot correction register. The remaining bits are reserved. The complete status information data packet is shown in Figure 12. LSB MSB 0 71 72 167 168 X X DC 0.0 DC15.5 X Reserved X DC Values 175 176 191 TEF LOD 0 LOD 15 TEF LOD Data Figure 12. Status Information Data Packet Format GRAYSCALE PWM OPERATION The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to counter values are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and completes the grayscale PWM cycle (see Figure 13). GS PWM Cycle n BLANK GS PWM Cycle n+1 twl1 twh1 th4 GSCLK 1 OUT0 (Current) tpd2 2 tpd4 4096 3 tpd4 tpd4+ n x td tpd2 + td tpd2 + 14 x td OUT15 (Current) tpd3 XERR Figure 13. Grayscale PWM Cycle Timing Chart 16 tsu4 1 twl1 nxtd OUT1 (Current) twh3 TLC5940 www.ti.com SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005 SERIAL DATA TRANSFER RATE Figure 14 shows a cascading connection of n TLC5940 devices connected to a controller, building a basic module of an LED display system. The maximum number of cascading TLC5940 devices depends on the application system and is in the range of 40 devices. Equation 5 calculates the minimum frequency needed: f 4096 f (GSCLK) (update) f (SCLK) 193 f (update) n (5) where: f(GSCLK): minimum frequency needed for GSCLK f(SCLK): minimum frequency needed for SCLK and SIN f(update): update rate of whole cascading system n: number cascaded of TLC5940 device APPLICATION EXAMPLE VCC V(LED) V(LED) V(LED) V(LED) 100 k OUT0 SIN XERR SCLK SCLK VCC 100 nF TLC5940 GSCLK DCPRG DCPRG BLANK BLANK SOUT VPRG OUT15 SIN SOUT XERR VCC SCLK XLAT GSCLK OUT0 SOUT XERR XLAT Controller OUT15 SIN IREF 100 nF XLAT GSCLK TLC5940 DCPRG IREF BLANK IC 0 VPRG IC n W_EEPROM 7 VPRG_D VPRG_OE V(22V) 50 k V(22V) 50 k 50 k 50 k 50 k 50 k VPRG Figure 14. Cascading Devices 17 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TLC5940NT ACTIVE PDIP NT 28 13 TBD Call TI TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940RHB ACTIVE QFN RHB 32 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940RHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 73 Level-NA-NA-NA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5940NT ACTIVE PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLC5940NTG4 ACTIVE PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940RHB ACTIVE QFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940RHBG4 ACTIVE QFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940RHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5940RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI004 – OCTOBER 1994 NT (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PINS SHOWN PINS ** A 24 28 A MAX 1.260 (32,04) 1.425 (36,20) A MIN 1.230 (31,24) 1.385 (35,18) B MAX 0.310 (7,87) 0.315 (8,00) B MIN 0.290 (7,37) 0.295 (7,49) DIM 24 13 0.280 (7,11) 0.250 (6,35) 1 12 0.070 (1,78) MAX B 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0°– 15° 0.010 (0,25) M 0.010 (0,25) NOM 4040050 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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