EMC EM73PA88AAQ

EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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GENERAL DESCRIPTION
EM73PA88A is an advanced single chip CMOS 4-bit one-time programming (OTP) micro-controller. It contains
16K-byte ROM, 500-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/
counters for the kernel function. EM73PA88A also equipped with 6 interrupt sources, 3 I/O ports (including 1
input port and 2 bidirection ports), LCD display (64x16), built-in sound generator and speech synthesizer can direct
drive speaker.
It's low power consumption and high speed feature are further strengten with DUAL, SLOW, IDLE and STOP
operation mode for optimized power saving.
FEATURES
• Operation voltage
• Clock source
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
: 2.2V to 4.8V.
: Dual clock system. Low-frequency oscillator is 32 KHz Crystal or RC oscillator
and high-frequency oscillator is a built-in internal oscillator (4.6 MHz).
Instruction set
: 107 powerful instructions.
Instruction cycle time
: 1.7µs for 4.6M Hz (high speed clock).
244µs for 32768 Hz (low speed clock).
ROM capacity
: 16K x 8 bits.
RAM capacity
: 500 x 4 bits.
Input port
: 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option.
(each input pin has a pull-up and pull-down resistor available by mask option).
Bidrection port
: 2 ports (P4, P8). IDLE/STOP release function for P8(0..3) is available by mask
option.
Built-in watch-dog-timer counter : It is available by mask option.
12-bit timer/counter
: Two 12-bit timer/counters are programmable for timer, event counter and pulse
width measurement mode.
Built-in time base counter : 22 stages.
Subroutine nesting
: Up to 13 levels.
Interrupt
: External interrupt . . . . . . 2 input interrupt sources.
Internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt.
1 speech interrupt.
LCD driver
: 64x16 dots, 1/16 duty, 1/5 bias with voltage multiplier.
Sound effect
: Tone generator and random generator.
Speech synthesizer
: 448K speech data ROM (use as 448K nibbles data ROM).
PWM or current D/A
: Output selection by mask option.
Power saving function : SLOW, IDLE, STOP operation modes.
Package type
: Chip form 109 pins.
QFP form 160 pins (AQ).
QFP form 128 pins (BQ).
* This specification are subject to be changed without notice.
10.8.2001
1
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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FUNCTION BLOCK DIAGRAM
CLK LXIN LXOUT
RESET
Reset
Control
Clock
Generator
Clock Mode
Control
Timing
Generator
System Control
Data pointer
Time
Base
ROM
Stack
ALU
RAM
Flag
Z
Timer/Counter
(TA,TB)
Stack pointer
ACC
Data Bus
Interrupt
Control
Instruction Decoder
Instruction Register
C
S
PC
HR
I/O Control
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
Sound
Generator
P4.0
P4.1
P4.2
P4.3
P8.0(INT1)/WAKEUPA
P8.1(TRGB)/WAKEUPB
P8.2(INT0)/WAKEUPC
P8.3(TRGA)/WAKEUPD
BZ2
Speech
synthesizer
BZ1
SEG0~SEG63
LCD Driver
COM0~COM15
V1~V5
VA,VB
LR
* This specification are subject to be changed without notice.
10.8.2001
2
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
NC
NC
NC
PIN ASSIGNMENT
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
EM73PA88AAQ
QFP 160
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
NC
NC
NC
NC
NC
NC
NC
NC
NC
NG
NG
NG
SEG33
SEG32
P8.0/DIN
P8.1/DOUT
P8.2
P8.3
P4.0
P4.1
P4.2
P4.3
P0.0/ACLK
P0.1/PGM
P0.2/OE
P0.3/DCLK
VDD2
BZ1
BZ2
VSS
RESET
CLK
VPP
LXIN
LXOUT
VDD
V1
V2
V3
V4
V5
VA
VB
SEG31
SEG30
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
NC
NC
NC
NC
NC
NC
NC
NC
NC
* This specification are subject to be changed without notice.
10.8.2001
3
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC
NC
NC
NC
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
NC
PIN ASSIGNMENT
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
EM73PA88ABQ
QFP 128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
NC
NC
NC
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
NC
NC
NC
NC
NC
SEG32
P8.0/DIN
P8.1/DOUT
P8.2
P8.3
P4.0
P4.1
P4.2
P4.3
P0.0/ACLK
P0.1/PGM
P0.2/OE
P0.3/DCLK
VDD2
BZ1
BZ2
VSS
RESET
CLK
VPP
LXIN
LXOUT
VDD
V1
V2
V3
V4
V5
VA
VB
SEG31
SEG30
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
NC
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
NC
NC
* This specification are subject to be changed without notice.
10.8.2001
4
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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PIN DESCRIPTIONS
Symbol
VDD
Pin-type
Function
Power supply (+).
Power supply (+) for programming OTP.
VDD2
Power supply (+).
VSS
Power supply (-).
Power supply (-) for programming OTP.
RESET
RESET-A
System reset input signal, low active.
Reset input signal for programming OTP.
Always internal pull-up.
CLK
OSC-G
Capacitor connecting pin for internal high frequency oscillator.
LXIN
OSC-B/OSC-H Crystal or RC osc connecting pin for low speed clock source.
LXOUT
OSC-B
Crystal osc connecting pin for low speed clock source.
P0(0..3)/WAKEUP0..3 INPUT-B
4-bit input port with IDLE/STOP releasing function
P0.0/ACLK : address counter clock for programming OTP.
P0.1/PGMB : program data to OTP cells for programming OTP.
P0.2/OEB : data output enable for programming OTP.
P0.3/DCLK : data in/out clock signal for programming OTP.
mask option :
wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P4(0..3)
I/O-O
4-bit bidirection I/O port with high current source.
mask option :
open-drain
push-pull, high current PMOS
push-pull, low current PMOS
P8.0(INT1)/WAKEUPA I/O-L
2-bit bidirection I/O port with external interrupt sources input and IDLE
P8.2(INT0)/WAKEUPC
/STOP releasing function.
P8.0/DIN : data input for programming OTP.
mask option :
wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
P8.1(TRGB)/WAKEUPB I/O-L
2-bit bidirection I/O port with time/counter A,B external input and IDLE
P8.3(TRGA)/WAKEUPD
/STOP releasing function.
P8.1/DOUT : data output for programming OTP.
mask option :
wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
BZ1
Tone / Speech PWM / D/A output pin.
BZ2
Tone / Speech PWM output pin.
V1, V2, V3, V4, V5,
LCD bias pins.
VA, VB
COM0~COM15
LCD common output pins.
SEG0~SEG63
LCD segment output pins.
TEST/VPP
Test pin must be floating.
VPP : high voltage (12V) power source for programming OTP.
* This specification are subject to be changed without notice.
10.8.2001
5
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
FUNCTION DESCRIPTIONS
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PROGRAM ROM ( 16K X 8 bits )
16 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of the program ROM may be categorized into 5 partitions.
1. Address 0000h: Reset start address.
2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses.
3. Address 000Eh-0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,0086h.
4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and
data region.
address
Bank 0 :
0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0086h
Reset start address
INT0 ; interrupt service routine entry address
SPI
TRGA
TRGB
TBI
INT1
Subroutine call entry address
designated by [LCALL a]
instruction
SCALL, subroutine call entry address
..
.
07FFh
0800h
0FFFh
1000h
1FFFh
Bank 1
Bank 2
Data table for
[LDAX],[LDAXI]
instruction
Bank 3
* This specification are subject to be changed without notice.
10.8.2001
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EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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User's program and fixed data are stored in the program ROM. User's program is executed using the PC value
to fetch an instruction code.
The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank.
The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC
and P3 are initialized to "0" during reset.
When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0 and
bank2 will be selected.
Address
0000h
:
:
0FFFh
1000h
:
:
1FFFh
P3=xx00B
P3=xx01B
P3=xx10B
Bank0
Bank0
Bank0
Bank1
Bank2
Bank3
PROGRAM EXAMPLE :
BANK 0
:
:
:
LDIA #00H
; set program ROM to bank1
OUTA P3
B
XA1
:
XA :
:
:
LDIA #01H
; set program ROM to bank2
OUTA P3
B
XB1
:
XB :
:
:
LDIA #02H
; set program ROM to bank3
OUTA P3
B
XC1
:
XC :
:
:
B
XD
XD :
:
:
:
;--------------- -------------------- -------------------- -------------------- -BANK 1
XA1 :
:
:
B
XA
:
XA2 :
:
START:
* This specification are subject to be changed without notice.
10.8.2001
7
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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B
XA2
:
;--------------- -------------------- -------------------- -------------------- -BANK 2
XB1 :
:
:
B
XB
:
XB2 :
:
B
XB2
:
;--------------- -------------------- -------------------- -------------------- -BANK 3
XC1 :
:
:
B
XC
:
XC2 :
:
B
XC2
Fixed data can be read out by table-look-up instruction. Table-look-up instruction is requires the Data point
(DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) :
LDAX
LDAXI
Acc ← ROM[DP]L
Acc ← ROM[DP]H,DP+1
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH",
then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction
"LDAXI"
PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h;
STADPL
STADPM
STADPH
:
LDL #00h;
LDH #03h;
LDAX
STAMI
LDAXI
STAM
;
ORG 1777h
DATA 56h;
; [DP]L ← 07h
; [DP]M ← 07h
; [DP]H ← 07h, Load DP=777h
; ACC ← 6h
; RAM[30] ← 6h
; ACC ← 5h
; RAM[31] ← 5h
DATA RAM ( 500-nibble )
A total 500 - nibble data RAM is available from address 000 to 1FFh
Data RAM includes the zero page region, stacks and data areas.
* This specification are subject to be changed without notice.
10.8.2001
8
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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Increment
Address
Bank 0
Increment
Zero-page
000h - 00Fh
010h - 01Fh
020h - 02Fh
:
:
:
0C0h - 0CFh
0D0h - 0DFh
0E0h - 0EFh
0F0h - 0F3h
Bank 1
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
Level 12
100h - 10Fh
110h - 11Fh
:
:
:
1E0h - 1EFh
1F0h - 1FFh
ZERO- PAGE:
From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To write immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh].
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL).
User can assign any level be the starting stack by providing the level number to stack pointer (SP).
When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address
is saved into the stack until returned from those subroutines, the PC value is restored by the data saved
in stack.
DATA AREA:
Except the area used by user's application, the whole RAM can be used as data area for storing and loading
general data.
ADDRESSING MODE
The 500 nibble data memory consists of two banks (bank 0 and bank 1). There are 244x4 bits (address
000h~0F3h) in bank 0 and 256x4 bits (address 100h~1FFh) in bank 1.
* This specification are subject to be changed without notice.
10.8.2001
9
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected. When P9.3 is set to "1", the bank
1 is selected.
The Data Memory consists of three Address mode, namely (1) Indirect addressing mode:
The address in the bank is specified by the HL registers.
P9.3
HR
LR
RAM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "032h".
SEP P9,3
LDL #3h
LDH #4h
LDAM
CLP P9,3
LDL #2h
LDH #3h
STAM
; P9.3← 1
; LR← 3
; HR← 4
; Acc← RAM[134h]
; P9.3← 0
; LR← 2
; HR← 3
; RAM[023h]← Acc
(2) Direct addressing mode:
The address in the bank is directly specified by 8 bits code of the second byte in the instruction field.
instruction field
xxxxxxxx
P9.3
xxxxxxxx
RAM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
SEP P9,3
LDA 43h
CLP P9,3
STA 23h
; P9.3← 1
; Acc← RAM[143h]
; P9.3← 0
; RAM[023h]← Acc
(3) Zero-page addressing mode:
The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits code of the second byte
in the instruction field.
instruction field
yyyy
RAM address 0
0000 yyyy
PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".
STD #0Fh, 05h ; RAM[05h]← 0Fh
* This specification are subject to be changed without notice.
10.8.2001
10
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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PROGRAM COUNTER (16K ROM) P
Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the
instruction of program ROM instruction.
For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address
from 0000h-1FFFh. The bank number is decided by P3.
(1) Branch instruction:
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC 12-6.a ( branch condition satisified )
PC Hold original PC value+1
a
a
a
a
a
a
SF=0; PC← PC +1( branch condition not satisified)
PC
Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← PC 12.a ( branch condition satisified )
PC
Hold
+2
a
a a
a
a
a
a
a
a
a
a
a
SF=0; PC← PC +2( branch condition not satisified)
PC
Original PC value + 2
SLBR a
Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)
0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)
Condition: SF=1; PC ← a ( branch condition satisified)
PC a
a
a
a
a
a
a
a
a
a
a
a
a
SF=0 ; PC ← PC + 3 ( branch condition not satisified )
PC
Original PC value + 3
(2) Subroutine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0
PC 0
0
0
0
0
a
a
a
a
a
LCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a
* This specification are subject to be changed without notice.
a
a
a
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EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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PC 0
0
a
a
a
a
a
a
a
a
a
a
a
RET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC
The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC
The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC. The interrupt vectors are as follows :
INT0 (External interrupt from P8.2)
PC 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
SPI (speech end interrupt)
PC 0
0
0
TRGA (Timer A overflow interrupt)
PC 0
0
0
0
0
TRGB (Time B overflow interrupt)
PC 0
0
0
0
0
0
0
0
0 1
0
0 0
0
0
0
0
0
0 1
0
1 0
TBI (Time base interrupt)
PC 0
0
0
INT1 (External interrupt from P8.0)
PC 0
0
0
0
0
0
0
0
0 1
1
0 0
0
0
0
0
0
0
0
0
0
0 0
(4) Reset operation:
PC 0
0
* This specification are subject to be changed without notice.
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(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
For 3-byte instruction execution: PC + 3
ACCUMULATOR
Accumulator(ACC) is a 4-bit data register for temporary data storage. For the arithematic, logic and
comparative opertion.., ACC plays a role which holds the source data and result.
FLAGS
There are three kinds of flag, CF (Carry flag), ZF (Zero flag) and SF (Status flag), these three 1-bit flags
are included by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction is executed.
(1) Carry Flag ( CF )
The carry flag is affected by the following operations:
a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1",
likewise, if the operation has no carry-out, CF is "0".
b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF
is "0", likewise, if there is no borrow-in, the CF is "1".
c. Comparision: CF as a borrow-in indicator for Comparision operation as in the subtraction operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0".
Under TTSFC instruction, the CF content is sent into SF then set itself as "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1",
likewise, the ZF is "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status.
a. SF is initiated to "1" for reset condition.
b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise, when SF = 0,
branch condition is unsatisified.
* This specification are subject to be changed without notice.
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PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF
CF
-
LDIA #00h;
LDIA #03h;
ADDA #05h;
ADDA #0Dh;
ADDA #0Eh;
ZF
1
0
0
0
0
SF
1
1
1
0
0
ALU
The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags that can be affected by
the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only.
ALU STRUCTURE
ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion.
DATA BUS
ALU
ZF CF SF
ALU FUNCTION
(1) Addition:
ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... .
The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1",
otherwise, ZF will be "0", When the addition operation has a carry-out. CF will be "1", otherwise, CF will
be "0".
EXAMPLE:
Operation
3+4=7
7+F=6
0+0=0
8+8=0
Carry
0
1
0
1
Zero
0
0
1
1
(2) Subtraction:
ALU supports subtraction function with instructions SUBM #k, SUBA #k, SBCAM, DECM... . The
subtraction operation affects CF and ZF. Under subtraction operation, if the result is negative, CF will
be "0", and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction
operation is "0", the ZF is "1", likewise, ZF is "1".
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
EXAMPLE:
Operation
8-4=4
7-F= -8(1000)
9-9=0
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Carry
1
0
1
Zero
0
0
1
(3) Rotation:
Two types of rotation operation are available, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value counter-clockwise, shift the CF value into the LSB bit of Acc and hold
the shift out data in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value clockwise, shift the CF value into the MSB bit of Acc and
hold the shift out data in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc clockwise (right) and shift a "1" into the MSB bit of Acc.
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the RAM memoryaddress. They are
used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer
to indicate the pin number ( Port4 only ).
HL REGISTER STRUCTURE
3
2
1
0
3
2
1
0
H REGISTER L REGISTER
HL REGISTER FUNCTION
(1) HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL,
EXAL, EXAH.
PROGRAM EXAMPLE: Load immediate data "5h" into L register, "0Dh" into H register.
LDL #05h;
LDH #0Dh;
(2) HL register is used as a pointer for the address of RAM memory for instructions : LDAM, STAM, STAMI ..,
PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h.
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) L register is used as a pointer to indicate the bit of I/O port for instructions : SELP, CLPL, TFPL,
(When LR = 0 indicate P4.0)
PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"
LDL #00h;
SEPL ; P4.0 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register that stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition.
When a new subroutine is received, the SP is decreased by one automatically, likewise, if returning from
a subroutine, the SP is increased by one.
The data transfer between ACC and SP is done with instructions "LDASP" and "STASP".
DATA POINTER (DP)
Data pointer is a 12-bit register that stores the ROM address can indicating the ROM code data
specified by user (refer to data ROM).
CLOCK AND TIMING GENERATOR
The clock generator is supported by a dual clock system. The high-frequency oscillator is internal oscillator,
the working frequency is 4.6 MHz. The low-frequency oscillator may be sourced from crystal or RC osc,
the working frequency is 32 KHz.
CLOCK GENERATOR STRUCTURE
There are two clock generator for system clock control unit, P14 is the status register that hold the CPU
status. P16, P19 and P22 are the command register for system clock mode control.
CLK
High-frequency
generator
fc
LXIN
LXOUT
Low-frequency
generator
P14
fs
P16
System clock
mode control
P19
P22
System control
LXIN
VDD
R
LXIN
LXOUT
open
LXOUT
Crystal connection
RC oscillator connection
R=1MΩ
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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SYSTEM CLOCK MODE CONTROL
The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator
and switch between the basic clocks. EM73PA88A has four operation modes (DUAL, SLOW, IDLE and
STOP operation modes).
STOP
operation
mode
I/O wakeup
High osc : stopped
Low osc : stopped
Command
(P16)
Reset
Reset
Command
(P16)
Command
(P22)
Command
(P22)
Reset release
RESET
operation
High osc : oscillating
Low osc : oscillating
NORMAL
operation
mode
Reset
SLOW
operation
mode
High osc : stopped
Low osc : oscillating
Command
(P19)
Reset
I/O or internal timer wakeup
IDLE
(CPU
stops)
High osc : stopped
Low osc : oscillating
Operation Mode
NORMAL
SLOW
IDLE
STOP
Oscillator
System Clock
Available function
One instruction cycle
High, Low frequency High frequency clock LCD, speech, sound gen.
8 / fc
Low frequency
Low frequency clock
LCD
8 / fs
Low frequency
CPU stops
LCD
None
CPU stops
All disable
-
DUAL OPERATION MODE
The 4-bit µc is in the DUAL operation mode when the CPU is reseted. This mode is dual clock system
(high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation
mode with the command register (P22 or P16).
LCD display, speech synthesizer and sound generator are available for the DUAL operation mode.
SLOW OPERATION MODE
The SLOW operation mode is single clock system (low-frequency clock oscillating). It can be changed to
the DUAL operation mode with the command register (P22), STOP operation mode with P16 and IDEL
operation mode with P19.
LCD display is available for the SLOW operation mode. Speech synthesizer and sound generator are
disabled in this mode.
* This specification are subject to be changed without notice.
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P22
3
*
2
SOM
0 0 0
1 * *
P14
3
*
1
SOM
0
Initial value : 0000
Select operation mode
DUAL operation mode
SLOW operation mode
2
WKS
1
0
LFS CPUS
Initial value : *000
LFS
0
1
Low-frequency status
LXIN source is not stable
LXIN source is stable
WKS
0
1
Wakeup status
Wakeup not by internal timer
Wakeup by internal timer
CPUS
0
1
CPU status
DUAL operation mode
SLOW operation mode
Port14 is the status register for CPU. P14.0 (CPU status) and P14.1 (Low-frequency status) are read-only
bits. P14.2 (wakeup status) will be set as "1" when CPU is waked by internal timer. P14.2 will be cleared as
"0" when user out data to P14.
IDLE OPERATION MODE
The IDLE operation mode suspends all CPU functions except the low-frequency clock oscillation and the
LCD driver. It keeps the internal status with low power consumption without stopping the slow clock
oscillator and LCD display.
LCD display is available for the IDLE operation mode. Sound generator is disabled in this mode. The IDLE
operation mode will be wakeup and return to the SLOW operation mode by the internal timing generator or
I/O pins (P0(0..3)/WAKEUP 0..3 and P8(0..3)/WAKEUPA..D).
P19
3
*
IDME
1
0
2
IDME
1
0
SIDR
Enable IDLE mode
Enable IDLE mode
no function
Initial value : 0000
SIDR
0 0
0 1
1 0
1 1
Select IDLE releasing condition
P0(0..3), P8(0..3) pin input
P0(0..3), P8(0..3) pin input and 1 sec signal
P0(0..3), P8(0..3) pin input and 0.5 sec signal
P0(0..3), P8(0..3) pin input and 15.625 ms signal
STOP OPERATION MODE
The STOP operation mode suspends system operation and holds the internal status immediately before the
suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/
WAKEUP 0..3 and P8(0..3)/WAKEUP A..D).
LCD display and sound generator are disabled in the STOP operation mode.
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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P16
3
*
2
SPME
SPME
1
0
1
0
SWWT
Initial value : 0000
Enable STOP mode
Enable STOP mode
no function
SWWT
0 0
0 1
1 0
1 1
Set wake-up warm-up time
214/LXIN
210/LXIN
212/LXIN
no function
TIME BASE INTERRUPT (TBI )
The time base can be used to generate a single fixed frequency interrupt. Eight types of frequencies can be
selected with the "P25" setting.
P25 3
2
1
0
initial value : 0000
0
0
0
0
0
1
1
1
1
1
P25
0 x
1 0
1 0
1 1
1 1
1 0
1 0
1 1
1 1
0 x
x
0
1
0
1
0
1
0
1
x
DUAL operation mode
Interrupt disable
Interrupt frequency LXIN / 23 Hz
Interrupt frequency LXIN / 24 Hz
Interrupt frequency LXIN / 25 Hz
Interrupt frequency LXIN / 214 Hz
Interrupt frequency LXIN / 21 Hz
Interrupt frequency LXIN / 26 Hz
Interrupt frequency LXIN / 28 Hz
Interrupt frequency LXIN / 210 Hz
Reserved
SLOW operation mode
Interrupt disable
Reserved
Reserved
Reserved
Interrupt frequency LXIN / 214 Hz
Reserved
Interrupt frequency LXIN / 26 Hz
Interrupt frequency LXIN / 28 Hz
Interrupt frequency LXIN / 210 Hz
Reserved
TIMER / COUNTER ( TIMERA, TIMERB)
Timer/counters support three special functions:
1. Even counter
2. Timer.
3. Pulse-width measurement.
These three functions can be executed by 2 timer/counter independently.
With timerA, the counter data is saved in timer register TAH, TAM, TAL. User can set counter initial
value and read the counter value by instruction "LDATAH(M,L)" and "STATAH(M,L)". With timer B
register is TBH, TBM, TBL and the W/R instruction are "LDATBH (M,L)" and "STATBH (M,L)".
The basic structure of timer/counter is composed by two identical counter module, these two modules can
be set initial timer or counter value to the timer registers, P28 and P29 are the command registers for timerA
and timer B, user can choose different operation modes and internal clock rates by setting these two
registers. When timer/counter overflows, it will generate a TRGA(B) interrupt request to interrupt control
unit.
* This specification are subject to be changed without notice.
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INTERRUPT CONTROL
TRGB request
TRGA request
DATA BUS
P8.3/
TRGA
12 BIT COUNTER
12 BIT COUNTER
EVENT COUNTER CONTROL
EVENT COUNTER CONTROL
TIMER CONTROL
TIMER CONTROL
PULSE-WIDTH MEASUREMENT
CONTROL
PULSE-WIDTH MEASUREMENT
CONTROL
internal clock
P28
TMSA
IPSA
P29
TMSB
P8.1/
TRGB
internal clock
IPSB
TIMER/COUNTER CONTROL
P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event
counter and pulse-width measurement mode.
Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/
counterB.
Port 28
3
2
1
TMSA
0
IPSA
Initial state: 0000
Port 29
3
2
TMSB
1
0
IPSB
TIMER/COUNTER MODE SELECTION
TMSA (B)
Function description
00
Stop
0 1
Event counter mode
1 0
Timer mode
11
Pulse width measurement mode
Initial state: 0000
INTERNAL PULSE-RATE SELECTION
IPSA(B)
DUAL mode
SLOW mode
0 0
LXIN/23 Hz
Reserved
0 1
LXIN/2 7 Hz
LXIN/2 Hz
1 0
LXIN/2 11Hz
LXIN/2 Hz
1 1
LXIN/2 15 Hz
LXIN/215Hz
* This specification are subject to be changed without notice.
7
11
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TIMER/COUNTER FUNCTION
Timer/counterA,B are programmable for timer, event counter and pulse width measurement mode. Each
timer/counter can execute any of these functions independently.
EVENT COUNTER MODE
under event counter mode, the timer/counter is increased by one at any rising edge of P8.1/TRGB for timerB
(P8.3/TRGA for timer A). When timerB (timerA) counts overflow, it will provide an interrupt request
TRGB (TRGA) to interrupt control unit.
P8.1/TRGB (P8.3/TRGA)
TimerB (TimerA) value n
n+1
n+2
n+3
n+4
n+5
n+6
PROGRAM EXAMPLE: Enable timerA with P28
LDIA #0100b;
OUTA P28; Enable timerA with event counter mode
TIMER MODE
Under timer mode ,the timer/counter is increased by one at any rising edge of internal pulse. User can choose
up to 4 types of internal pulse rate by setting IPSB for timerB (IPSA for timerA).
When timer/counter counts overflow, an interrupt request will be sent to interrupt control unit.
Internal pulse
TimerB (TimerA )value
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz
LDIA #0100B;
EXAE; enable mask 2
EICIL 110111b; interrupt latch ←0, enable EI
LDIA #0Ah;
STATAL;
LDIA #00h;
STATAM;
LDIA #0Fh;
STATAH;
LDIA #1000B;
OUTA P28; enable timerA with internal pulse rate: LXIN/23 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure.
Internal pulse rate: LXIN/23 ; LXIN = 32KHz
The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms
The number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0F6h
The preset value of timer/counter register = 1000h - 0F6h = F0Ah
PULSE WIDTH MEASUREMENT MODE
* This specification are subject to be changed without notice.
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Under the pulse width measurement mode, the counter is incresed at the rising edge of internal pulse during
external timer/counter input (P8.1/TRGB, P8.3/TRGA ) in high level, interrupt request is generated as soon as
timer/counter count overflow.
P8.1/TRGB(P8.3/TRGA)
Internal pulse
TimerB(TimerA) value
n
n+1
n+2
n+3
n+4
n+5
PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode.
LDIA #1100b;
OUTA P28; Enable timerA with pulse width measurement mode.
INTERRUPT FUNCTION
Six interrupt sources are available, 2 from external interrupt sources and 4 from internal interrupt sources.
Multiple interrupts are admitted according to their priority.
Type
External
Internal
Internal
Internal
Internal
External
Interrupt source
External interrupt(INT0)
speech end interrupt (SPI)
TimerA overflow interrupt (TRGA)
TimerB overflow interrupt (TRGB)
Time base interrupt(TBI)
External interrupt(INT1)
Priority
Interrupt
Latch
Interrupt
Enable condition
ProgramROM
entry address
1
2
3
4
5
6
IL5
IL4
IL3
IL2
IL1
IL0
EI=1
EI=1, MASK3=1
EI=1, MASK2=1
EI=1, MASK1=1
002h
004h
006h
008h
00Ah
00Ch
EI=1,MASK0=1
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3
INT1
r0
Reset by system reset and program
instruction
TBI
r1
IL0
IL1
TRGB TRGA
r2
r3
IL2
IL3
SPI
INT0
r5
IL4
IL5
r4
Priority checker
Reset by system reset and program
instruction
Set by program instruction
EI
Interrupt request
Entry address generator
Interrupt entry address
Interrupt controller:
IL0-IL5
: Interrupt latch. Hold all interrupt requests from all interrupt sources. IL's can not
be set by program, but can be reset by program or system reset, so IL can only
decide which interrupt source can be accepted.
MASK0-MASK3
: Except INT0, MASK register may permit or inhibit all interrupt sources.
* This specification are subject to be changed without notice.
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: Enable interrupt Flip-Flop may promit or inhibit all interrupt sources, when inter-
EI
rupt occurs, EI is auto cleared to "0", after RTI instruction is executed, EI is auto
set to "1" again.
Priority checker : Check interrupt priority when multiple interrupts occur.
INTERRUPT OPERATION
The procedure of interrupt operation :
1. Push PC and all flags to stack.
2. Set interrupt entry address into PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts occur.
5. Clear the IL with which interrupt source has already been accepted.
6. Excute interrupt subroutine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests.
PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"
LDIA #0100B;
EXAE; set mask register "1100b"
EICIL 010111B ; enable interrupt F.F. and clear IL3 and IL5
LCD DRIVER
It can directly drive the liquid crystal display ( LCD ) and has 64 segments, 16 commons output pins.
There are total 64x16 dots can be display. The V1~V5 are the LCD bias voltage input pins.
(1) LCD driver control command register:
Port27 3 2 1 0
Initial value: 0000
LDC
*
*
LCD DISPLAY CONTROL
LDC
Function description
0 0
LCD display disable
0 1
Blanking
1 0
no function
1 1
LCD display enable
* : Don't care.
P27 is the LDC driver control command register. The initial value is 0000.
When LDC ( bit2 and bit3 of P27 ) is set to "00", the LCD display is disabled.
When LDC is set to "01", the LCD is blanking, the COM pins are inactive and the SEG pins
output the display data continuously.
When LDC is set to "11", the LCD display is enabled.
(2) LCD display data area:
The LCD display data is stored in the display data area of the data memory (RAM). The LCD display data
area is as illustrated below :
* This specification are subject to be changed without notice.
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The display data from the display data area are automatically read out and send to the LCD driver directly by
the hardware. Therefore, the display patterns can be changed only by overwritting the contents of the display
data area through software.
The dispaly memory area that is not used to store the LCD display data could be used as the ordinary data
memory.
LCD display data area :
Bank1
P9.3=1
0
1
2
3
4
100-10Fh
110-11Fh
120-12Fh
130-13Fh
140-14Fh
150-15Fh
160-16Fh
170-17Fh
180-18Fh
190-19Fh
1A0-1AFh
1B0-1BFh
1C0-1CFh
1D0-1DFh
1E0-1EFh
1F0-1FFh
5
6
7
8
9
A
B
C
D
E
F
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
P26 is the start address register of LCD common pin.
Port26
3 2 1 0
Initial value: 0000
CSA
Common start address register
RAM
CSA
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
100109h
110119h
120129h
130139h
140149h
150159h
160169h
170179h
180189h
190199h
1A01A9h
1B01B9h
1C01C9h
1D01D9h
1E01F01EF9h 1F9h
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15
COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14
COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13
COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12
COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11
COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM5
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM4
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM3
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM2
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
COM1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
PROGRAM EXAMPLE:
LDIA
OUTA
LDIA
OUTA
LDIA
SEP
STA
#0000B
P26
#1100B ; LCD display enable
P27
#1010B ; store 1010B to RAM[101h]
P9,3
01H
* This specification are subject to be changed without notice.
10.8.2001
24
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
(3) LCD waveform : (1/5 bias)
S
E
G
0
* TYPE A :
COM0
* TYPE B :
COM0
COM0
V5
V5
V4
V3
V2
V1
Vss
: ON
: OFF
V4
V3
V2
V1
Vss
COM1
COM1
SEG0
SEG0
SEG0-COM0
SEG0-COM0
ON
ON
SEG0-COM1
SEG0-COM1
OFF
OFF
COM15
Frame freq.=64Hz
Frame freq.=64Hz
(4) LCD drive voltage :
• The LCD bias voltage is supplied by voltage multiplier. The application circuit is illustated as below :
VA
0.1µF
VB
0.1µF
V5
V4
V3
V2
V1
0.1µF
0.1µF
0.1µF
0.1µF
SPEECH SYNTHESIZER
Set sound mode
Set sound freq.
P23,24 Write
Set sound effect amplitude
P30 Write
P17 Write
D/A
BZ1
PWM
Sound effect generator
speech
ROM
P7 Write
P7 Read
speech
decoder
BZ2
SPI interrupt
P5.3 read
P6 Write
P5 Write
Set data address
(write 5 times)
Read data
Set speech address
(write 4 times)
Speech active
Set sample rate
Block diagram of speech and sound effect
* This specification are subject to be changed without notice.
10.8.2001
25
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
EM73PA88A speech synthesizer operates as following :
1. Send the speech start address to the address latch by writing P6 four times.
2. Choose the sampling rate, enable the speech synthesizer by writing P5.
3. The ROM address counters send the ROM address A6 .. A17 to the speech ROM.
4. ACT is the speech acknowledge signal. When the speech synthesizer has voice output. ACT is high .
When ACT is changed from high to low, the speech synthesizer can generate the speech ending
interrupt SPI. The ACT signal can be read from P5.3.
SPEECH SYNTHESIZER CONTROL
Speech sample rate control register (P5 write) :
3
2
1
0
Initial value : *111
SR
SR
000
001
010
011
100
101
111
Sample rate selection
PWM on CLK/64/1/3
CLK/64/1/4
CLK/64/2/3
CLK/64/2/4
CLK/64/3/3
CLK/64/3/4
PWM off
Speech active flag (P5 read) :
3
2
1
0
ACT *
*
*
Sample rate
24K
18K
12K
9K
8K
6K
port 5 -- initialization is "*111".
port 6 -- initialization is pointed to the lownibble of start address latch.
CLK=4.6 MHz
Initial value : 0***
ACT is the speech acknowledge signal. When the speech synthesizer has voice output, ACT is high. When
ACT is high → low, the speech synthesizer can generate the speech ending interrupt SPI.
Speech start address register (P6 write) :
3
2
1
Port 6
P6L1
A9 A8
A7
0
A6
Initial value : 1111
P6L2
A13 A12 A11 A10
P6L3
A17 A16 A15 A14
P6L4
-
-
-
A18
Send the speech start address to the speech synthesizer by writing P6 four times. There is a pointer counter to
point the address latch (P6L1, P6L2, P6L3, P6L4). It will increase one when write P6. So, the first time
writing P6 to P6L1, the second time is P6L2, the third time is P6L3, the fourth time is P6L4 and the fifth time
is P6L1 latch again, ... etc. The pointer counter point to P6L1 when CPU is reset or P5 is writen.
In the NORMAL operation mode, the speech synthesizer is available. In the other operation modes, it is
disable.
* This specification are subject to be changed without notice.
10.8.2001
26
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE:
inary
m
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P
SP_ADR1
EQU
:
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
; set sample rate & start speech
LDIA
OUTA
; wait speech end
WAIT
TTP
B
1234H
; the start address of the speech section
#SP_ADR1
P6
#SP_ADR1/10H
P6
#SP_ADR1/100H
P6
#SP_ADR1/1000H
P6
#0010B
P5
P5,3
WAIT
; get speech active flag
USING SPEECH ROM AS DATA ROM
The speech ROM can be used for speech synthesizer and for data ROM simutaneously.
First, write initial address to P7 (five times), and after four cycles, you can read P7 to get data, and address
counter increases one automatically.The following read operations must be at an internval of instruction
cycles which are more than 3.
The read operation should be all done before you leave normal mode and change to slow mode.
Get speech ROM data (P7 read) :
3
2
1
0
Port 7
Set speech ROM address (P7 write) :
3
2
1
0
Port 7
P7L1
A3 A2 A1 A0
P7L2
A7 A6 A5 A4
P7L3
P7L4
A11 A10 A9 A8 A15 A14 A13 A12
P7L5
- A18 A17 A16
PROGRAM EXAMPLE:
D_ADR1
EQU
:
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
12345H
; the start address of the speech ROM
#D_ADR1
P7
#D_ADR1/10H
P7
#D_ADR1/100H
P7
#D_ADR1/1000H
P7
#D_ADR1/10000H
P7
* This specification are subject to be changed without notice.
10.8.2001
27
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
NOP
NOP
NOP
NOP
; READ DATA
INA
STA
NOP
4 cycles
P7
TEMP
; read D_ADR1
3 cycles
INA
P7
; read D_ADR1+1
MELODY (SOUND EFFECT) CONTROL
One channel melody/sound effect output, controlled by port 23, 24, 17, and 30.
There is a built-in sound effect. It includes the tone generator and random generator. The tone generator is a
binary down counter and the random generator is a 9-bit liner feedback shift register.
P30
P23,P24
f2
Tone
4 kinds f1 generator
of divider
CLK/8
2
2
Output
control
f2x2
Random
generator
PWM / D/A ckt.
Sound effect command register (P30)
There are 4 kinds of basic frequency for sound generator which can be selected by P30. The output of sound
effect is tone and random combination.
Port30
3
2
BFREQ
1
0
SMODE
Initial value : 0000
BFREQ Basic frequency (f1) select
0 0 CLK/16
0 1 CLK/32
1 0 CLK/64
1 1 Reserved
(CLK=4.6MKz)
SMODE
0 0
0 1
1 0
1 1
Sound generator mode
Disable
Tone output
Random output
Tone+random output
Tone frequency register (P23, P24)
The 8-bit tone frequency register is P24 and P23. The tone frequency will be changed when user output
the different data to P23. Thus, the data must be output to P24 before P23 when users want to change the 8bit tone frequency (TF).
Port24
Port23
3
2
1
0
Higher nibble register
3
2
1
0
Initial value : 1111 1111
Lower nibble register
** f1=CLK/2X, f2=f1/(TF+1)/2, TF=1~255, TF-0
** Example : CLK=4.6 MHz, BFREQ=10, TF=00110001B.
⇒ f1=143.75K Hz, f2=143.75K Hz/50/2=1430 Hz
* This specification are subject to be changed without notice.
10.8.2001
28
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
Random generator
+
f(x)=x9+x4+1
1
2
3
4
5
6
7
8
9
Volume control register (P17)
The are 16 levels of volume for sound generator. P17 is the volume control register.
Port17
Initial value : 1111
3 2
1
0
VCR
VCR
ts/tp
ts
1
1
1
1
15/16
1
1
1
0
14/16
1
tp=
CLK/64
(CLK=4.6MHz)
:
:
tp
0
0
0
1
1/16
0
0
0
0
0/16
PROGRAM EXAMPLE:
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
#1001B
P30
#0111B
P17
#0011B
P24
#0001B
P23
; basic frequency : CLK/32, tone output
; volume control
; 1430 Hz tone output
WATCH-DOG-TIMER (WDT)
Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every
certain time . User can use the time up signal to give system a reset signal when system is fail.
This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU
is reseted or in the STOP operation mode.
The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit .
The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the
counter will be cleared and continue counting . Otherwise, if there is a malfunction happened, the WDT control
will send a WDT signal ( low active ) to reset CPU. The WDT checking period is assign by P21 ( WDT command
port ).
WDT counter
LXIN/213
0
1
2
3
RESET pin
counter clear request
mask option
WDT control
P21
WDT
command port
* This specification are subject to be changed without notice.
10.8.2001
29
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET.
Port 21
3
CWC
2
*
1
*
0
Initial value :0000
WDT
CWC
0
1
Clear watchdog timer counter
Clear counter then return to 1
Nothing
WDT
0
1
Set watch-dog-timer detect time
3 x 213/LXIN = 3 x 213/32K Hz = 0.75 sec
7 x 213/LXIN = 7 x 213/32K Hz = 1.75 sec
PROGRAM EXAMPLE
To enable WDT with 7 x 213/LXIN detection time.
LDIA #0001B
OUTA P21; set WDT detection time and clear WDT counter
:
:
RESETTING FUNCTION
When CPU in normal working condition and RESET pin is held in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state
Program counter
Status flag
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2, 3
Interrupt latch ( IL )
P3, 9, 14, 16, 19, 21, 22, 25, 26, 27, 28, 29, 30
P5
P0, 4, 6, 7, 8, 17, 23, 24
CLK, LXIN
Initial value
0000h
01h
00h
00h
00h
00h
07h
0Fh
Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
10.8.2001
30
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
EM73PA88A I/O PORT DESCRIPTION :
Port
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
E
E
I
I
E
I
Input function
Input port , wakeup function
---Input port
P5.3 : Speech active signal (ACT)
-DATA ROM data
Input port, wakeup function,
external interrupt input
-----CPU status register
--
Output function
I
E
I
I
I
E
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Note
--P3(1..0) : ROM bank selection
Output port
Speech sample rate register
Speech start address register
Data start address register
Output port
P9.3 : RAM bank selection
------STOP mode control register
Sound effect volume control register
-IDLE mode control register
-WDT control register
DUAL/SLOW mode control register
Sound effect frequency register
Sound effect frequency register
Timebase control register
LCD common start address register
LCD control register
Timer/counter A control register
Timer/counter B control register
Sound effect command register
--
* This specification are subject to be changed without notice.
low nibble
high nibble
10.8.2001
31
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
APPLICATION CIRCUIT
100
VBAT
0.1µF
VBAT
0.1µF
VDD
3V
VDD2
P0.0
P0.1
SEG0~
SEG63
COM0~
COM15
LCD PANNEL
VA
P0.2
0.1µF
VB
BZ1
100Ω
BZ2
RESET
0.1µF
V5
V4
V3
V2
V1
LXOUT
all 0.1µF
32.768KHz
LXIN
RESET
20P
VSS
CLK
0.022µF
EM73PA88A
* This specification are subject to be changed without notice.
10.8.2001
32
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
ABSOLUTE MAXIMUM RATINGS
Items
Sym.
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Ratings
V DD
V IN
VO
PD
T OPR
TSTG
Conditions
-0.5V to 6V
-0.5V to VDD+0.5V
-0.5V to VDD+0.5V
300mW
0oC to 50oC
-55oC to 125oC
TOPR=50 oC
RECOMMANDED OPERATING CONDITIONS
Items
Sym.
Supply Voltage
Input Voltage
Operating Frequency
Ratings
VDD
VIH
VIL
FC
Fs
Condition
2.2V to 4.8V
0.90xVDD to VDD
0V to 0.10xVDD
4.6MHz
32KHz
CLK
LXIN,LXOUT
DC ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, TOPR=25oC)
Parameters
Supply current
Hysteresis voltage
Input current
Sym.
I DD
VHYS+
VHYSIIH
I IL
Output voltage
Leakage current
Input resistor
V OH
VOL
ILO
RIN
Min.
Typ.
-
0.5
1.2
mA
-
38
33
12
1
-
25
20
7
0.1
-250
±1
±1
-500
µA
µA
µA
µA
V
V
µA
µA
µA
2.4
-
-
V
2.0
2.4
-
V
100
300
0.15
200
600
0.3
1
300
900
V
µA
KΩ
KΩ
0.50VDD
0.20VDD
Max. Unit
0.75VDD
0.40VDD
* This specification are subject to be changed without notice.
Conditions
VDD=3.3V,no load,DUAL mode,Fs=32KHz,
Fc=4.6MHz
VDD=3.3V,SLOW mode,LCD on
VDD=3.3V,IDLE mode,LCD on
VDD=3.3V,IDLE mode,LCD off
VDD=3.3V, STOP mode
RESET, P0, P8
P0, RESET, VDD=3.3V,VIH=3.3/0V
Open-drain, VDD=3.3V,VIH=3.3/0V
Normal current push-pull,VDD=3.3V,P4(low),
P8
Push-pull, P4(high current PMOS), SOUND,
VDD=2.7V, IOH=-0.9mA
Push-pull, P4(low current PMOS), P8,
VDD=2.7V, IOH=-40µA
VDD=2.7V,IOL=0.9mA, P4, P8
Open-drain, VDD=3.3V, VO=3.3V
P0
RESET
10.8.2001
33
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
DC ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, TOPR=25oC)
Parameters
Output current
of BZ1, BZ2
Output current
of VO
LCD bias voltage
Sym.
Min.
Typ.
Max. Unit
I OH
I OL
-
25
25
2
3
60
60
4
mA
mA
mA
V1
V2
V3
V4
V5
-
0.9
1.8
2.7
3.6
4.5
-
V
V
V
V
V
* This specification are subject to be changed without notice.
Conditions
VDD=3V,VBZ=1.5V,
VDD=3V,VO=0.7V
VDD=3V, LCD on, no load
10.8.2001
34
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
RESET PIN TYPE
TYPE RESET-A
RESET
OSCILLATION PIN TYPE
TYPE OSC-B
TYPE OSC-G
LXIN
Crystal
Osc.
CLK
Internal
Osc.
LXOUT
TYPE OSC-H
RC Osc.
LXIN
INPUT PIN TYPE
TYPE INPUT-A
TYPE INPUT-B
WAKEUP function
mask option
: mask option
* This specification are subject to be changed without notice.
P0/WAKEUP
TYPE INPUT-A
10.8.2001
35
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
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P
I/O PIN TYPE
TYPE I/O
TYPE I/O-L
path B
SEL
path A
Input
data
mask option
Output
data
latch
TYPE I/O
Special function
control input
Output
data
WAKEUP function
mask option
TYPE I/O-N
TYPE I/O-O
path B
Input
data
path A
TYPE I/O-N
: mask option
: mask option
Path A :
Path B :
Output
data
latch
Output
data
Special function
output
For set and clear bit of port instructions, data goes through path A from output data latch to CPU.
For input and test instructions, data from output pin go through path B to CPU and the output data latch
will be set to high.
* This specification are subject to be changed without notice.
10.8.2001
36
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
99
SEG47
100
SEG45
103 102 101
SEG46
SEG44
104
SEG43
105
SEG42
SEG39
107 106
SEG40
108
SEG38
SEG35
109
SEG37
SEG34
1
SEG36
SEG33
PAD DIAGRAM
SEG41
inary
m
i
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P
98
97
96
95
94
93
92
91
90
89
88
87
SEG56
86
SEG57
85
SEG58
84
SEG59
6
83
SEG60
P4.0
7
82
SEG61
P4.1
8
81
SEG62
P4.2
9
80
SEG63
79
COM15
78
COM14
77
COM13
76
COM12
75
COM11
74
COM10
SEG32
2
P8.0/DIN
3
P8.1/DOUT
4
P8.2
P8.3
P4.3
P0.0/ACLK
5
10
11
P0.1/PGM
12
P0.2/OE
13
P0.3/DCLK
VDD2
14
15
BZ1
16
BZ2
17
(0,0)
VSS
18
RESET
19
CLK
20
TEST/VPP
21
EM73PA88A
73
COM9
72
COM8
71
COM7
70
COM6
69
COM5
68
COM4
67
COM3
66
COM2
65
COM1
64
COM0
63
SEG0
62
SEG1
61
SEG2
60
SEG3
59
SEG4
LXIN
22
LXOUT
23
VDD
24
V1
25
V2
26
V3
27
V4
28
V5
29
58
SEG5
30
57
SEG6
SEG7
SEG8
VA
44
45
46
47
48
49
50
51
52
53
54
SEG12
SEG11
SEG10
SEG9
SEG22
43
SEG13
SEG23
42
SEG14
41
SEG15
40
SEG16
39
SEG17
38
SEG18
37
SEG19
36
SEG20
35
SEG21
34
SEG24
33
SEG25
SEG30
SEG26
55
SEG27
32 ELAN
SEG28
SEG31
SEG29
31
56
VB
* This specification are subject to be changed without notice.
10.8.2001
37
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
i
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P
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
SEG33
SEG32
P8.0/DIN
P8.1/DOUT
P8.2
P8.3
P4.0
P4.1
P4.2
P4.3
P0.0/ACLK
P0.1/PGM
P0.2/OE
P0.3/DCLK
VDD2
BZ1
BZ2
VSS
RESET
CLK
TEST/VPP
LXIN
LXOUT
VDD
V1
V2
V3
V4
V5
VA
VB
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
X
-1414.4
-1628.0
-1628.0
-1628.0
-1628.0
-1628.0
-1633.0
-1633.0
-1633.0
-1633.0
-1633.0
-1633.0
-1633.0
-1633.0
-1601.5
-1605.8
-1605.8
-1601.5
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1613.0
-1319.6
-1189.6
-1059.6
-929.6
-799.6
-669.6
-539.6
* This specification are subject to be changed without notice.
Y
2805.6
2655.6
2530.6
2410.5
2290.6
2170.5
2050.6
1930.6
1810.5
1690.6
1570.5
1450.6
1330.6
1210.5
1008.2
780.2
377.3
150.1
-332.9
-503.1
-661.5
-843.1
-1012.9
-1193.0
-1395.3
-1565.5
-1735.3
-1905.5
-2107.8
-2288.5
-2458.3
-2629.1
-2798.8
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
10.8.2001
38
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
i
l
e
r
P
Pad No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG63
X
-409.6
-279.6
-149.6
-19.6
110.4
240.4
370.0
499.9
629.9
759.9
889.9
1020.0
1149.9
1279.9
1618.5
1618.5
1618.5
1618.5
1618.5
1618.5
1618.5
1618.5
1618.5
1618.5
1618.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
* This specification are subject to be changed without notice.
Y
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2816.0
-2609.9
-2479.8
-2349.9
-2219.8
-2089.8
-1959.9
-1829.9
-1699.8
-1569.9
-1439.8
-1309.9
-1035.1
-865.3
-695.0
-526.3
-357.2
-188.5
-19.4
149.2
318.3
487.1
656.2
824.9
993.9
1162.6
1331.8
10.8.2001
39
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
i
l
e
r
P
Pad No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
Symbol
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
X
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1613.5
1442.2
1312.1
1182.1
1052.1
922.1
792.2
662.1
532.1
402.1
272.1
142.2
12.1
-117.9
-247.9
-377.9
-507.9
-637.9
-767.9
-897.9
-1027.9
-1157.9
-1287.9
Y
1500.4
1669.5
1838.2
2007.3
2176.0
2345.1
2513.9
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
2805.6
Unit : µm
Chip Size : 3530 x 5910 µm
Note : For PCB layout, IC substrate must be floated or connected to Vss.
* This specification are subject to be changed without notice.
10.8.2001
40
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INSTRUCTION TABLE
inary
m
i
l
e
r
P
(1) Data Transfer
Mnemonic
LDA
x
LDAM
LDAX
LDAXI
LDH #k
LDHL x
LDIA #k
LDL #k
STA
x
STAM
STAMD
STAMI
STD
#k,y
STDMI #k
THA
TLA
Object code ( binary )
Operation description
Byte
0110 1010 xxxx xxxx
0101 1010
0110 0101
0110 0111
1001 kkkk
0100 1110 xxxx xx00
1101 kkkk
1000 kkkk
0110 1001 xxxx xxxx
0101 1001
0111 1101
0111 1111
0100 1000 kkkk yyyy
1010 kkkk
0111 0110
0111 0100
Acc←RAM[x]
Acc ←RAM[HL]
Acc←ROM[DP]L
Acc←ROM[DP]H,DP+1
HR←k
LR←RAM[x],HR←RAM[x+1]
Acc←k
LR←k
RAM[x]←Acc
RAM[HL]←Acc
RAM[HL]←Acc, LR-1
RAM[HL]←Acc, LR+1
RAM[y]←k
RAM[HL]←k, LR+1
Acc←HR
Acc←LR
2
1
1
1
1
2
1
1
2
1
1
1
2
1
1
1
Object code ( binary )
Operation description
Byte
Cycle
2
1
2
2
1
2
1
1
2
1
1
1
2
1
1
1
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
Flag
Z
Z
Z
S
C'
C'
C
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
S
C'
C'
C'
C'
C'
C'
C'
C
C
C
C'
10.8.2001
41
S
1
1
1
1
1
1
1
1
1
1
C
C'
1
C'
1
1
(2) Rotate
Mnemonic
RLCA
RRCA
0101 0000
0101 0001
←CF←Acc←
→CF→Acc→
1
1
Cycle
1
1
(3)
3) Arithmetic operation
Mnemonic
Object code ( binary )
Operation description
Byte
ADCAM
ADD
#k,y
ADDA #k
ADDAM
ADDH #k
ADDL #k
ADDM #k
DECA
DECL
DECM
INCA
0111
0100
0110
0111
0110
0110
0110
0101
0111
0101
0101
Acc←Acc + RAM[HL] + CF
RAM[y]←RAM[y] +k
Acc←Acc+k
Acc←Acc + RAM[HL]
HR←HR+k
LR←LR+k
RAM[HL]←RAM[HL] +k
Acc←Acc-1
LR←LR-1
RAM[HL]←RAM[HL] -1
Acc←Acc + 1
1
2
2
1
2
2
2
1
1
1
1
0000
1001 kkkk yyyy
1110 0101 kkkk
0001
1110 1001 kkkk
1110 0001 kkkk
1110 1101 kkkk
1100
1100
1101
1110
* This specification are subject to be changed without notice.
Cycle
1
2
2
1
2
2
2
1
1
1
1
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
i
l
e
r
P
INCL
INCM
SUBA #k
SBCAM
SUBM #k
0111 1110
0101 1111
0110 1110 0111 kkkk
0111 0010
0110 1110 1111 kkkk
LR←LR + 1
RAM[HL]←RAM[HL]+1
Acc←k-Acc
Acc←RAM[HLl - Acc - CF'
RAM[HL]←k - RAM[HL]
1
1
2
1
2
1
1
2
1
2
C
-
Z
Z
Z
Z
Z
C'
C'
C
C
C
(4) Logical operation
Object code ( binary )
Operation description
Byte
ANDA #k
ANDAM
ANDM #k
ORA
#k
ORAM
ORM #k
XORAM
0110
0111
0110
0110
0111
0110
0111
Acc←Acc&k
Acc←Acc & RAM[HL]
RAM[HL]←RAM[HL]&k
Acc←Acc k
Acc ←Acc RAM[HL]
RAM[HL]←RAM[HL] k
Acc←Acc^RAM[HL]
2
1
2
2
1
2
1
--
1110 0110 kkkk
1011
1110 1110 kkkk
1110 0100 kkkk
1000
1110 1100 kkkk
1001
----
Mnemonic
Cycle
2
1
2
2
1
2
1
Flag
C
Z
Z
Z
Z
Z
Z
Z
Z
S
Z'
Z'
Z'
Z'
Z'
Z'
Z'
(5) Exchange
Mnemonic
Object code ( binary )
Operation description
Byte
EXA x
EXAH
EXAL
EXAM
EXHL x
0110 1000 xxxx xxxx
0110 0110
0110 0100
0101 1000
0100 1100 xxxx xx00
Acc↔RAM[x]
Acc↔HR
Acc↔LR
Acc↔RAM[HL]
LR↔RAM[x],
HR↔RAM[x+1]
2
1
1
1
2
Cycle
Flag
C
Z
S
2
2
2
1
-
Z
Z
Z
Z
1
1
1
1
2
-
-
1
Flag
C
Z
S
(6) Branch
Mnemonic
Object code ( binary )
Operation description
Byte
Cycle
SBR a
00aa aaaa
1
1
-
-
1
LBR a
SLBR a
1100 aaaa aaaa aaaa
0101 0101 1100 aaaa
If SF=1 then PC←PC12-6.a5-0
else null
If SF= 1 then PC←a else null
If SF=1 then PC←a else null
2
3
2
3
-
-
1
1
Operation description
Byte
k-RAM[y]
RAM[x]-Acc
2
2
aaaa aaaa (a:1000~1FFFh)
0101 0111 1100 aaaa
aaaa aaaa (a:0000~0FFFh)
(7) Compare
Mnemonic
Object code ( binary )
CMP #k,y 0100 1011 kkkk yyyy
CMPA x
0110 1011 xxxx xxxx
* This specification are subject to be changed without notice.
Cycle
2
2
Flag
C
Z
S
C
C
Z'
Z'
Z
Z
10.8.2001
42
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary
m
i
l
e
r
P
Mnemonic
CMPAM
CMPH #k
CMPIA #k
CMPL #k
Object code ( binary )
0111 0011
0110 1110 1011 kkkk
1011 kkkk
0110 1110 0011 kkkk
Operation description
Byte
RAM[HL] - Acc
k - HR
k - Acc
k-LR
1
2
1
2
Operation description
Byte
Cycle
1
2
1
2
C
Flag
Z
S
C
C
-
Z
Z
Z
Z
Z'
C
Z'
C
(8) Bit manipulation
Mnemonic
Object code ( binary )
Cycle
C
-
Flag
Z
-
S
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
S
-
1111 00bb
0110 1101 11bb pppp
0110 0000
0110 1100 11bb yyyy
1111 01bb
0110 1101 01bb pppp
0110 0010
0110 1100 01bb yyyy
0110 1100 00bb yyyy
1111 10bb
1111 11bb
0110 1101 00bb pppp
0110 0001
0110 1100 10bb yyyy
0110 1101 10bb pppp
RAM[HL]b←0
PORT[p]b←0
PORT[LR3-2+4]LR1-0←0
RAM[y]b←0
RAM[HL]b←1
PORT[p]b←1
PORT[LR3-2+4]LRl-0←1
RAM[y]b←1
SF←RAM[y]b'
SF←Accb'
SF←RAM[HL]b'
SF←PORT[p]b'
SF←PORT[LR 3-2 +4]LR1-0'
SF←RAM[y]b
SF←PORT[p]b
1
2
1
2
1
2
1
2
2
1
1
2
1
2
2
Mnemonic
Object code ( binary )
Operation description
Byte
LCALL a
0100 0aaa aaaa aaaa
2
2
SCALL a
1110 nnnn
1
2
-
-
-
RET
0100 1111
STACK[SP]←PC,
SP←SP -1, PC←a
STACK[SP]←PC,
SP←SP - 1, PC←a, a = 8n + 6
(n =1∼15),0086h (n = 0)
SP←SP + 1, PC←STACK[SP]
Flag
C
Z
-
1
2
-
-
-
Object code ( binary )
Operation description
Byte
CLM
CLP
CLPL
CLR
SEM
SEP
SEPL
SET
TF
TFA
TFM
TFP
TFPL
TT
TTP
b
p,b
y,b
b
p,b
y,b
y,b
b
b
p,b
y,b
p,b
1
2
2
2
1
2
2
2
2
1
1
2
2
2
2
(9) Subroutine
Cycle
(10) Input/output
Mnemonic
INA
INM
OUT
OUTA
OUTM
p
p
#k,p
p
p
0110 1111 0100 pppp
0110 1111 1100 pppp
0100 1010 kkkk pppp
0110 1111 000p pppp
0110 1111 100p pppp
Acc←PORT[p]
RAM[HL]←PORT[p]
PORT[p]←k
PORT[p]←Acc
PORT[p]←RAM[HL]
* This specification are subject to be changed without notice.
2
2
2
2
2
Cycle
2
2
2
2
2
Flag
Z
Z
-
S
Z'
Z'
1
1
1
10.8.2001
43
C
-
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
(11) Flag manipulation
inary
m
i
l
e
r
P
Mnemonic
Object code ( binary )
Operation description
Byte
Cycle
TFCFC
TTCFS
TZS
0101 0011
0101 0010
0101 1011
SF←CF', CF←0
SF←CF, CF←1
SF←ZF
1
1
1
1
1
1
Operation description
Byte
Flag
C
0
1
-
Z
-
S
*
*
*
(12) Interrupt control
Mnemonic
CIL
r
DICIL r
EICIL r
EXAE
RTI
Object code ( binary )
0110 0011 11rr rrrr
0110 0011 10rr rrrr
0110 0011 01rr rrrr
0111 0101
0100 1101
IL←IL & r
EIF←0,IL←IL&r
EIF←1,IL←IL&r
MASK↔Acc
SP←SP+1,FLAG.PC
←STACK[SP],EIF ←1
2
2
2
1
1
Object code ( binary )
Operation description
Byte
Cycle
2
2
2
1
2
Flag
Z
*
S
1
1
1
1
*
Flag
C
Z
-
S
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
*
(13) CPU control
Mnemonic
NOP
0101 0110
no operation
1
Cycle
1
(14) Timer/Counter & Data pointer & Stack pointer control
Mnemonic
LDADPL
LDADPM
LDADPH
LDASP
LDATAL
LDATAM
LDATAH
LDATBL
LDATBM
LDATBH
STADPL
STADPM
STADPH
STASP
STATAL
STATAM
STATAH
STATBL
STATBM
STATBH
Object code ( binary )
0110 1010 1111 1100
0110 1010 1111 1101
0110 1010 1111 1110
0110 1010 1111 1111
0110 1010 1111 0100
0110 1010 1111 0101
0110 1010 1111 0110
0110 1010 1111 1000
0110 1010 1111 1001
0110 1010 1111 1010
0110 1001 1111 1100
0110 1001 1111 1101
0110 1001 1111 1110
0110 1001 1111 1111
0110 1001 1111 0100
0110 1001 1111 0101
0110 1001 1111 0110
0110 1001 1111 1000
0110 1001 1111 1001
0110 1001 1111 1010
Operation description
Acc←[DP]L
Acc←[DP]M
Acc←[DP]H
Acc←SP
Acc←[TA]L
Acc←[TA]M
Acc←[TA]H
Acc←[TB]L
Acc←[TB]M
Acc←[TB]H
[DP]L←Acc
[DP]M←Acc
[DP]H←Acc
SP←Acc
[TA]L←Acc
[TA]M←Acc
[TA]H←Acc
[ TB]L←Acc
[TB]M←Acc
[TB]H←Acc
* This specification are subject to be changed without notice.
Byte
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C
-
10.8.2001
44
EM73PA88A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
**** SYMBOL DESCRIPTION
Symbol
HR
PC
SP
ACC
CF
SF
IL
PORT[p]
ΤΒ
RAM[x]
ROM[DP]H
[DP]M
[TA]L([TB]L)
[TA]H([TB]H)
LR3-2
PC12-6
↔
--
#k
y
b
inary
m
i
l
e
r
P
Description
Symbol
H register
Program counter
Stack pointer
Accumulator
Carry flag
Status flag
Interrupt latch
Port ( address : p )
Timer/counter B
Data memory (address : x )
High 4-bit of program memory
Middle 4-bit of data pointer register
Low 4-bit of timer/counter A
(timer/counter B) register
High 4-bit of timer/counter A
(timer/counter B) register
Bit 3 to 2 of LR
LR
DP
STACK[SP]
FLAG
ZF
EI
MASK
ΤΑ
RAM[HL]
ROM[DP]L
[DP]L
[DP]H
[TA]M([TB]M)
Bit 12 to 6 of program counter
Exchange
Substraction
Logic OR
Inverse operation
4-bit immediate data
4-bit zero-page address
Bit address
←
+
&
^
.
x
p
r
LR 1-0
a5-0
* This specification are subject to be changed without notice.
Description
L register
Data pointer
Stack specified by SP
All flags
Zero flag
Enable interrupt register
Interrupt mask
Timer/counter A
Data memory (address : HL )
Low 4-bit of program memory
Low 4-bit of data pointer register
High 4-bit of data pointer register
Middle 4-bit of timer/counter A
(timer/counter B) register
Contents of bit assigned by bit
1 to 0 of LR
Bit 5 to 0 of destination address for
branch instruction
Transfer
Addition
Logic AND
Logic XOR
Concatenation
8-bit RAM address
4-bit or 5-bit port address
6-bit interrupt latch
10.8.2001
45