PF754-03 SCI7654M0A/C0A DC/DC Converter Double/Triple/Quadruple Boosting 95% Excellent Power Conversion Efficiency Built-in Voltage Regulator DESCRIPTION The SCI7654 is a highly efficient, but low power-consumption DC-to-DC converter based on the advanced CMOS technologies. It can generate an output voltage double/triple/quadruple times higher than the input (in negative direction) if 4/3/2 external capacitors are attached. With a built-in voltage regulator, the SCI7654 can provide a stable output by setting the DC/DC output to any voltage via two external resistors. This is optimum to the LCD panel power supply as the stable output can have the negative temperature gradient required for an LCD panel. FEATURES An input voltage can be boosted double/triple/quadruple to negative potential. Input voltages: –2.4 to –5.5V (quadruple boosting), –2.4 to –7.3V (triple boosting), –2.4 to –11.0V (double boosting) Excellent vol tage conversion efficiency: 95% (Typ.) Large output current: 20 mA (Max.) during quadruple boosting Built-in voltage regulator (for stable voltage output) Built-in reference voltage source for accurate regulation: –1.5 ±0.05V (CT0) Regulator output voltage temperature gradient function: –0.04, –0.15, –0.35, –0.55%/˚C Low current consumption: 130 µA (Typ.) Low standby current: 5.0 µA (Max.) Built-in oscillator circuit 5/6-time voltage boosting in negative potential by serial connection Package: SCI7654M0A SSOP2-16pin (plastic), SCI7654C0A DIP-16pin (plastic) BLOCK DIAGRAM VDD POFF1 POFF2 FC Ref. Voltage Circuit Power-Off Control Clock Generator TC1 TC2 RV Booster Control Voltage Regulator VREG VRI Voltage Converter VIN C1P C1N C3N C2P VOUT C2N SCI7654M0A/C0A PIN CONFIGURATION SSOP2-16pin/DIP-16pin VOUT 1 16 C2P VRI 2 15 C2N VREG 3 14 C3N RV 4 13 C1N VDD 5 12 C1P FC 6 11 VIN TC1 7 10 POFF1 TC2 8 9 POFF2 PIN DESCRIPTION Pin No. Pin Name Function 1 VOUT Voltage output 2 VRI Regulator input 3 VREG 4 RV Input for regulator output voltage adjustment 5 VDD Input voltage pin (Positive) 6 FC Internal clock rate switch input, and clock input in serial/parallel Regulator output connection (Common input pin) 2 7 TC1 Input for regulator output temperature gradient setup (1) 8 TC2 Input for regulator output temperature gradient setup (2) 9 POFF2 Power-off control input (2) 10 POFF1 Power-off control input (1) 11 VIN Input voltage pin (Negative) 12 C1P Common double and quadruple boosting capacitor positive pin 13 C1N Double boosting capacitor negative pin 14 C3N Quadruple boosting capacitor negative pin 15 C2N Triple boosting capacitor negative pin 16 C2P Triple boosting capacitor positive pin SCI7654M0A/C0A ABSOLUTE MAXIMUM RATINGS Input Power Voltage Rating Symbol VIN Min. -26.0/N Max. VDD +0.3 Unit V Input Pin Voltage VI VIN -0.3 VDD +0.3 V VIN -0.3 Remark N=Boosting time; at VIN pin Output Pin Voltage 1 V0C1 VDD +0.3 V POFF1, POFF2 TC1, TC2, FC pins At C1P and C2P pins Output Pin Voltage 2 Output Pin Voltage 3 Output Pin Voltage 4 VOC2 VOC3 VOC4 2 3 4 VIN -0.3 VIN -0.3 VIN -0.3 VIN +0.3 2 VIN +0.3 3 VIN +0.3 V V V At C1N pin At C2N pin At C3N pin Regulator Input Power Voltage Regulator Input Pin Voltage Output Voltage VRI VRV V0 N N VIN -0.3 VIN -0.3 VDD +0.3 VDD +0.3 V V N=Boosting time; at VRI pin N=Boosting time; at RV pin N VIN -0.3 VDD +0.3 V Input Current Output Current IIN IOUT — — N=Boosting time; at VOUT and VREG pins At VIN pin N=Boosting time; at VOUT and VREG pins Allowable Loss Operating Temperature Storage Temperature Soldering Temperature and Time Pd Topr Tstg Tsol — -30 -55 — 80 N≤4: 20 N>4: 80/N mA mA 210 85 150 260•10 mW ˚C ˚C ˚C.S — — — Temperature at leads ELECTRICAL CHARACTERISTICS (Unless otherwise designated: Ta=–30°V to +85°C, VDD=0V, VIN=–5.0V) Characteristic Input Power Voltage 1 Symbol VIN1 Input Power Voltage 2 Input Power Voltage 3 Input Power Voltage N VIN2 VIN3 VINN Boost Startup Input Power Voltage VSTA Booster Output Voltage VOUT Regulator Input Voltage Regulator Output Voltage VRI VREG Booster Output Impedance ROUT Booster Power Conversion Efficiency Peff Booster Operating Current Consumption 1 IOPR1 Booster Operating Current Consumption 2 IOPR2 Regulator Operating Current Consumption IOPVR Condition During quadruple boosting Min. -5.5 Typ. — Max. -2.4 Unit V During triple boosting During double boosting During large-time boosting using -7.3 -11 -22/N — — -2.4 -2.4 -2.4 V V V -22/N — -2.4 V -22 — — V -22 — — — -2.4 -2.4 V V — 200 300 — 95 — % — 130 220 A — 520 880 A — 10 15 A external diodes N=Boosting time, IOUT<200 FC=VDD — A, — IREG=0, VRI=-22V, RRV=1MΩ IOUT=10mA, during quadruple boosting IOUT=2 mA; during quadruple boosting; C1, C2, C3, COUT=10 F Tantalum FC=VDD, POFF1=VIN, POFF2=VDD; during no loading; C1, C2, C3, COUT=10 F Tantalum FC=VIN, POFF1=VIN, POFF2=VDD; during no loading; C1, C2, C3, COUT=10 F Tantalum VRI=-20 V, during no loading, RRV=1 M 3 SCI7654M0A/C0A ELECTRICAL CHARACTERISTICS (continued) Characteristic Static Current Symbol IQ Input Leakage Current Stable Output Saturation Resistance ILIN RSAT (*1) Stable Output Voltage Stability DVR (*2) Stable Output Load Variation Reference Voltage (Ta = 25°C) Reference Voltage Temperature Coefficient (*4) (*5) Input Voltage Level (*1) RSAT = At POFF1, POFF2, FC, TC1, TC2 pins 0<IREG<20mA RV=VDD Ta=25˚C -20V<VRI<-10V, IREG=1mA Min. — Typ. — Max. 5.0 Unit A — — — 10 0.5 20 A — 0.2 — %/V VREG=-15V — 30 50 mV VREF0 VREF1 Ta=25˚C VRI=-20V VREG=-15V Ta=25˚C 0<IREG<20mA TC1 = VDD, TC2 = VDD TC1 = VDD, TC2 = VIN -1.55 -1.70 -1.50 -1.50 -1.45 -1.30 V V VREF2 VREF3 TC1 = VIN, TC2 = VDD TC1 = VIN, TC2 = VIN -1.90 -2.15 -1.50 -1.50 -1.10 -0.85 V V CT0 CT1 CT2 TC1 = VDD, TC2 = VDD, SSO package TC1 = VDD, TC2 = VIN, SSO package TC1 = VIN, TC2 = VDD, SSO package -0.07 -0.25 -0.45 -0.04 -0.15 -0.35 0 -0.07 -0.20 %/˚C %/˚C %/˚C CT3 VIH TC1 = VIN, TC2 = VIN, SSO package VIN =-2.0V to -5.5V At POFF1, POFF2, FC, TC1, TC2 pins -0.75 -0.55 -0.30 %/˚C 0.2VIN — — V — — 0.8VIN V — — 47 µF DV0 (*3) VIL Capacitance of Booster Capacitors Condition POFF1=VIN, POFF2=VIN, FC=VDD CMAX VIN =-2.0V to -5.5V At POFF1, POFF2, FC, TC1, TC2 pins Capacitors C1, C2, C3 (VREG – VOUT) IREG VREG VOUT•VREG (*2) VR = (*3) R0 = VREG IREG (*4) CT = |VREF(50˚C)| – |VREF(0˚C)| 50˚C – 0˚C 100 |VREF(25˚C)| (*5) The reference voltage temperature coefficient of each chip product may vary depending on the used molding materials. Perform the temperature test before use. 4 SCI7654M0A/C0A FUNCTIONAL DESCRIPTION Clock Generator Circuit As the SCI7654 has a built-in clock generator circuit, it requires no external source at all. The clock rate changes depending on the FC pin signal level, and the Low Output or High Output mode can be selected. This allows a frequency selection according to the current capacitance and load current when the booster output impedance changes depending on the clock rate and external booster capacitance. FC pin Mode Clock Rate Current Consumption Output Ripple H (VDD) Low Output 4.0 kHz (Typ.) IOP VRP L (VIN) High Output 16.0 kHz (Typ.) Approx. 4 times of IOP Approx. 1/4 time of VRI Voltage Converter Circuit The voltage converter receives a clock from the clock generator, and boosts the VIN input power voltage quadruple, triple or double. Four converter circuits are required for quadruple boosting, three converts are required for triple boosting, and dual converters are required for double boosting. VDD (0V) VIN (-5V) 10V -10V double boosting 15V -15V triple boosting 20V -20V quadruple boosting Voltage step-up diagram (during -5V input) Reference Voltage Circuit The SCI7654 has a built-in reference voltage circuit for the voltage regulator. The temperature coefficient of reference voltage can be changed using pins TC1 and TC2, and a voltage having one of four types of temperature gradients can be output at VREG pin for LCD driving. Reference Voltage, VREF (V) Temperature Coefficient, CT (%/˚C) TC1 TC2 CT0 H(VDD) H(VDD) -1.55 -1.5 -1.45 -0.07 -0.04 0 CT1 H L(VIN) -1.70 -1.5 -1.30 -0.25 -0.15 -0.07 CT2 L(VIN) H -1.90 -1.5 -1.10 -0.45 -0.35 -0.20 CT3 L L -2.15 -1.5 -0.85 -0.75 -0.55 -0.30 Mode Min. Typ. Max. Min. Typ. Max. 5 SCI7654M0A/C0A Voltage Regulator Circuit The circuit receives a voltage from VRI pin, stabilizes it, and outputs at any voltage. The output is adjustable with a ratio of R1 and R2 external divider resistors. Although the sum of divider resistors is desirable to be minimum to prevent an interference due to external noise, 100 to 1 megohms are recommended as the current consumption may be increased by the divider resistors. R1 R2 1 VOUT 2 VRI 3 VREG 4 RV 5 VDD 6 FC 7 TC1 8 TC2 C2P 16 C2N 15 C3N 14 C1N 13 C1P 12 VIN 11 POFF1 10 POFF2 9 Power Off Control The SCI7654 has an automatic power-off function, and can turn on or off each function depending on the external signals entered in POFF1 and POFF2 pins. Function Status POFF1 POFF2 PS1 H(VDD) L(VIN) ON ON ON All circuits are turned ON. PS2 L L OFF OFF (*1) OFF (*2) All circuits are turned OFF. PS3 H H OFF ON ON Mode Oscillator Booster Regulator Description Slave side (booster and regulator) in parallel connection Master side (for booster only) PS4 L H ON ON OFF in parallel connection; first stage in serial connection (*3) *1 When the booster circuit is OFF, approximately VIN +0.6V voltage appears at VOUT pin. *2 When the regulator is OFF, the VREG pin is set to the high-impedance status. *3 The mode selected depends on the line connection at the second stage of serial connection. 6 SCI7654M0A/C0A REFERENCE CIRCUIT EXAMPLE Four-time booster circuit This example drives the booster circuit only, boosts the VIN input voltage four times in negative direction, and outputs it at the VOUT pin. However, this does not have a voltage regulator and the voltage at VOUT pin may have a ripple. COUT + VOUT VDD + CIN 1 VOUT C2P 16 + 2 VRI C2N 15 C2 3 VREG C3N 14 4 RV C1N 13 5 VDD C1P 12 6 FC VIN 11 7 TC1 POFF1 10 8 TC2 POFF2 9 C3 + C1 + VIN Four-time booster and regulator circuits This example receives a boost output from VOUT pin, stabilizes it via the voltage regulator circuit, and outputs a voltage having the temperature gradient at VREG pin via the temperature gradient selector circuit. COUT + VREG CREG R1 + R2 VDD 1 VOUT C2P 16 + 2 VRI C2N 15 C2 3 VREG C3N 14 4 RV C1N 13 5 VDD C1P 12 6 FC + CIN C3 + C1 + VIN 11 7 TC1 POFF1 10 8 TC2 POFF2 9 VIN 7 SCI7654M0A/C0A PACKAGE DIMENSIONS Plastic SSOP2-16pin 7max (0.275max) ±0.2 6.6+0.007 (0.26 –0.008 ) 6.2±0.3 4.4±0.2 +0.008 INDEX (0.244±0.011) 9 (0.173 –0.007 ) 16 1.7max (0.066max) 8 1.5±0.1 1 (0.059±0.003) 0° 10° 0.15±0.05 +0.003 ±0.1 0.36+0.004 (0.014 –0.003 ) 0.05 0.8 (0.031) (0.002) (0.006 –0.002 ) ±0.2 0.5+0.007 (0.02 –0.008 ) 0.9 (0.035) Unit : mm (inch) 8 SCI7654M0A/C0A Plastic DIP-16pin 19.7max (0.775max) 19±0.1 (0.748±0.003) 9 6.3±0.1 (0.248±0.003) 16 1 8 0.8±0.1 +0.004 (0.031 –0.003 ) 4.4±0.1 +0.004 (0.119min) (0.173 –0.003 ) 1.5 (0.059) 3min +0.03 .01 2.54 (0.1) ±0.1 0.46+0.004 (0.018 –0.003 ) 0° 15° 7.62 0.25 –0 +0.001 ) (0.01 –0 (0.3) Unit : mm (inch) 9 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 2000 All right reserved. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group ■ EPSON Electronic Devices Website http://www.epson.co.jp/device/ ED International Marketing Department I (Europe & U.S.A.) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : +81-(0)42-587-5812 FAX : +81-(0)42-587-5564 ED International Marketing Department II (Asia) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : +81-(0)42-587-5814 FAX : +81-(0)42-587-5110 First issue June, 1995 Printed February, 2000 in Japan T