ERICSSON PBL386102QNT

February 1999
PBL 386 10/2
Subscriber Line
Interface Circuit
Description
Key Features
The PBL 386 10/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in PBX, Terminal adapters and other telecommunications equipment.
The PBL 386 10/2 has been optimized for low total line interface cost and a high
degree of flexibility in different applications.
The PBL 386 10/2 emulates a transformer equivalent dc-feed, programmable
between 2x25 Ω and 2x900 Ω, with short loop current limiting adjustable to max
65 mA.
A second lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions. The
PBL 386 10/2 is compatible with loop start signalling.
Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
line terminating impedance could be complex or real to fit every market.
Longitudinal line voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 10/2 package is 28-pin PLCC.
• Selectable overhead voltage principle
– All adaptive: The overhead voltage
follows 0.6 VPeak < signals < 5 VPeak.
– Semi adaptive: The overhead voltage
follows 2.5 VPeak < signals < 5 VPeak.
• Metering 1.6Vrms
• High and low battery with automatic
switching
• Battery supply as low as -10V
• Only +5V in addition to GND
and battery (VEE optional)
• 35 mW on-hook power dissipation in
active state
• Long loop battery feed tracks VBat for
maximum line voltage
• 44V open loop voltage @ -48 V battery
feed
• Constant loop voltage for line
leakage <5 mA
• On-hook transmission
• Full longitudinal current capability
during on-hook
Ring Relay
Driver
RRLY
DT
Ring Trip
Comparator
DR
TIPX
Ground Key
Detector
RINGX
C1
• Ground key detector
C2
• Analog temperature guard
C3
• Integrated Ring Relay Driver
VCC
DET
TS
Two-wire
Interface
Line Feed
Controller
and
Longitudinal
Signal
Suppression
PSG
LP
REF
PLC
AOV
VBAT2
Off-hook
Detector
PLD
38 PB
6 L
10
/2
HP
VEE
Input
Decoder and
Control
• Programmable loop & ring-trip detector
threshold
AGND
VBAT
VTX
BGND
VF Signal
Transmission
RSN
VEE
Figure 1. Block diagram.
28-pin plastic PLCC
1
PBL 386 10/2
Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature, Humidity
Storage temperature range
Operating temperature range
Operating junction temperature range, Note 1
TStg
TAmb
TJ
-55
-40
-40
+150
+110
+140
°C
°C
°C
Power supply, 0°C ≤ TAmb ≤ +70°C
VCC with respect to AGND
VEE with respect to AGND
VBat with respect to BGND, continuous
VBat with respect to BGND, 10 ms
VBat2 with respect to A/BGND
VCC
VEE
VBat
VBat
VBat2
-0.4
VBat
-75
-80
VBat
6.5
0.4
0.4
0.4
0.4
V
V
V
V
V
Power dissipation
Continuous power dissipation at TAmb ≤ +70 °C
PD
1.5
W
VCC
V
BGND +13
75 mA
V
Ground
Voltage between AGND and BGND
Relay Driver
Ring relay supply voltage
Ring relay current
VG
-5
Ring trip comparator
Input voltage
Input current
VDT, VDR
IDT, IDR
VBat
-5
VCC
5
V
mA
Digital inputs, outputs (C1, C2, C3, DET)
Input voltage
VID
-0.4
VCC
V
Output voltage (DET not active)
VOD
-0.4
Output current (DET)
IOD
TIPX and RINGX terminals, 0°C < TAmb < +70°C, VBat = -50 V
TIPX or RINGX current
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2
TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2
TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2
TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3
ITIPX, IRINGX
VTA, VRA
VTA, VRA
VTA, VRA
VTA, VRA
Parameter
Ambient temperature
VCC with respect to AGND
VEE with respect to AGND
VBat with respect to BGND
VBat2 with respect to BGND
VCC
V
30
mA
-110
VBat
VBat - 20
VBat - 40
VBat - 70
+110
2
5
10
15
mA
V
V
V
V
Symbol
Min
Max
Unit
TAmb
VCC
VEE
VBat
VBat2
0
4.75
VBat
-58
VBat
+70
5.25
-4.75
-10
-10
°C
V
V
V
V
Recommended Operating Condition
Notes
2
1.
The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability.
2.
A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V.
A pulse ≤1µs is increased to the greater of |-70V| and |VBat -40V|.
3.
RF1 and RF2 ≥ 20 Ω are also required. Pulse is supplied to TIP and RING outside RF1 and RF2.
PBL 386 10/2
Electrical Characteristics
0 °C ≤ TAmb ≤ +70 °C, VCC = +5V ±5 %, VEE = -5V ± 5%, VBat = -58V to -40V, RLC=18.7kΩ, (IL = 27 mA), ZL = 600 Ω, RLD = 50 kΩ,
RF1, RF2 = 0 Ω, RRef = 15kΩ, CHP = 68nF, CLP=0.33 µF, RT = 120 kΩ, RSG = 24 kΩ, RRX = 120 kΩ, AOV- and VBat2-pin not connected,
unless otherwise specified. Current definition: current is positive if flowing into a pin.
Parameter
Ref
fig
Conditions
Min
Typ
Max
Unit
Two-wire port
Overload level, VTRO
Off-Hook, ILDC ≥ 10 mA
On-Hook, ILDC ≤ 5 mA
Input impedance, ZTR
Longitudinal impedance, ZLoT, ZLoR
Longitudinal current limit, ILoT, ILoR
Longitudinal to metallic balance, BLM
2
Active state
1% THD, Note 1
2.5
1.4
Note 2
0 < f < 100 Hz
active state
12
IEEE standard 455-1985,ZTRX = 736 Ω
0.2 kHz < f < 1.0 kHz
53
1.0 kHz < f < 3.4 kHz
53
Longitudinal to metallic balance, BLME
E
BLME = 20 • Log Lo
VTR
3
Longitudinal to four-wire balance, BLFE
ELo
BLFE = 20 • Log
VTX
3
Metallic to longitudinal balance, BMLE
VTR
BMLE = 20 • Log
VLo
4
Ω/wire
mArms /wire
53
53
70
70
dB
dB
0.2 kHz ≤ f ≤ 1.0 kHz
1.0 kHz < f < 3.4 kHz
59
59
70
70
dB
dB
active state
0.2 kHz < f < 3.4 kHz
40
58
dB
active state
0.2 kHz ≤ f ≤ 1.0 kHz
1.0 kHz < f < 3.4 kHz
active state
C
RL
TIPX
VTRO
ILDC
VTX
PBL 386 10/2
RINGX
RT
E RX
RSN
RRX
RT = 120 kΩ, RRX = 120 kΩ
<< 150 Ω, RLR = RLT = RL /2= 300Ω
35
dB
dB
1 << R , R = 600 Ω
L
L
ωC
1
ωC
ZT/200
20
70
70
Figure 2. Overload level, VTRO, two-wire
port
Figure 3. Longitudinal to metallic (BLME)
and Longitudinal to four-wire (BLFE)
balance
VPeak
VPeak
TIPX
ELo
C
VTX
RLT
V TR
PBL 386 10/2
RT
V TX
RLR
RINGX
RSN
RRX
RT = 120 kΩ, RRX = 120 kΩ
3
PBL 386 10/2
Parameter
Ref
fig
Conditions
Four-wire to longitudinal balance, BFLE
4
active state
ERX
VLo
0.2 kHz < f < 3.4 kHz
|ZTR + ZL|
r = 20 • Log
|ZTR - ZL|
0.2 kHz < f < 0.5 kHz
0.5 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz, Note 3
active, IL = 0
active, IL = 0
active, IL = 0
Min
Typ
40
58
Max
Unit
BFLE = 20 • Log
Two-wire return loss, r
TIPX idle voltage, VTi
RINGX idle voltage, VRi
|VTR|
Four-wire transmit port (VTX)
Overload level, VTXO
Off-hook, ILDC ≥ 10 mA
On-hook, ILDC ≤ 5 mA
Output offset voltage, ∆VTX
Output impedance, zTX
Load impedance > 20 kΩ,
1% THD, Note 4
Frequency response
Two-wire to four-wire, g2-4
6
TIPX
VLo
dB
dB
dB
V
V
V
- 1.2
VBat + 2.4
|VBat +4.5| |VBat +3.6|
60
20
VPeak
VPeak
mV
Ω
5
IRSN = 0 mA
0.2 kHz < f < 3.4 kHz
0.3 kHz < f < 3.4 kHz
GND +25
10
50
mV
Ω
400
ratio
relative to 0 dBm, 1.0 kHz. ERX = 0 V
0.3 kHz < f < 3.4 kHz
f = 8.0 kHz, 12 kHz, 16 kHz
-0.15
-0.5
-0.1
0.15
0
dB
dB
Figure 4. Metallic to longitudinal and
four-wire to longitudinal balance
VTX
RT
PBL 386 10/2
E RX
RLR
RINGX
1.25
0.7
-60
0.2 kHz < f < 3.4 kHz
RLT
V TR
25
27
23
5
Four-wire receive port (RSN)
Receive summing node (RSN) dc voltage
Receive summing node (RSN) impedance
Receive summing node (RSN)
current (IRSN) to metallic loop current (IL)
gain,αRSN
C
dB
1
<< 150 Ω, RLT = RLR = RL /2 =300Ω
ωC
RT = 120 kΩ, RRX = 120 kΩ
RSN
RRX
C
TIPX
Figure 5. Overload level, VTXO, four-wire
transmit port
VTX
RL
ILDC
EL
PBL 386 10/2
RINGX
RT
1
<< RL, RL = 600 Ω
ωC
RT = 120 kΩ, RRX = 120 kΩ
RSN
RRX
4
VTXO
PBL 386 10/2
Parameter
Ref
fig
Four-wire to two-wire, g4-2
6
Four-wire to four-wire, g4-4
6
Four-wire to two-wire, G4-2
6
Four-wire to two-wire RLDC ≤ 2 kΩ
relative to 0 dBm, 1.0 kHz. EL = 0 V
0.3 kHz < f < 3.4 kHz
f = 8 kHz, 12 kHz,
16 kHz
relative to 0 dBm, 1.0 kHz. EL = 0 V
0.3 kHz < f < 3.4 kHz
6
Insertion loss
Two-wire to four-wire, G2-4
Gain tracking
Two-wire to four-wire RLDC ≤ 2 kΩ
Conditions
0 dBm, 1.0 kHz, Note 5
VTX
G2-4 = 20 • Log
,ERX = 0
VTR
0 dBm, 1.0 kHz, Notes 5, 6
VTR
G4-2 = 20 • Log
,EL = 0
ERX
6
Noise
Idle channel noise at two-wire
(TIPX-RINGX)
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
Typ
Max
Unit
-0.15
-1.0
-1.0
-0.2
-0.3
0.15
0
0
dB
dB
dB
0.15
dB
-5.82
dB
-0.2
0.2
dB
-0.1
-0.2
0.1
0.2
dB
dB
-0.1
-0.2
0.1
0.2
dB
dB
12
-78
dBrnC
dBmp
-50
-50
dB
dB
-0.15
-6.22
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +3 dBm
-55 dBm to -40 dBm
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +3 dBm
-55 dBm to -40 dBm
6
Min
C-message weighting
Psophometrical weighting
Note 8
6
0 dBm, 1.0 kHz test signal
0.3 kHz < f < 3.4 kHz
12
ILProg =
-6.02
7
-85
Battery feed characteristics
Constant loop current, ILConst
500
RLC
18 < ILProg < 65 mA
Figure 6.
Frequency response, insertion loss,
gain tracking.
0.92 ILProg ILProg
C
TIPX
1.08 ILProg mA
VTX
RL
VTR
1
<< RL, RL = 600 Ω
ωC
EL
RT = 120 kΩ, RRX = 120 kΩ
ILDC
PBL 386 10/2
RINGX
RT
E RX
VTX
RSN
RRX
5
PBL 386 10/2
Parameter
Ref
fig
Min
Typ
Max
Unit
0.9•ILTh
ILTh
1.1•ILTh
mA
Ground key detector
Ground key detector threshold
ILTIPX and ILRINGX current difference to trigger ground key det.
11
15
19
mA
Ring trip comparator
Offset voltage, ∆VDTDR
Input bias current, IB
Input common mode range, VDT, VDR
-20
-50
VBat +1
0
-20
20
-1
mV
nA
V
0.5
100
V
µA
0.5
VCC
200
200
V
V
µA
µA
Loop current detector
Programmable threshold, IDET
ILTh > 10 mA
Ring relay driver
Saturation voltage, VOL
Off state leakage current, ILk
Digital inputs (C1, C2, C3)
Input low voltage, VIL
Input high voltage, VIH
Input low current, |IIL|
Input high current, IIH
Detector output (DET)
Output low voltage, VOL
Internal pull-up resistor to VCC
Power dissipation (VBat = -48V, VBat2 = -32V)
P1
P2 @ VEE = -5V
P3 @ VEE = -48V
P4 @ VEE = -5V
P5 @ VEE = -5V
Power supply currents (VBat = -48V)
VCC current, ICC
VEE current, IEE
VBat current, IBat
VCC current, ICC
VEE current, IEE
VBat current, IBat , On-hook
Power supply rejection ratios
VCC to 2- or 4-wire port
VEE to 2- or 4-wire port
VBat to 2- or 4-wire port
VBat2 to 2- or 4-wire port
Temperature guard
Junction threshold temperature, TJG
6
Conditions
ILTh =
500
RLD
Source resistance, RS = 0 Ω
IB = (IDT + IDR)/2
IOL = 50 mA
VOH = 12 V
0.2
0
2.5
VIL = 0.5
VIH = 2.5 V
IOL = 1 mA
0.1
Open circuit state, C1, C2, C3 = 0, 0, 0
Active state, C1, C2, C3 = 0, 1, 0
Longitudinal current = 0 mA, IL = 0 mA
RL = 300Ω (off-hook)
RL = 800Ω (off-hook)
Open circuit state
C1, C2, C3 = 0, 0, 0
Active state
C1, C2, C3 = 0, 1, 0
Long Current = 0 mA, IL = 0 mA
Active State
C1, C2, C3 = 0, 1, 0
f = 1 kHz, Vn = 100mV
0.6
10
V
kΩ
10
35
39
710
340
14
42
46
mW
mW
mW
mW
mW
1.4
-0.8
1.0
-0.1
-0.1
2.1
0.1
-0.5
mA
mA
mA
mA
mA
mA
30
28.5
40
28.5
45
55
50
60
-0.2
-0.2
140
3.5
0.3
dB
dB
dB
dB
°C
PBL 386 10/2
Notes
1.
2.
3.
The overload level is automatically expanded when the
signal level > 2.5 VPeak and is specified at the two-wire port
with the signal source at the four-wire receive port.
The two-wire impedance is programmable by selection of
external component values according to:
ZTR = ZT/|G2-4S α RSN| where:
ZTR = impedance between the TIPX and RINGX
terminals
ZT = programming network between the VTX and RSN
terminals
G2-4S = transmit gain, nominally = -0.5
α RSN = receive current gain, nominally = 400 (current
defined as positive flowing into the receivesumming node, RSN, and when flowing from tip to ring).
Higher return loss values can be achieved by adding a
reactive component to RT, the two-wire terminating
impedance programming resistance, e.g. by dividing RT
into two equal halves and connecting a capacitor from the
common point to ground.
4.
5.
6.
7.
8.
The overload level is automatically expanded as needed
up to 2.5 VPeak when the signal level >1.25 VPeak and is
specified at the four-wire transmit port, VTX, with the
signal source at the two-wire port. Note that the gain from
the two-wire port to the four-wire transmit port is
G2-4S = -0.5.
Secondary protection resistors RF impact the insertion
loss. The specified insertion loss is for RF = 0.
The specified insertion loss tolerance does not include
errors caused by external components.
The level is specified at the four-wire receive port and
referenced to a 600 Ω programmed two-wire impedance
level.
The two-wire idle noise is specified with the four-wire
receive port grounded (ERX = 0; see figure 6).
The four-wire idle noise at VTX is the two-wire value -6 dB
and is specified with the two-wire port terminated in 600 Ω
(RL). The noise specification is referenced to a 600 Ω
programmed two-wire impedance level at VTX. The fourwire receive port is grounded (ERX = 0).
7
PBL 386 10/2
Pin Description
Refer to figure 7.
PLCC
Symbol
Description
1
2
VBAT
VBAT2
3
AOV
4
PSG
5
LP
6
DT
7
DR
Battery supply voltage. Negative with respect to BGND.
An optional second battery voltage, connected in series with a diode, or an external powerhandling
resistor connects to this pin.
Adaptive Overhead Voltage. If the pin is left open then the overhead voltage is set internally to 2.5 VPeak
in off-hook and 1.4 VPeak in on-hook. The overhead voltage will adapt to signals > 2.5 VPeak. If pin is
connected to AGND then no internal overhead voltage is set. The overhead voltage adapts to
0.6 VPeak < signals < 5 VPeak.
Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a
resistor connected from this pin to VBAT.
Low Pass saturation guard filter capacitor connected here to filter out noise and improve PSRR. Other
end of CLP connects to VBAT.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level
low, indicating off-hook condition. The ring trip network connects to this input.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The ring trip network connects to this input.
8
9
10
11
VEE
REF
NU
PLC
12
PLD
13
VCC
14
15
16
17
18
C3
C2
C1
NC
DET
19
RSN
20
21
AGND
VTX
22
23
24
25
26
RRLY
TS
NC
HP
RINGX
27
28
BGND
TIPX
8
}
-5V to VBAT power supply.
A 15kohm resistor should be connected between this pin and AGND.
Not Used. Must be left open.
Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor
connected from this pin to AGND.
Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
+5 V power supply.
C1, C2 and C3 are digital inputs Controlling the SLIC operating states. Refer to section
Operating states for details.
No Connect. Must be left open.
Detector output. Active low when indicating loop or ring trip detection, active high when indicating ground
key detection
Receive Summing Node. 400 times the current flowing into this pin equals the metallic (transversal)
current flowing from TIPX to RINGX. Programming networks for two-wire impedance and receive gain
connect to the receive summing node.
Analog Ground, should be tied together with BGND.
Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire
impedance programming network connects between VTX and RSN.
Ring Relay driver output.
Tip Sense should be connected to TIPX.
No Connect. Must be left open.
High Pass connection for ac/dc separation capacitor CHP. Other end of CHP connects to RINGX (pin 26).
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
Battery Ground, should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
VBAT
TIPX
BGND
RINGX
27
26
VBAT2
2
1
AOV
3
28
PSG
4
PBL 386 10/2
LP 5
25 HP
DT 6
24 NC*
DR 7
23 TS
VEE 8
22 RRLY
REF 9
21 VTX
20 AGND
NU 10
DET 18
NC* 17
C1 16
C2 15
C3 14
VCC 13
19 RSN
PLD 12
PLC 11
* Pins must be left open.
Figure 7. Pin configuration, 28 pin PLCC package, top view.
SLIC Operating States
State
C3
C2
C1
SLIC operating state
Active detector
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Open circuit
Ringing state
Active state
Not applicable
Not applicable
Active state
Not applicable
Not applicable
Detector is set high
Ring trip detector (active low)
Loop detector (active low)
Ground key detector (active high)
-
Table 1. SLIC operating states.
9
PBL 386 10/2
TIPX
TIP
+
IL
RF
ZL
ZTR
VTR
RHP
EL
-
+
RING
+
G2-4S
-
VTX
+
VTX
RF
IL
RINGX
-
ZT
Z RX
+
RSN
VRX
I L /α RSN
-
PBL 386 10/2
Figure 9. Simplified ac transmission circuit.
Functional Description and Applications
Information Transmission
General
A simplified ac model of the transmission
circuits is shown in figure 9. Circuit analysis
yields:
VTX
VTR =
(1)
- I • 2RF
G2-4S L
VTX VRX
I
(2)
+
= L
ZRX αRSN
ZT
VTR = IL • ZL - EL
(3)
where:
VTX is a ground referenced version
of the ac metallic voltage
between the TIPX and RINGX
terminals.
VTR is the ac metallic voltage
between tip and ring.
EL is the line open circuit ac metallic
voltage.
IL
is the ac metallic current.
RF is a fuse resistor.
G2-4S is the SLIC two-wire to fourwire gain (transmit direction) with
a nominal value of -0.5.
ZL is the line impedance.
ZT determines the SLIC TIPX to
RINGX impedance for signal in
the 0 - 20kHz frequency range.
ZRX controls four- to two-wire gain.
10
VRX is the analogue ground referenced
receive signal.
αRSN is the receive summing node
current to metallic loop current
gain. The nominal value of
αRSN = 400
Two-Wire Impedance
To calculate ZTR, the impedance presented to the two-wire line by the SLIC including
the fuse resistor RF, let VRX = 0.
From (1) and (2):
ZT
ZTR =
- 2RF
αRSN • G2-4S
Thus with ZTR, G2-4S, αRSN, and RF known:
ZT = αRSN • G2-4S • (2RF - |ZTR|)
Two-Wire to Four-Wire Gain
From (1) and (2) with VRX = 0:
G2-4 =
VTX
=
VTR
ZT/αRSN
ZT
- 2RF
αRSN • G2-4S
Four-Wire to Two-Wire Gain
From (1), (2) and (3) with EL = 0:
G4-2 =
VTX ZT
ZL
•
=
VTR ZRX ZT
• ( ZL + 2RF)
-G
αRSN 2-4S
In applications where
2RF - ZT/(αRSN • G2-4S) is chosen to be
equal to ZL, the expression for G4-2 simplifies to:
G4-2 = -
ZT
1
•
ZRX 2 • G2-4S
Four-Wire to Four-Wire Gain
From (1), (2) and (3) with EL = 0:
G4-4 =
G2-4S • ( ZL + 2RF)
VTX ZT
•
=
VRX ZRX ZT
- G2-4S • ( ZL + 2RF)
αRSN
PBL 386 10/2
Hybrid Function
The PBL 386 10/2 SLIC may also be
used together with programmable CODEC/
filters. The programmable CODEC/filter
allows for system controller adjustment of
hybrid balance to accommodate different
line impedances without change of hardware. In addition, the transmit and receive
gain may be adjusted. Please, refer to the
programmable CODEC/filter data sheets
for design information.
The hybrid function can easily be implemented utilizing the uncommitted amplifier
in conventional CODEC/filter combinations.
Please, refer to figure 10. Via impedance
ZB a current proportional to VRX is injected
into the summing node of the combination
CODEC/filter amplifier. As can be seen
from the expression for the four-wire to
four-wire gain a voltage proportional to VRX
is returned to VTX. This voltage is converted
by RTX to a current flowing into the same
summing node. These currents can be
made to cancel by letting:
Longitudinal Impedance
A feed back loop counteracts longitudinal
voltages at the two-wire port by injecting
longitudinal currents in opposing phase.
Thus longitudinal disturbances will appear as longitudinal currents and the TIPX
and RINGX terminals will experience very
small longitudinal voltage excursions, leaving metallic voltages well within the SLIC
common mode range.
The SLIC longitudinal impedance per wire,
ZLoT and ZLoR, appears as typically 20 Ω to
longitudinal disturbances. It should be noted that longitudinal currents may exceed
the dc loop current without disturbing the vf
transmission.
VTX VRX
+
= 0 (EL = 0)
RTX ZB
The four-wire to four-wire gain, G4-4, includes the required phase shift and thus
the balance network ZB can be calculated
from:
V
ZB = - RTX • RX =
VTX
Z
- RTX • RX •
ZT
ZT
αRSN - G2-4S • ( ZL + 2RF)
G2-4S • ( ZL + 2RF)
When choosing RTX, make sure the
output load of the VTX terminal is (RTX//RT
in figure 12) > 20 kΩ.
Capacitors CTC and CRC
If RFI filtering is needed, the capacitors
designated CTC and CRC in figure 12, connected between TIPX and ground as well
as between RINGX and ground, may be
mounted.
CTC and CRC work as RFI filters in conjunction with suitable series impedances
(i.e. resistances, inductances). Resistors
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is recommended. Contact Ericsson Microelectronics for assistance.
RF1 and RF2 may be sufficient, but series
inductances can be added to form a second order filter. Current-compensated inductors are suitable since they suppress
common-mode signals with minimum influence on return loss. Recommended values
for CTC and CRC are below 1 nF. Lower
values impose smaller degradation on return loss and longitudinal balance, but also
attenuate radio frequencies to a smaller
extent. The influence on the impedance
loop must also be taken into consideration
when programming the CODEC. CTC and
CRC contribute to a metallic impedance of
1/(π•f•CTC) = 1/(π•f•CRC), a TIPX to ground
impedance of 1/(2•π•f•CTC) and a RINGX to
ground impedance of 1/(2•π•f•CRC).
AC - 3DC Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HP and RINGX p r o vides the separation of the ac and dc
signals. CHP positions the low end frequency response break point of the ac loop in the
SLIC. Refer to table 1 for recommended
value of CHP.
Example: A CHP value of 68 nF will
position the low end frequency response
3dB break point of the ac loop at 13 Hz (f3dB)
according to f3dB = 1/(2•π•RHP•CHP) where
RHP = 180 kΩ.
RFB
RTX
VTX
VT
PBL
386 10/2
ZT
ZB
Z RX
Combination
CODEC/Filter
V RX
RSN
Figure 10. Hybrid function.
11
PBL 386 10/2
High-Pass Transmit Filter
When CODEC/filter with a singel 5 V power
supply is used, it is necessary to separate
the different signal reference voltages between the SLIC and the CODEC/filter. In
the transmit direction this can be done by
connecting a capacitor between the VTX
output of the SLIC and the CODEC/filter
input. This capacitor will also form, together with RTX and/or the input impedance of
the CODEC/filter, a high-pass RC filter. It is
recommended to position the 3 dB break
point of this filter between 30 and 80 Hz to
get a fast enough response for the dc steps
that may occur with DTMF signaling.
Capacitor CLP
The capacitor CLP, which connects between
the terminals LP and VBAT, positions the
high end frequency break point of the low
pass filter in the dc loop in the SLIC. CLP
together with CHP and ZT (see section TwoWire Impedance) forms the total two wire
output impedance of the SLIC. The choice
of these programming components influence the power supply rejection ratio
(PSRR) from VBAT to the two wire side in
the low frequency range.
RFeed
RSG
CLP
CHP
[Ω]
[kΩ] [nF] [nF]
2•25
4.02 330 68
23.7 330 68
2•50
2•200
147 100 33
2•400
301 47
33
2•800
619 22
33
Table 1. RSG, CLP and CHP values for
different feeding characteristics.
Table 1 suggest values of CLP and CHP for
different feeding characteristics.
For values outside table 1, please contact Ericsson Microelectronics for assistance.
Adaptive Overhead Voltage, AOV
The Adaptive Overhead Voltage feature
minimises the power dissipation and at the
same time provides a flexible solution for
differing system requirements and possible future changes concerning voice, metering and other signal levels. This is done
by using an overhead voltage which automatically adapts to the signal level (voice +
metering). With the AOV-pin left open, the
PBL 386 10/2 will behave as a SLIC with
fixed overhead voltage for signals in the 0
- 20kHz frequency range and with an ampli-
12
Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst
undersampled).
tude less than 2.5VPeak11. For signal amplitudes between 2.5VPeak and 5.0VPeak, the
AOV-function will expand the overhead
voltage making it possible for the signal, Vt,
to propagate through the SLIC without distortion (see figure 11). The expansion of
the overhead voltage occurs instantaneously. When the signal amplitude decreases, the overhead voltage returns to its initial
value with a time constant of approximately
one second.
If the AOV-pin is connected to AGND, the
overhead voltage will automatically be adjusted for signal levels between 0.6 VPeak
and 5.0 VPeak.
AOV In the Constant Current Region
When the overhead voltage is automatically increased, the apparent battery (VApp,
reference F in figure 13), will be reduced by
the signal amplitude minus 2.5 VPeak(11), (Vt
- 2.5(11)).
In the constant current region this change
will not affect the line current as long as
VTR < VApp - (ILConst • RFeed) - (Vt- 2.5(11)),
(references A-C in figure 13).
AOV In the Resistive Loop Feed
Region
The saturation guard will be activated when
the SLIC is working in the resistive loop
feed region, i.e.
VTR > VApp - (ILConst • RFeed) - (Vt - 2.5(11))
(references D in figure 13).
If the signal amplitude is greater than
2.5VPeak11 the line current, IL, will be re-
duced corresponding to the formula
∆IL = | (Vt - 2.5(11))/(RL + RFeed) |.
This reduction of line current will introduce a transversal signal into the two-wire
which under some circumstances may be
audible (e g when sending metering signals > 2.5 VPeak without any speech signal
burying the transversal signal generated
from the linecurrent reduction).
The sum of all signals should not exceed
5.0 VPeak.
Line Feed
If VTR < VApp - (ILConst • RFeed), the PBL 386 10/
2 SLIC will emulate constant current feed
(references A-C in figure 13).
For VTR > VApp - (ILConst • RFeed) the PBL 386
10/2 SLIC will emulate resistive loop feed
programmable between 2•25 Ω12 and 2•900
Ω (references D in figure 13). The current
limitation region is adjustable between 0
mA and 65 mA13.
When the line current is approaching
open loop conditions, the overhead voltage is reduced. To ensure maximum open
loop voltage, even with telephone line leakage, this occurs at a line current of approximately 5 mA (references E in figure 13).
After the overhead voltage reduction, the
line voltage is kept nearly constant with a
steep slope corresponding to 2 • 25 Ω(reference G in figure 13).
The open loop voltage, VTRMax, measured
between the TIPX and RINGX terminals is
tracking the battery voltage VBat (references H in figure 13). VTRMax is programmable
by connecting the AOV-pin to AGND or by
leaving the AOV-pin open.
PBL 386 10/2
VTRMax is defined as the battery voltage on
the VBat terminal minus the Battery Over
Head voltage, VBOH, according to the equation
VTRMax(at IL = 0 mA) = |VBat| - VBOH
Refer to table 2 for typical VBOH values.
AOV-PIN NC
AOV-PIN to AGND
VBOH(typ) [V]
3.7
3.2
Table 2. The battery overhead voltages
at open loop conditions.
Resistive Loop Feed Region
The resistive loop feed (reference D in
figure 13) is programmed by connecting a
resistor RSG , between terminals PSG and
VBAT according to the equation
RFeed =
RSG
+ 40 + 2RF
400
If the VB2 voltage is not available, an
optional external power management resistor, RPM, may be connected between the
VBAT2-pin and the VBAT-pin to move power dissipation outside the chip.
Calculation of the external power management resistor to locate the maximum
power dissipation outside the SLIC is according to:
RPM =
|VBat| - 3
ILProg
Metering Applications
It is very easy to use PBL 386 10/2 in
metering applications; simply connect a
suitable resistor (RM) in series with a capacitor (CM) between pin RSN and the
metering source. Capacitor CM decouples
all DC-voltages that may be superimposed
on the metering signal. Choose 1/(2πRMCM)
≥ 5kHz to suppress low frequency disturbances from the metering puls generator.
The metering signal gain can be calculated
from the equation:
Analog Temperature Guard
The widely varying environmental conditions in which SLICs operate may lead to
the chip temperature limitations being exceeded. The PBL 386 10/2 SLIC reduces
the dc line current and the longitudinal
current limit when the chip temperature
reaches approximately 145°C and increases it again automatically when the temperature drops.
The detector output, DET, is forced to a
logic low level when the temperature guard
is active.
Loop Monitoring Functions
The loop current, ground key and ring trip
detectorsreport their status through a common output, DET. The status of the detector pin, DET, is selected via the three bit
control interface C1, C2 and C3. Please
refer to section Control Inputs for a description of the control interface.
Constant Current Region
The current limit (reference C in figure 13)
is adjusted by connecting a resistor, RLC,
between terminal PLC and ground according to the equation:
RLC =
500
ILProg
14
Battery Switch (VBAT2)
To reduce short loop power dissipation, a
second lower battery voltage may be connected to the device through an external
diode at terminal VBAT2. The SLIC automatically switches between the two battery
supply voltages without need for external
control. The silent battery switching occurs
when the line voltage passes the value
|VBat2| - 40•IL - 6 15
Connect the terminal VBAT2 to the second power supply via the diode DB2 in figure
14.
An optional diode DBB connected between
terminal VBAT and the VB2 power supply,
see figure 12, will make sure that the SLIC
continues to work on the second battery
even if the first battery voltage disappears.
G4-2Metering =
ZT
ZM
•
VTR
=
VMeter
ZLM
ZT
- G2-4S • (ZLM + 2RF)
αRSN
where
Vmeter is the voltage of the signal at the
metering generator,
is the line impedance seen by the
ZLM
12 or 16 kHz metering signal,
G2-4S is the transmit gain through the SLIC,
i e -0.5.
In metering applications with resistive
line feeding characteristic and very strict
requirements (as mentioned earlier in chapter “AOV in resistive loop feed region“), the
metering signal level should not exceed 2.2
VRMS 16, since a reduction of the line current
will generate a transversal, and sometimes
audible, signal (which is not the case in the
constant current region).
13
PBL 386 10/2
R FB
PBL 386 10/2
R TX
KR
RRLY
+12 V /+5V
C GG
C RC
VB
C TC
R F2
C B2
D BB
R SG
VB
CB
R1
RSN
HP
DET
out
RT
RINGX
NC
BGND
C1
TIPX
C2
RB
R RX
+
CODEC/
Filter
C3
VBAT2
VCC
AOV
PLD
PSG
PLC
LP
NC
DR
REF
DT
VEE
VCC
R RT
R2
C1
R3
R4
R LD
R LC
C LP
E RG
R RF
NC
VBAT
D B2
VB2
DB
AGND
out
OVP
TIP
TS
C HP
R F1
RING
-
VTX
SYSTEM CONTROL
INTERFACE
R REF
VEE
C2
VCC
+5 V
C VCC
C VEE
VBAT<VEE<-5 V
RESISTORS: (Values according to IEC-63 E96
series)
RSG
RLD
RLC
RREF
RT
RTX
RB
RRX
RFB
R1
R2
R3
R4
RRT
RRF
RF1, RF2
= 23.7 kΩ 1% 1/10 W
= 49.9 kΩ 1% 1/10 W
= 18.7 kΩ
1% 1/10 W
= 15 kΩ
1% 1/10 W
= 105 kΩ
1% 1/10 W
= 32.4kΩ
1% 1/10 W
= 57.6kΩ
1% 1/10 W
= 105kΩ
1% 1/10 W
Depending on CODEC / filter
= 604 kΩ
1% 1/10 W
= 604 kΩ
1% 1/10 W
= 249 kΩ
1% 1/10 W
= 280 kΩ
1% 1/10 W
= 332 Ω
5% 2 W
= 332 Ω
5% 2 W
= Line resistor, 40 Ω 1%
CAPACITORS:(Values according to IEC-63 E6
series)
DIODES:
CB
CB2
CVCC
CVEE
CTC
CRC
CHP
CLP
CGG
C1
C2
DB
DB2
DBB
= 100 nF
= 150 nF
= 100 nF
= 100 nF
= optional
= optional
= 68 nF
= 330 nF
= 220 nF
= 330 nF
= 330 nF
100 V 20%
100 V 20%
10 V 20%
10 V* 20%
100 V 20%
100 V 20%
100 V 20%
63 V 10%
63 V 10%
VEE
= 1N4448
= 1N4448
= 1N4448 (optional)
OVP:
Secondary protection (eg Power Innovations TISP
PBL1 or PBL2). The ground terminals of the
secondary protection should be connected to the
common ground on the Printed Board Assembly
with a track as short and wide as possible,
preferably a groundplane.
*100V if VEE pin connected to VBAT, VBAT2
Figure 12. Single-channel subscriber line interface with PBL 386 10/2 and combination CODEC/filter
Loop Current Detector
The loop current detector indicates that the
telephone is off hook and that DC current is
flowing in the loop by putting the output pin
DET, to a logic low level when selected.
The loop current detector threshold value,
ILTh, where the loop current detector changes state, is programmable with the RLD
resistor. RLD connects between pin PLD
and ground and is calculated according to:
RLD =
14
500
ILTh
The current detector is internally filtered
and is not influenced by the ac signal at the
two wire side.
Ground Key Detector
The ground key detector indicates when
the ground key is pressed (active) by putting
the output pin DET to a logic high level
when selected. The ground key detector
circuit senses the difference between TIPX
and RINGX currents. The detector is triggered when the difference exceeds the
current threshold.
Ring Trip Detector
Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The
ringing source can be balanced or unbalanced e g superimposed on the battery
voltage or ground. The unbalanced ringing
source may be applied to either the ring
lead or the tip lead with return via the other
wire. A ring relay driven by the SLIC ring
relay driver connects the ringing source to
tip and ring.
The ring trip function is based on a polarity change at the comparator input when
PBL 386 10/2
the line goes off-hook. In the on-hook state
no dc current flows through the loop and
the voltage at comparator input DT is more
positive than the voltage at input DR. When
the line goes off-hook, while the ring relay
is energized, dc current flows and the comparator input voltage reverses polarity.
Figure 12 gives an example of a ring trip
detection network. This network is applicable, when the ring voltage superimposed
on the battery voltage is injected on the ring
lead of the two-wire port. The dc voltage
across sense resistor RRT is monitored by
the ring trip comparator input DT and DR
via the filter network R1, R2, R3, R4, C1 and
C2. DT is more positive than DR, with the
line on-hook (no dc current). The DET
output will report logic level high, i.e. the
detector is not tripped. When the line goes
off-hook, while ringing, a dc current will flow
through the loop including sense resistor
RRT and will cause the input DT to become
more negative than input DR. This changes the output on the DET pin to logic level
low, i.e. tripped detector condition. The
system controller (or line card processor)
responds by de-energizing the ring relay
via the SLIC, i.e. ring trip.
Complete filtering of the 20 Hz ac component at terminals DT and DR is not necessary. A toggling DET output can be examined by a software routine to determine the
duty cycle. Off-hook condition is indicated
when the DET output is at logic level low for
more than half the time.
Detector Output (DET)
The PBL 386 10/2 SLIC incorporates a
detector output driver designed as open
collector (npn) with a current sinking capability of min 3 mA, and a 10 kΩ pull-up
resistor. The emitter of the drive transistor
is connected to AGND. A LED can be
connected in series with a resistor (≈1 kΩ)
at the DET output to visualize, for example
loop status.
Relay driver
The PBL 386 10/2 SLIC incorporates a
ring relay driver designed as open collector
(npn) with a current sinking capability of 50
mA.The emitter of the drive transistor is
connected to BGND. The relay driver has
an internal zener diode clamp to protect the
SLIC from inductive kick-back voltages. No
external clamp is needed.
Control Inputs
The PBL 386 10/2 SLIC has three digital
control inputs, C1, C2 and C3.
A decoder in the SLIC interprets the control input condition and sets up the commanded operating state.
C1 to C3 are internal pull-up inputs.
Open Circuit State
In the Open Circuit State the TIPX and
RINGX line drive amplifiers as well as other
circuit blocks are powered down. This causes the SLIC to present a high impedance to
the line. Power dissipation is at a minimum
and no detectors are active.
Ringing State
In the ringing state the SLIC will behave
as in the active state with the exception
that the ring relay driver and the ring trip
detector are activated. The ring trip detector will indicate off hook with a logic low
level at the detector output.
Active State
TIPX is the terminal closest to ground
and sources loop current while RINGX is
the more negative terminal and sinks loop
current. The loop current or the ground key
detector is activated. The loop current detector indicates off hook with a logic low
level and the ground key detector indicates
active ground key with a logic high level
present at the detector output.
Overvoltage Protection
PBL 386 10/2 must be protected against
overvoltages on the telephone line. The
overvoltages could be caused for instance
by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and
RINGX terminals, for maximum continuous and transient voltages.
Secondary Protection
The circuit shown in figure 12 utilizes
series resistors together with a programmable overvoltage protector (e g Power
Innovations TISP PBL1 or PBL2), serving
as a secondary protection.
The TISP PBLx is a dual forward-conducting buffered p-gate overvoltage protector. The protector gate references the
protection (clamping) voltage to negative
supply voltage (i.e. the battery voltage, VB).
As the protection voltage will track the
negative supply voltage the overvoltage
stress on the SLIC is minimised.
Positive overvoltages are clamped to
ground by a diode. Negative overvoltages
are initially clamped close to the SLIC negative supply rail voltage and the protector
will crowbar into a low voltage on-state
condition, by firing an internal thyristor.
A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high
enough current to quickly turn on the thyristor in the protector. CGG should be placed
close to the overvoltage protection device.
Without the capacitor even the low inductance in the track to the VB supply will limit
the current and delay the activation of the
thyristor clamp.
15
PBL 386 10/2
DC characteristics
B
A
C
C
B
D
I L [mA]
D
E
J
G
F
H
F
V T R [V]
A:
IL (@ VTR = 0) = ILConst
B, C: IL = ILConst
ILConst (typ) = ILProg =
500
RLC (14)
VTR = VBatVirt - RFeed • (ILProg - 5•10-3)
E:
RSG
+ 40
400
IL ≈ 5 mA
F:
G:
Apparent battery VApp (@IL = 0) = VBatVirt + 5•10-3 • RFeed
RFeedG = 2 • 25 Ω
H:
J:
VTRMax = |VBat| - VBOH
Virtual battery VBatVirt (@ IL = 5 mA) = |VBat| - 6.1(17)
D:
RFeed =
Figure 13. Battery feed characteristics (without the protection resistors on the line).
The programmed line current, ILProg, must
be less than 55 mA when using the TISP
PBL1 to ensure that the TISP holding current is not exceeded. For higher programmed line currents, the TISP PBL2 is
recommended.
The fuse resistors RF serve the dual purposes of being non- destructive energy
dissipators, when transients are clamped
and of being fuses, when the line is exposed to a power cross. Ericsson Microelectronics AB offers a series of thick film
16
resistors networks (e g PBR 51- series and
PBR 53-series) designed for this purpose.
Also devices with a built in resetable fuse
function are offered (e g PBR 52-series)
including positive temperature coefficient
(PTC) resistors, working as resetable fuses, in series with thick film resistors.
Note that it is always important to use
resistors not sensitive to temperature in
series with PTC´s since the PTC acts as a
capacitance for transients. Otherwise the
SLIC is not protected properly.
Power-up Sequence
No special power-up sequence is necessary except that ground has to be present
before all other power supply voltages.
The digital inputs C1 to C3 are internal
pull-up terminals.
PBL 386 10/2
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout
is essential for proper function;
The components connecting to the RSN
input should be placed in close proximity to
that pin, such that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable.
Analog ground (AGND) should be connected to battery ground (BGND) on the
PCB in one point.
RLC and RREF should be connected to
AGND with short leads. Pin LP, pin PSG
and pin AOV are sensitive to leakage currents. Pin AOV should be surrounded by a
guardring connected to AGND.
RSG and CLP connections to VBAT should
be short and very close to each other.
CB and CB2 must be connected with short
wide leads.
Notes
Note 11.
2.5 VPeak if AOV-pin is left open and 0.6 VPeak
if AOV-pin is connected to AGND.
Note 12.
RFeed lower than 2x50Ω will reduce noise
and PSRR performance in resistive loop
region (reference D in figure 13). Better
PSRR performance can be achieved by
increasing CLP and CHP.
Note 13.
If the momentary value of the current in
TIPX-pin or RINGX-pin exceeds 85mA
harmonic distortion specification can be
derated.
Note 14.
The accurate equation for RLC is:
RLC =
500 10.4 • In (ILProg • 32)
ILProg
ILProg
Note 15.
5.3V when AOV-pin is not connected, 3.9V
when AOV-pin is connected to AGND.
Note 16.
1.6VRMS if AOV-pin is left open and 0.4VRMS
if AOV-pin is connected to AGND.
Note 17.
6.1V when AOV-pin is left open, 4.2V when
AOV-pin is connected to AGND.
17
PBL 386 10/2
Ordering Information
Package
Temp. Range
28pin PLCC Tube
28pin PLCC Tape & Reel
0 ° - + 70 °C PBL 386 10/2QNS
0 ° - + 70 °C PBL 386 10/2QNT
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third parties
which may result from its use. No license is granted by
implication or otherwise under any patent or patent
rights of Ericsson Microelectronics AB. These products
are sold only according to Ericsson Microelectronics
general conditions of sale, unless otherwise confirmed
in writing.
Specifications subject to change without
notice.
1522-PBL 386 10/2 Uen Rev. D
© Ericsson Microelectronics AB, 1999
This product is an original Ericsson product
protected by US, European and other
patents.
Ericsson Microelectronics AB
S-164 81 Kista-Stockholm, Sweden
Telephone: +46 (0)8 757 50 00
18
Part No.