Preliminary February 2000 PBL 386 61/2 Subscriber Line Interface Circuit Description Key Features The PBL 386 61/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in Central Office, MUX and other telecommunications equipment. The PBL 386 61/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 61/2 emulates a transformer equivalent dc-feed, programmable between 2x25 Ω and 2x900 Ω, with short loop current limiting adjustable to max 65 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current and ring trip detection functions. The PBL 386 61/2 is compatible with loop start signalling. Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating impedance could be complex or real to fit every market. Longitudinal line voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 61/2 package is 28-pin PLCC. • Selectable overhead voltage principle – All adaptive: The overhead voltage follows 0.6 VPeak < signals < 6.2 VPeak. – Semi adaptive: The overhead voltage follows 3.1 VPeak < signals < 6.2 VPeak. • Metering 2.2 Vrms. • High and low battery with automatic switching • Battery supply as low as -10 V • Only +5 V in addition to GND and battery (VEE optional) • 39 mW on-hook power dissipation in active state • Long loop battery feed tracks VBat for maximum line voltage • 44 V open loop voltage @ -48 V battery feed • Constant loop voltage for line leakage <5 mA • On-hook transmission • Full longitudinal current capability during on-hook Ring Relay Driver RRLY • Programmable loop & ring-trip detector threshold C1 • Analog temperature guard DT Ring Trip Comparator DR TIPX Ground Key Detector RINGX C3 VCC DET TS Two-wire Interface Line Feed Controller and Longitudinal Signal Suppression PSG LP REF PLC 38 PB 6 L 61 /2 HP VEE C2 Input Decoder and Control AOV VBAT2 Off-hook Detector PLD AGND VBAT VTX BGND VF Signal Transmission RSN VEE 28-pin plastic PLCC Figure 1. Block diagram. 1 PBL 386 61/2 Preliminary Maximum Ratings Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range, Note 1 TStg TAmb TJ -55 -40 -40 +150 +110 +140 °C °C °C Power supply, 0°C ≤ TAmb ≤ +70°C VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND, continuous VBat with respect to BGND, 10 ms VBat2 with respect to A/BGND VCC VEE VBat VBat VBat2 -0.4 VBat -75 -80 VBat2 6.5 0.4 0.4 0.4 0.4 V V V V V Power dissipation Continuous power dissipation at TAmb ≤ +70 °C PD 1.5 W VCC V BGND +13 75 mA V Ground Voltage between AGND and BGND Relay Driver Ring relay supply voltage Ring relay current VG -5 Ring trip comparator Input voltage Input current VDT, VDR IDT, IDR VBat -5 VCC 5 V mA Digital inputs, outputs (C1, C2, DET) Input voltage VID -0.4 VCC V Output voltage (DET not active) VOD -0.4 Output current (DET) IOD TIPX and RINGX terminals, 0°C < TAmb < +70°C, VBat = -50 V TIPX or RINGX current TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3 ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA Parameter Ambient temperature Maximum supplied VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND VBat2 with respect to BGND VCC V 30 mA -110 VBat VBat - 20 VBat - 40 VBat - 70 +110 2 5 10 15 mA V V V V Symbol Min Max Unit TAmb VCC VEE VBat VBat2 0 4.75 VBat -58 VBat +70 5.25 -4.75 -10 -10 °C V V V V Recommended Operating Condition Notes 2 1. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. 2. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V. A pulse ≤1µs is increased to the greater of |-70V| and |VBat -40V|. 3. RF1 and RF2 ≥20 Ω are also required. Pulse is supplied to TIP and RING outside RF1 and RF2. Preliminary PBL 386 61/2 Electrical Characteristics 0 °C ≤ TAmb ≤ +70 °C, VCC = +5V ±5 %, VEE = -5V ± 5%, VBat = -58V to -40V, RLC=18.7kΩ, IL = 27 mA, ZL = 600 Ω, RF1, RF2 = 0 Ω, RRef = 15kΩ, CHP = 68nF, CLP=0.33 µF, RT = 120 kΩ, RSG = 24 kΩ, RRX = 120 kΩ, AOV and VBat2 pin not connected, unless otherwise specified. Current definition: current is positive if flowing into a pin. Parameter Ref fig Conditions Min Typ Max Unit Two-wire port Overload level, VTRO ,ILDC > 10 mA 2 Active state 1% THD, Note 1 On-Hook, ILDC ≤ 5 mA Input impedance, ZTR Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM VPeak VPeak Note 2 ZT/200 0 < f < 100 Hz 20 active state 28 IEEE standard 455-1985, ZTRX = 736 Ω, active state 0.2 kHz < f < 1.0 kHz 55 1.0 kHz < f < 3.4 kHz 55 Longitudinal to metallic balance, BLME E BLME = 20 • Log Lo VTR 3 Longitudinal to four-wire balance, BLFE ELo BLFE = 20 • Log VTX 3 Metallic to longitudinal balance, BMLE VTR BMLE = 20 • Log VLo 4 35 Ω/wire mArms /wire dB dB active state 0.2 kHz ≤ f ≤ 1.0 kHz 1.0 kHz < f < 3.4 kHz 55 55 dB dB 0.2 kHz ≤ f ≤ 1.0 kHz 1.0 kHz < f < 3.4 kHz 61 61 dB dB active state 0.2 kHz < f < 3.4kHz 40 dB active state Figure 2. Overload level, VTRO, two-wire port 1 << R , R = 600 Ω L L ωC 3.1 1.4 C RL TIPX VTRO ILDC VTX PBL 386 61/2 RT = 120 kΩ, RRX = 120 kΩ RINGX RT E RX RSN RRX Figure 3. Longitudinal to metallic (BLME) and Longitudinal to four-wire (BLFE) balance 1 ωC TIPX ELo C V TR << 150 Ω, RLR = RLT = RL /2= 300Ω VTX RLT PBL 386 61/2 RT V TX RLR RINGX RSN RRX RT = 120 kΩ, RRX = 120 kΩ 3 Preliminary PBL 386 61/2 Parameter Ref fig Conditions Four-wire to longitudinal balance, BFLE 4 active state Min ERX VLo 0.2 kHz < f < 3.4 kHz |ZTR + ZL| r = 20 • Log |ZTR - ZL| 0.2 kHz < f < 0.5 kHz 0.5 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz, Note 3 active, IL = 0 active, IL = 0 active, IL = 0 Typ Max Unit BFLE = 20 • Log Two-wire return loss, r TIPX idle voltage, VTi RINGX idle voltage, VRi VTR Four-wire transmit port (VTX) Overload level, ILDC ≥ 10 mA On hook ILDC ≤ 5 mA Output offset voltage, ∆VTX Output impedance, zTX 5 Four-wire receive port (RSN) Receive summing node (RSN) dc voltage Receive summing node (RSN) impedance Receive summing node (RSN) current (IRSN) to metallic loop current (IL) gain,αRSN Frequency response Two-wire to four-wire, g2-4 6 TIPX C dB 25 27 23 - 1.5 VBat+ 2.7 VBat +4.2 dB dB dB V V V 0.2 kHz < f < 3.4 kHz 5 VPeak VPeak mV Ω IRSN = 0 mA 0.2 kHz < f < 3.4 kHz 0.3 kHz < f < 3.4 kHz GND +25 10 50 mV Ω 400 ratio Load impedance > 20 kΩ, 1% THD, Note 4 1.55 0.7 -60 relative to 0 dBm, 1.0 kHz. ERX = 0 V 0.3 kHz < f < 3.4 kHz f = 8.0 kHz, 12 kHz, 16 kHz RT PBL 386 61/2 -0.1 0.15 0 dB dB 1 << 150 Ω, RLT = RLR = RL /2 =300Ω ωC E RX RLR RINGX -0.15 -0.5 60 20 Figure 4. Metallic to longitudinal and four-wire to longitudinal balance VTX RLT V TR VLo 40 RT = 120 kΩ, RRX = 120 kΩ RSN RRX C TIPX Figure 5. Overload level, VTXO, four-wire transmit port VTX RL ILDC EL PBL 386 61/2 RINGX RT 1 << RL, RL = 600 Ω ωC RT = 120 kΩ, RRX = 120 kΩ RSN RRX 4 VTXO Preliminary Parameter Ref fig Four-wire to two-wire, g4-2 6 Four-wire to four-wire, g4-4 6 Four-wire to two-wire, G4-2 6 Gain tracking Two-wire to four-wire RLDC≤ 2kΩ Four-wire to two-wire RLDC≤ 2kΩ 0 dBm, 1.0 kHz, Note 5 V G2-4 = 20 • Log TX ,ERX = 0 VTR 0 dBm, 1.0 kHz, Notes 5, 6 V G4-2 = 20 • Log TR ,EL = 0 ERX 6 6 Min Typ Max Unit -0.15 -1.0 -1.0 -0.2 -0.3 0.15 0 0 dB dB dB 0.15 dB -5.82 dB -0.2 0.2 dB -0.1 -0.2 0.1 0.2 dB dB -0.1 -0.2 0.1 0.2 dB dB 12 -78 dBrnC dBmp -50 -50 dB dB -0.15 -6.22 Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -55 dBm to -40 dBm Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -55 dBm to -40 dBm Noise Idle channel noise at two-wire (TIPX-RINGX) Harmonic distortion Two-wire to four-wire Four-wire to two-wire Conditions relative to 0 dBm, 1.0 kHz. EL = 0 V 0.3 kHz < f < 3.4 kHz f = 8 kHz, 12 kHz, 16 kHz relative to 0 dBm, 1.0 kHz. EL = 0 V 0.3 kHz < f < 3.4 kHz 6 Insertion loss Two-wire to four-wire, G2-4 PBL 386 61/2 C-message weighting Psophometrical weighting Note 8 6 0 dBm, 1.0 kHz test signal 0.3 kHz < f < 3.4 kHz 12 ILProg = 500 RLC -6.02 7 -85 Battery feed characteristics Constant loop current, ILConst 18 < ILProg < 65 mA Figure 6. Frequency response, insertion loss, gain tracking. 0.92 ILProg ILProg C TIPX 1.08 ILProg mA VTX RL VTR 1 << RL, RL = 600 Ω ωC EL RT = 120 kΩ, RRX = 120 kΩ ILDC PBL 386 61/2 RINGX RT E RX VTX RSN RRX 5 Preliminary PBL 386 61/2 Parameter Ref fig Loop current detector Programmable threshold, IDET Ring trip comparator Offset voltage, ∆VDTDR Input bias current, IB Input common mode range, VDT, VDR Ring relay driver Saturation voltage, VOL Off state leakage current, ILk Digital inputs (C1, C2, C3) Input low voltage, VIL Input high voltage, VIH Input low current, IIL Input high current, IIH Detector output (DET) Output low current, IOL Internal pull-up resistor Power dissipation (VBat = -48V, VBat2 = -32V) P1 P2 @ VEE = -5V P3 @ VEE = -48V P4 @ VEE = -5V P5 @ VEE = -5V Power supply currents (VBat = -48V) VCC current, ICC VEE current, IEE VBat current, IBat VCC current, ICC VEE current, IEE VBat current, IBat Power supply rejection ratios VCC to 2- or 4-wire port VEE to 2- or 4-wire port VBat to 2- or 4-wire port VBat2 to 2- or 4-wire port Temperature guard Junction threshold temperature, TJG 6 Conditions Min Typ Max Unit ILTh = 500 RLD 0.9•ILTh ILTh 1.1•ILTh mA Source resistance, RS = 0 Ω IB = (IDT + IDR)/2 -20 -50 VBat+1 0 -20 20 200 -1 mV nA V 0.5 100 V µA 0.5 VCC -200 200 V V µA µA IOL = 50 mA VOH = 12 V 0 2.5 VIL = 0.5 VIH = 2.5 V VOL < 0.6V 0.5 1 10 mA kΩ Open circuit state, C1, C2, C3 = 0, 0, 0 Active state, C1, C2, C3 = 0, 1, 0 Longitudinal current = 0 mA, IL = 0 mA RL = 300Ω (off-hook) RL = 800Ω (off-hook) 14 39 44 710 340 mW mW mW mW mW Open circuit state C1, C2, C3 = 0, 0, 0 0.8 -0.1 -0.2 2.0 0.1 -0.7 mA mA mA mA mA mA 35 55 40 60 dB dB dB dB Active state C1, C2, C3 = 0, 1, 0 On-hook, Long Current = 0 mA, IL = 0 mA Active State C1, C2, C3 = 0, 1, 0 50 Hz < f< 3400 Hz, Vn = 100mV 28.5 28.5 28.5 28.5 140 °C Preliminary PBL 386 61/2 Notes 1. 2. 3. The overload level is automatically expanded when the signal level > 3.1 VPeak and is specified at the two-wire port with the signal source at the four-wire receive port. The two-wire impedance is programmable by selection of external component values according to: ZTR = ZT/|G2-4S αRSN| where: ZTR = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G2-4S = transmit gain, nominally = -0.5 αRSN = receive current gain, nominally = 400 (current defined as positive flowing into the receivesumming node, RSN, and when flowing from tip to ring). Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance programming resistance, e.g. by dividing RT into two equal halves and connecting a capacitor from the common point to ground. 4. 5. 6. 7. 8. The overload level is automatically expanded as needed up to 3.1 VPeak when the signal level >1.55 VPeak and is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G2-4S = -0.5. Secondary protection resistors RF impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for RF = 0. The specified insertion loss tolerance does not include errors caused by external components. The level is specified at the four-wire receive port and referenced to a 600 Ω programmed two-wire impedance level. The two-wire idle noise is specified with the four-wire receive port grounded (ERX = 0; see figure 6). The four-wire idle noise at VTX is the two-wire value -6 dB and is specified with the two-wire port terminated in 600 Ω (RL). The noise specification is referenced to a 600 Ω programmed two-wire impedance level at VTX. The fourwire receive port is grounded (ERX = 0). 7 Preliminary PBL 386 61/2 Pin Description Refer to figure 7. PLCC Symbol 1 2 VBAT VBAT2 3 AOV 4 PSG 5 LP 6 DT 7 DR 8 9 10 11 VEE REF NU PLC 12 PLD Description Battery supply voltage. Negative with respect to BGND. An optional second battery voltage, connected in series with a diode, or an external powerhandling resistor connects to this pin. Adaptive Overhead Voltage. If the pin is left open then the overhead voltage is set internally to 3.1 VPeak in off-hook and 1.4 VPeak in on-hook. The overhead voltage will adapt to signals > 3.1 VPeak. If the pin is connected to AGND then no internal overhead voltage is set. The overhead voltage adapts to 0.6 VPeak < signals < 6.2 VPeak. Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a resistor connected from this pin to VBAT. Low Pass saturation guard filter capacitor connected here to filter out noise and improve PSRR. Other end of CLP connects to VBAT. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. -5V to VBAT power supply. A 15 kΩ resistor should be connected between this pin and AGND. Not Used. Must be left open. Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor connected from this pin to AGND. Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor connected from this pin to AGND. 13 VCC +5 V power supply. 14 NU Not Used. Pin must be connected to AGND. 15 16 C2 C1 17 NC No Connect. Must be left open. 18 DET 19 RSN 20 21 AGND VTX 22 23 24 25 26 RRLY TS NC HP RINGX 27 28 BGND TIPX Detector output. Active low when indicating loop or ring trip detection, active high when indicating ground key detection Receive Summing Node. 400 times the current flowing into this pin equals the metallic (transversal) current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain connect to the receive summing node. Analog Ground, should be tied together with BGND. Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire impedance programming network connects between VTX and RSN. Ring Relay driver output. Tip Sense should be connected to TIPX. No Connect. Must be left open. High Pass connection for ac/dc separation capacitor CHP. Other end of CHP connects to RINGX (pin 26). The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). Battery Ground, should be tied together with AGND. The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). 8 } C1 and C2 are digital inputs Controlling the SLIC operating states. Refer to section operating states for details. PSG AOV VBAT2 VBAT TIPX BGND RINGX 4 3 2 1 28 27 26 Preliminary PBL 386 61/2 23 TS VEE 8 22 RRLY REF 9 21 VTX NU 10 20 AGND PLC 11 19 RSN DET 18 DR 7 NC* 17 NC* C1 16 24 C2 15 DT 6 NU 14 HP VCC 13 25 PLD 12 LP 5 * Pins must be left open. Figure 7. Pin configuration 28 pin PLCC package, top view. SLIC Operating States State C3 C2 C1 SLIC operating state Active detector 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Open circuit Ringing state Active state Not applicable Not applicable Not applicable Not applicable Not applicable Detector is set high Ring trip detector (active low) Loop detector (active low) - Table 1. SLIC operating states. 9 Preliminary PBL 386 61/2 TIPX TIP + IL RF ZL ZTR VTR RHP EL - + RING + G2-4S - VTX + VTX RF IL RINGX - ZT Z RX + RSN VRX I L /α RSN - PBL 386 61/2 Figure 9. Simplified ac transmission circuit. Functional Description and Applications Information Transmission General A simplified ac model of the transmission circuits is shown in figure 9. Circuit analysis yields: VTX VTR = (1) - I • 2RF G2-4S L VTX VRX I + = L (2) ZRX αRSN ZT VTR = IL • ZL - EL (3) where: VTX is a ground referenced version of the ac metallic voltage between the TIPX and RINGX terminals. VTR is the ac metallic voltage between tip and ring. EL is the line open circuit ac metallic voltage. IL is the ac metallic current. RF is a fuse resistor. G2-4S is the SLIC two-wire to fourwire gain (transmit direction) with a nominal value of -0.5. ZL is the line impedance. ZT determines the SLIC TIPX to RINGX impedance for signal in the 0 - 20kHz frequency range. ZRX controls four- to two-wire gain. 10 VRX is the analogue ground referenced receive signal. αRSN is the receive summing node current to metallic loop current gain. The nominal value of αRSN = 400 Two-Wire Impedance To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the fuse resistor RF, let VRX = 0. From (1) and (2): ZT ZTR = - 2RF αRSN • G2-4S Thus with ZTR, G2-4S, αRSN, and RF known: ZT = αRSN • G2-4S • (2RF - |ZTR|) Two-Wire to Four-Wire Gain From (1) and (2) with VRX = 0: G2-4 = VTX = VTR ZT/αRSN ZT - 2RF αRSN • G2-4S Four-Wire to Two-Wire Gain From (1), (2) and (3) with EL = 0: G4-2 = VTX ZT ZL • = VTR ZRX ZT • ( ZL + 2RF) -G αRSN 2-4S In applications where 2RF - ZT/(αRSN • G2-4S) is chosen to be equal to ZL, the expression for G4-2 simplifies to: G4-2 = - ZT 1 • ZRX 2 • G2-4S Four-Wire to Four-Wire Gain From (1), (2) and (3) with EL = 0: G4-4 = VTX ZT G2-4S • ( ZL + 2RF) • = VRX ZRX ZT - G2-4S • ( ZL + 2RF) αRSN Preliminary Hybrid Function The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional CODEC/filter combinations. Please, refer to figure 10. Via impedance ZB a current proportional to VRX is injected into the summing node of the combination CODEC/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain a voltage proportional to VRX is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be made to cancel by letting: VTX VRX + = 0 (EL = 0) RTX ZB The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the balance network ZB can be calculated from: V ZB = - RTX • RX = VTX Z - RTX • RX • ZT ZT αRSN - G2-4S • ( ZL + 2RF) G2-4S • ( ZL + 2RF) When choosing RTX, make sure the output load of the VTX terminal (RTX//RT in figure 12) is > 20 kΩ. If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. Contact Ericsson Microelectronics for assistance. PBL 386 61/2 The PBL 386 61/2 SLIC may also be used together with programmable CODEC/ filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information. Longitudinal Impedance A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range. The SLIC longitudinal impedance per wire, ZLoT and ZLoR, appears as typically 20 Ω to longitudinal disturbances. It should be noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. Capacitors CTC and CRC If RFI filtering is needed, the capacitors designated CTC and CRC in figure 12, connected between TIPX and ground as well as between RINGX and ground, may be mounted. CTC and CRC work as RFI filters in conjunction with suitable series impedances (i.e. resistances, inductances). Resistors RF1 and RF2 may be sufficient, but series inductances can be added to form a second order filter. Current-compensated inductors are suitable since they suppress common-mode signals with minimum influence on return loss. Recommended values for CTC and CRC are below 1 nF. Lower values impose smaller degradation on return loss and longitudinal balance, but also attenuate radio frequencies to a smaller extent. The influence on the impedance loop must also be taken into consideration when programming the CODEC. CTC and CRC contribute to a metallic impedance of 1/(π•f•CTC) = 1/(π•f•CRC), a TIPX to ground impedance of 1/(2•π•f•CTC) and a RINGX to ground impedance of 1/(2•π•f•CRC). AC - DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HP and RINGX p r o vides the separation of the ac and dc signals. CHP positions the low end frequency response break point of the ac loop in the SLIC. Refer to table 1 for recommended value of CHP. Example: A CHP value of 68 nF will position the low end frequency response 3dB break point of the ac loop at 13 Hz (f3dB) according to f3dB = 1/(2•π•RHP•CHP) where RHP = 180 kΩ. RFB RTX VTX VT PBL 386 61/2 ZT ZB Z RX Combination CODEC/Filter V RX RSN Figure 10. Hybrid function. 11 PBL 386 61/2 Preliminary High-Pass Transmit Filter When CODEC/filter with a singel 5 V power supply is used, it is necessary to separate the different signal reference voltages between the SLIC and the CODEC/filter. In the transmit direction this can be done by connecting a capacitor between the VTX output of the SLIC and the CODEC/filter input. This capacitor will also form, together with RTX and/or the input impedance of the CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a fast enough response for the dc steps that may occur with DTMF signaling. Capacitor CLP The capacitor CLP, which connects between the terminals LP and VBAT, positions the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with CHP and ZT (see section TwoWire Impedance) forms the total two wire output impedance of the SLIC. The choice of these programming components influence the power supply rejection ratio (PSRR) from VBAT to the two wire side in the low frequency range. RFeed RSG CLP CHP [Ω] [kΩ] [nF] [nF] 4.02 330 68 2•25 2•50 23.7 330 68 2•200 147 100 33 2•400 301 47 33 2•800 619 22 33 Table 1. RSG, CLP and CHP values for different feeding characteristics. Table 1 suggest values of CLP and CHP for different feeding characteristics. For values outside table 1, please contact Ericsson Microelectronics for assistance. Adaptive Overhead Voltage, AOV The Adaptive Overhead Voltage feature minimises the power dissipation and at the same time provides a flexible solution for differing system requirements and possible future changes concerning voice, metering and other signal levels. This is done by using an overhead voltage which automatically adapts to the signal level (voice + metering). With the AOV-pin left open, the PBL 386 61/2 will behave as a SLIC with fixed overhead voltage for signals in the 0 - 20kHz frequency range and with an ampli- 12 Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst undersampled). tude less than 3.1VPeak11. For signal amplitudes between 3.1VPeak and 6.2VPeak, the AOV-function will expand the overhead voltage making it possible for the signal, Vt, to propagate through the SLIC without distortion (see figure 11). The expansion of the overhead voltage occurs instantaneously. When the signal amplitude decreases, the overhead voltage returns to its initial value with a time constant of approximately one second. If the AOV-pin is connected to AGND, the overhead voltage will automatically be adjusted for signal levels between 0.6 VPeak and 6.2 VPeak. AOV In the Constant Current Region When the overhead voltage is automatically increased, the apparent battery (VApp, reference F in figure 13), will be reduced by the signal amplitude minus 3.1 VPeak(11), (Vt - 3.1(11)). In the constant current region this change will not affect the line current as long as VTR < VApp - (ILConst • RFeed) - (Vt-3.1(11)), (references A-C in figure 13). AOV In the Resistive Loop Feed Region The saturation guard will be activated when the SLIC is working in the resistive loop feed region, i.e. VTR > VApp - (ILConst • RFeed) - (Vt - 3.1(11)) (references D in figure 13). If the signal amplitude is greater than 3.1VPeak11 the line current, IL, will be reduced corresponding to the formula ∆IL = | (Vt - 3.1(11))/(RL + RFeed) |. This reduction of line current will introduce a transversal signal into the two-wire which under some circumstances may be audible (e g when sending metering signals > 3.1 VPeak without any speech signal burying the transversal signal generated from the linecurrent reduction). The sum of all signals should not exceed 6.2 VPeak. Line Feed If VTR < VApp - (ILConst • RFeed), the PBL 386 61/ 2 SLIC will emulate constant current feed (references A-C in figure 13). For VTR > VApp - (ILConst • RFeed) the PBL 386 61/2 SLIC will emulate resistive loop feed programmable between 2•25 Ω12 and 2•900 Ω (references D in figure 13). The current limitation region is adjustable between 0 mA and 65 mA13. When the line current is approaching open loop conditions, the overhead voltage is reduced. To ensure maximum open loop voltage, even with telephone line leakage, this occurs at a line current of approximately 5 mA (references E in figure 13). After the overhead voltage reduction, the line voltage is kept nearly constant with a steep slope corresponding to 2 • 25 Ω(reference G in figure 13). The open loop voltage, VTRMax, measured between the TIPX and RINGX terminals is tracking the battery voltage VBat (references H in figure 13). VTRMax is programmable by connecting the AOV-pin to AGND or by Preliminary leaving the AOV-pin open. VTRMax is defined as the battery voltage on the VBat terminal minus the Battery Over Head voltage, VBOH, according to the equation VTRMax(at IL = 0 mA) = |VBat| - VBOH Refer to table 2 for typical VBOH values. VBOH(typ) [V] AOV-PIN NC 4.2 AOV-PIN to AGND 3.2 Table 2. The battery overhead voltages at open loop conditions. Resistive Loop Feed Region The resistive loop feed (reference D in figure 13) is programmed by connecting a resistor RSG , between terminals PSG and VBAT according to the equation RFeed = RSG + 40 + 2RF 400 even if the first battery voltage disappears. If the VB2 voltage is not available, an optional external power management resistor, RPM, may be connected between the VBAT2-pin and the VBAT-pin to move power dissipation outside the chip. Calculation of the external power management resistor to locate the maximum power dissipation outside the SLIC is according to: RPM = |VBat| - 3 ILProg RLC = 500 ILProg 14 Battery Switch (VBAT2) To reduce short loop power dissipation, a second lower battery voltage may be connected to the device through an external diode at terminal VBAT2. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery switching occurs when the line voltage passes the value |VBat2| - 40•IL - 6 15 Connect the terminal VBAT2 to the second power supply via the diode DB2 in figure 12. An optional diode DBB connected between terminal VBAT and the VB2 power supply, see figure 12, will make sure that the SLIC continues to work on the second battery Analog Temperature Guard The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 386 61/2 SLIC reduces the dc line current and the longitudinal current limit when the chip temperature reaches approximately 145°C and increases it again automatically when the temperature drops. The detector output, DET, is forced to a logic low level when the temperature guard is active. Metering Applications It is very easy to use PBL 386 61/2 in metering applications; simply connect a suitable resistor (RM) in series with a capacitor (CM) between pin RSN and the metering source. Capacitor CM decouples all DC-voltages that may be superimposed on the metering signal. Choose 1/(2πRMCM) ≥ 5kHz to suppress low frequency disturbances from the metering puls generator. The metering signal gain can be calculated from the equation: Constant Current Region The current limit (reference C in figure 13) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: PBL 386 61/2 G4-2Metering = ZT ZM • VTR = VMeter ZLM ZT • (ZLM + 2RF) -G αRSN 2-4S where VMeter is the voltage of the signal at the metering generator, is the line impedance seen by the ZLM 12 or 16 kHz metering signal, G2-4S is the transmit gain through the SLIC, i e -0.5. In metering applications with resistive line feeding characteristic and very strict requirements (as mentioned earlier in chapter “AOV in resistive loop feed region“), the metering signal level should not exceed 2.2 VRMS 16, since a reduction of the line current will generate a transversal, and sometimes audible, signal (which is not the case in the constant current region). Loop Monitoring Functions The loop current and ring trip detectors report their status through a common output, DET. The status of the detector pin, DET, is selected via the two bit control interface C1 and C2. Please refer to section Control Inputs for a description of the control interface. Loop Current Detector The loop current detector indicates that the telephone is off hook and that DC current is flowing in the loop by putting the output pin DET, to a logic low level when selected. The loop current detector threshold value, ILTh, where the loop current detector changes state, is programmable with the RLD resistor. RLD connects between pin PLD and ground and is calculated according to: RLD = 500 ILTh The current detector is internally filtered and is not influenced by the ac signal at the two wire side. Ring Trip Detector Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced e g superimposed on the battery voltage or ground. The unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC ring relay driver connects the ringing source to 13 Preliminary PBL 386 61/2 R FB PBL 386 61/2 R TX KR RRLY +12 V /+5V C GG C RC VB C TC R F2 C B2 D BB R SG VB CB R1 RSN HP DET out RT RINGX NC BGND C1 TIPX C2 RB R RX + CODEC/ Filter C3 VBAT2 VCC AOV PLD PSG PLC LP NC DR REF DT VEE VCC R RT R2 C1 R3 R4 R LD R LC C LP E RG R RF NC VBAT D B2 VB2 DB AGND out OVP TIP TS C HP R F1 RING - VTX SYSTEM CONTROL INTERFACE R REF VEE C2 VCC +5 V C VCC C VEE VBAT<VEE<-5 V RESISTORS: (Values according to IEC-63 E96 series) RSG RLD RLC RREF RT RTX RB RRX RFB R1 R2 R3 R4 RRT RRF RF1, RF2 = 23.7 kΩ 1% 1/10 W = 49.9 kΩ 1% 1/10 W = 18.7 kΩ 1% 1/10 W = 15 kΩ 1% 1/10 W = 105 kΩ 1% 1/10 W = 32.4kΩ 1% 1/10 W = 57.6kΩ 1% 1/10 W = 105kΩ 1% 1/10 W Depending on CODEC / filter = 604 kΩ 1% 1/10 W = 604 kΩ 1% 1/10 W = 249 kΩ 1% 1/10 W = 280 kΩ 1% 1/10 W = 332 Ω 5% 2 W = 332 Ω 5% 2 W = Line resistor, 40 Ω 1% VEE series) CB CB2 CVCC CVEE CTC CRC CHP CLP CGG C1 C2 = 100 nF = 150 nF = 100 nF = 100 nF = optional = optional = 68 nF = 330 nF = 220 nF = 330 nF = 330 nF 100 V 20% 100 V 20% 10 V 20% 10 V* 20% 100 V 20% 100 V 20% 100 V 20% 63 V 10% 63 V 10% DB DB2 DBB = 1N4448 = 1N4448 = 1N4448 (optional) OVP: Secondary protection (eg Power Innovations TISP PBL1 or PBL2). The ground terminals of the secondary protection should be connected to the common ground on the Printed Board Assembly with a track as short and wide as possible, preferably a groundplane. *100V if VEE pin connected to VBAT, VBAT2 DIODES: CAPACITORS:(Values according to IEC-63 E6 Figure 12. Single-channel subscriber line interface with PBL 386 61/2 and combination CODEC/filter tip and ring. The ring trip function is based on a polarity change at the comparator input when the line goes off-hook. In the on-hook state no dc current flows through the loop and the voltage at comparator input DT is more positive than the voltage at input DR. When the line goes off-hook, while the ring relay is energized, dc current flows and the comparator input voltage reverses polarity. Figure 12 gives an example of a ring trip detection network. This network is applicable, when the ring voltage superimposed on the battery voltage is injected on the ring 14 lead of the two-wire port. The dc voltage across sense resistor RRT is monitored by the ring trip comparator input DT and DR via the filter network R1, R2, R3, R4, C1 and C2. DT is more positive than DR, with the line on-hook (no dc current). The DET output will report logic level high, i.e. the detector is not tripped. When the line goes off-hook, while ringing, a dc current will flow through the loop including sense resistor RRT and will cause the input DT to become more negative than input DR. This changes the output on the DET pin to logic level low, i.e. tripped detector condition. The system controller (or line card processor) responds by de-energizing the ring relay via the SLIC, i.e. ring trip. Complete filtering of the 20 Hz ac component at terminals DT and DR is not necessary. A toggling DET output can be examined by a software routine to determine the duty cycle. Off-hook condition is indicated when the DET output is at logic level low for more than half the time. Preliminary Detector Output (DET) Active State The PBL 386 61/2 SLIC incorporates a detector output driver designed as open collector (npn) with a current sinking capability of min 3 mA, and a 5 kΩ pull-up resistor. The emitter of the drive transistor is connected to AGND. A LED can be connected in series with a resistor (≈1 kΩ) at the DET output to visualize, for example loop status. TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop current. The loop current or the ground key detector is activated. The loop current detector indicates off hook with a logic low level and the ground key detector indicates active ground key with a logic high level present at the detector output. Relay driver Overvoltage Protection The PBL 386 61/2 SLIC incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50 mA.The emitter of the drive transistor is connected to BGND. The relay driver has an internal zener diode clamp to protect the SLIC from inductive kick-back voltages. No external clamp is needed. Control Inputs The PBL 386 61/2 SLIC has two digital control inputs, C1 and C2. A decoder in the SLIC interprets the control input condition and sets up the commanded operating state. C1 and C2 are internal pull-up inputs. Open Circuit State In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This causes the SLIC to present a high impedance to the line. Power dissipation is at a minimum and no detectors are active. Ringing State In the ringing state the SLIC will behave as in the active state with the exception that the ring relay driver and the ring trip detector are activated. The ring trip detector will indicate off hook with a logic low level at the detector output. PBL 386 61/2 must be protected against overvoltages on the telephone line. The overvoltages could be caused for instance by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and RINGX terminals, for maximum continuous and transient voltages. Secondary Protection The circuit shown in figure 12 utilizes series resistors together with a programmable overvoltage protector (e g Power Innovations TISP PBL1 or PBL2), serving as a secondary protection. The TISP PBLx is a dual forward-conducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to negative supply voltage (i.e. the battery voltage, VB). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimised. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. PBL 386 61/2 A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. CGG should be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the VB supply will limit the current and delay the activation of the thyristor clamp. The programmed line current, ILProg, must be less than 55 mA when using the TISP PBL1 to ensure that the TISP holding current is not exceeded. For higher programmed line currents, the TISP PBL2 is recommended. The fuse resistors RF serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. Note that it is always important to use resistors not sensitive to temperature in series with PTC´s since the PTC acts as a capacitance for transients. Otherwise the SLIC is not protected properly. 15 Preliminary PBL 386 61/2 DC characteristics B A C C B D I L [mA] D E J G F H F V T R [V] A: IL (@ VTR = 0) = ILConst B, C: IL = ILConst ILConst (typ) = ILProg = 500 RLC (14) VTR = VBatVirt - RFeed • (ILProg - 5•10-3) E: F: RSG + 40 400 IL ≈ 5 mA Apparent battery VApp (@IL = 0) = VBatVirt + 5•10-3 • RFeed G: H: RFeedG = 2 • 25 Ω VTRMax = |VBat| - VBOH J: Virtual battery VBatVirt (@ IL = 5 mA) = |VBat| - 6.8(17) D: RFeed = Figure 13. Battery feed characteristics (without the protection resistors on the line). Power-up Sequence Printed Circuit Board Layout No special power-up sequence is necessary except that ground has to be present before all other power supply voltages. The digital inputs C1 and C2 are internal pull-up terminals. Care in Printed Circuit Board (PCB) layout is essential for proper function; The components connecting to the RSN input should be placed in close proximity to that pin, such that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be con- 16 nected to battery ground (BGND) on the PCB in one point. RLC and RREF should be connected to AGND with short leads. Pin LP, pin PSG and pin AOV are sensitive to leakage currents. Pin AOV should be surrounded by a guardring connected to AGND. RSG and CLP connections to VBAT should be short and very close to each other. CB and CB2 must be connected with short wide leads. Preliminary PBL 386 61/2 Notes Note 11. 3.1 VPeak if AOV-pin is left open and 0.6 VPeak if AOV-pin is connected to AGND. Note 12. RFeed lower than 2x50Ω will reduce noise and PSRR performance in resistive loop region (reference D in figure 13). Better PSRR performance can be achieved by increasing CLP and CHP. Note 13. If the momentary value of the current in TIPX-pin or RINGX-pin exceeds 85mA harmonic distortion specification can be derated. Note 14. The accurate equation for RLC is: RLC = 500 10.4 • In (ILProg • 32) ILProg ILProg Note 15. 6.0V when AOV-pin is not connected, 3.9V when AOV-pin is connected to AGND. Note 16. 2.2VRMS if AOV-pin is left open and 0.4VRMS if AOV-pin is connected to AGND. Note 17. 6.8V when AOV-pin is left open, 4.2V when AOV-pin is connected to AGND. 17 Preliminary PBL 386 61/2 Ordering Information Package Temp. Range Part No. 28pin PLCC Tube 0 °C - + 70 °C PBL 386 61/2QNS 28pin PLCC Tape & Reel 0 °C - + 70 °C PBL 386 61/2QNT Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBL 386 61/2 Uen Rev.2A © Ericsson Microelectronics AB, 2000 This product is an original Ericsson product protected by US, European and other patents. Ericsson Microelectronics AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 18