Features • • • • • • • • • • • • Fully Integrated Low IF Receiver Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 Kbits/s High Sensitivity of Typically –93 dBm Due to Integrated LNA High Output Power of Typically +4 dBm Multi-channel Operation – 95 Channels – Support Frequency Hopping (ETSI) and Digital Modulation (FCC) Supply-voltage Range 2.9V to 3.6V (Unregulated) Auxiliary Voltage Regulator on Chip (3.2V to 4.6V) Low Current Consumption Few Low-cost External Components Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier Low Profile Lead-free Plastic Package QFN32 (5 mm × 5 mm × 0.9 mm) RoHs Compliant Low-IF 2.4-GHz ISM Transceiver ATR2406 Applications • • • • • • • High-tech Multi-user Toys Wireless Game Controllers Telemetry Wireless Audio/Video Electronic Point of Sales Wireless Head Set FCC CFR47, Part 15, ETSI EN 300 328, EN 300 440 and ARIB STD-T-66 Compliant Radio Links 1. Description The ATR2406 is a single chip RF transceiver intended for applications in the 2.4-GHz ISM band. The QFN32-packaged IC is a complete transceiver including image rejection mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF transceiver offers a clock recovery function on-chip. 4779L–ISM–09/06 Figure 1-1. Block Diagram REG_DEC VREG REG_CTRL VS_REG IREF VS_SYN VREG_VCO VCO REG AUX REG AUX REG LNA IR-Mixer BP VS_IFD VS_IFA VS_RX/TX LIMITER RSSI RX_IN DEMOD RX_DATA RSSI PA VCO Divider by 2 TX_OUT BUS CLOCK DATA ENABLE TEST1 TEST2 RAMP_OUT RAMP GEN PLL PU_REG GAUSSIAN FILTER CTRL LOGIC PU_TRX RX_ON TX_ON nOLE CP REF_CLK TX_DATA VTUNE 2. Pin Configuration Pinning QFN32 - 5 × 5 ENABLE DATA CLOCK TX_DATA RX_DATA PU_TRX nOLE TX_ON Figure 2-1. 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 ATR2406 21 20 19 18 17 9 10 11 12 13 14 15 16 RX_ON IC IC RAMP_OUT TX_OUT RX_IN1 RX_IN2 VS_TRX REG_CTRL VREG VS_REG REG_DEC VREG_VCO VTUNE CP VS_SYN PU_REG REF_CLK RSSI VS_IFD VS_IFA RX-CLOCK IC IREF 2 ATR2406 4779L–ISM–09/06 ATR2406 Table 2-1. Pin Description Pin Symbol Function 1 PU_REG Power-up input for auxiliary regulator 2 REF_CLK Reference frequency input 3 RSSI 4 VS_IFD Digital supply voltage 5 VS_IFA Analog supply voltage for IF circuits 6 RX-CLOCK 7 IC 8 IREF External resistor for band-gap reference 9 REG_CTRL Auxiliary voltage regulator control output 10 VREG 11 VS_REG 12 REG_DEC 13 VREG_VCO 14 VTUNE Received signal strength indicator output RX-CLOCK, if RX mode with clock recovery is active Internally connected. Connect to VS if internal AUX regulator is not used Auxiliary voltage regulator output Auxiliary voltage regulator supply voltage Decoupling pin for VCO_REG VCO voltage regulator VCO tuning voltage input 15 CP 16 VS_SYN Synchronous supply voltage Charge-pump output 17 VS_TRX Transmitter receiver supply voltage 18 RX_IN2 Differential receiver input 2 19 RX_IN1 Differential receiver input 1 20 TX_OUT TX driver amplifier output 21 RAMP_OUT Ramp generator output for PA power ramping 22 IC Internally connected, do not connect on PCB 23 IC Internally connected, do not connect on PCB 24 RX_ON RX control input 25 TX_ON TX control input 26 nOLE Open loop enable input 27 PU_TRX RX/TX/PLL/VCO power-up input 28 RX_DATA RX data output 29 TX_DATA TX data input 30 CLOCK 3-wire-bus: Clock input 31 DATA 3-wire-bus: Data input 32 ENABLE Paddle GND 3-wire-bus: Enable input Ground 3 4779L–ISM–09/06 3. Functional Description 3.1 Receiver The RF signal at RF_IN is differentially fed through the LNA to the image rejection mixer IR_MIXER, driving the integrated low-IF band-pass filter. The IF frequency is 864 kHz. The limiting IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator DEMOD. No tuning is required. Data slicing is handled internally. 3.2 Clock Recovery For a 1152-kBit/s data rate, the receiver has a clock recovery function on-chip. The receiver includes a clock recovery circuit which regenerates the clock out of the received data. The advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data), which significantly reduces the load of the processing microcontroller. The falling edge of the clock is the optimal sampling position for the RX_Data signal, so at this event the data must be sampled by the microcontroller. The recovered clock is available at pin 6. 3.3 Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian filter (GF) and fed to the fully integrated VCO operating at twice the output frequency. After modulation, the signal is frequency divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typically +4 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled internally so that spurious requirements are fulfilled. 3.4 Synthesizer The IR_MIXER, the PA, and the programmable counter (PC) are driven by the fully integrated VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the desired frequency to the TX_DRIVER, the 0/90 degree phase shifter for the IR_MIXER, and to be used by the PC for the phase detector (PD) (fPD = 1.728 MHz). Open loop modulation is supported. 3.5 Power Supply An integrated band-gap–stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. 4 ATR2406 4779L–ISM–09/06 ATR2406 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage auxiliary regulator VS –0.3 +4.7 V Supply voltage VS –0.3 +3.6 V Vcontr –0.3 VS V Storage temperature Tstg –40 +125 °C Input RF level PRF +10 dBm VESD_ana TBD V VESD_dig TBD V Control voltages ESD protection Electrostatic sensitive device. Observe precautions for handling. 5. Operating Range Parameters Symbol Min. Max. Unit VS 2.9 3.6 V VS_BATT 3.2 4.6 V Temperature ambient Tamb –10 +60 °C Input frequency range fRX 2400 2483 MHz Supply voltage Auxiliary regulator supply voltage 5 4779L–ISM–09/06 6. Electrical Characteristics VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified No. 1 Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply 1.1 Supply voltage With AUX regulator VS 3.2 3.6 4.6 V 1.2 Supply voltage Without AUX regulator VS 2.9 3.0 3.6 V 1.3 RX supply current 1.4 TX supply current 1.5 Battery lifetime of a remote control application using an AVR® See Section 10. ”Appendix: Current Calculations for a Remote Control” on page 20 1.6 Supply current in power-down mode 1.7 Supply current in power-down mode 2 CW mode (peak current) IS 57 mA Burst mode at 10 Kbits/s(4) IS 625 µA CW mode (peak current) IS 42 mA Burst mode at 10 Kbits/s(4) IS 500 µA With AUX regulator PU_TRX = 0; PU_REG = 0 IS <1 µA Without AUX regulator PU_TRX = 0; PU_REG = 0 IS <1 µA Voltage Regulator 2.1 AUX regulator VREG 3.0 V 2.2 VCO regulator VREG_VCO 2.7 V 72/144/288/576/1152 kBits/s 3 Transmitter Part 3.1 TX data rate 3.2 Output power 3.3 TX data filter clock 9 taps in filter 3.4 Frequency deviation To be tuned by GFCS bits 3.5 Frequency deviation scaling(3) GFFM = GFFM_nom × GFCS (Refer to bus protocol D9 to D11) GFCS 3.6 Frequency drift With standard loop filter and slot length of 1400 µs (Refer to the application note “ATR2406 Loop Filter and Data Rates”) ∆fo (drift) 3.7 Harmonics BW = 100 kHz(1) 3.8 Spurious emissions 30 – 1000 MHz 1 – 12.75 GHz 1.8 – 1.9 GHz 5.15 – 5.3 GHz BW = 100 kHz(1) 4 PTX 4 dBm fTXFCLK 10.368/13.824 MHz GFFM_nom ±400 kHz 60 130 % ±40 kHz –41.2 dBm –57 –57 –57 –57 dBm dBm dBm dBm Ramp Generator, Pin 21 4.1 Minimum output voltage TX_ON = low Vmin 4.2 Maximum output voltage Refer to bus protocol D12 to D13 Vmax 0.7 1.1 V 1.9 V 4.3 Rise time tr 5 µs 4.4 Fall time tf 5 µs Notes: ® 1. Measured and guaranteed only on the Atmel evaluation board, including microstrip filter, balun, and Smart Radio Frequency (Smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. 4. Burst mode with 0.9% duty cycle 6 ATR2406 4779L–ISM–09/06 ATR2406 6. Electrical Characteristics (Continued) VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified No. 5 5.1 Parameters Test Conditions Symbol Min. Typ. Max. Unit Receiver Part RX input impedance Differential 5.2 Sensitivity At input for BER ≤ 10-3 at 1152 kBits/s(1) 5.3 Third order input intercept point Zin IIP3 170 + j0 Ω –93 dBm –15 dBm -3 5.4 Intermodulation rejection BER < 10 , wanted at -83 dBm, level of interferers in channels N + 2 and N + 4(1) IM3 32 dBc 5.5 Co-channel rejection BER < 10-3, wanted at –76 dBm(1) RCO –11 dBc 5.6 Adjacent channel rejection ±1.728 MHz BER < 10-3, wanted at –76 dBm, adjacent level referred to wanted channel level(1) Ri (N – 1) 14 dBc 5.7 Bi-adjacent channel rejection ±3.456 MHz BER < 10-3, wanted at –76 dBm, bi-adjacent level referred to wanted channel level(1) Ri (N – 2) 30 dBc 5.8 Rejection with ≥ 3 channels separation ≥ ±5.128 MHz BER < 10-3, wanted at –76 dBm, n ≥ 3 adjacent level referred to wanted channel level(1) Ri (n ≥ 3) 40 dBc 5.9 Out of band rejection > 6 MHz BER < 10-3, wanted at –83 dBm at 2.45 GHz(1) Bldf>6MHz 38 dBc Out of band rejection 5.10 2300 MHz to 2394 MHz 2506 MHz to 2600 GHz BER < 10-3, wanted at –83 dBm at 2.45 GHz(1) Blnear 47 dBc Out of band rejection 5.11 30 MHz to 2300 MHz 2600 MHz to 6 GHz BER < 10-3, wanted at –83 dBm at 2.45 GHz(1) Blfar 57 dBc 6 RSSI Part 6.1 Maximum RSSI output voltage 6.2 RSSI output voltage, monotonic With –33 dBm at RF input over range –96 dBm to –36 dBm With –96 dBm at RF input 7 Under high RX input signal level VRSSImax 2.1 V VRSSI 1.9 0.1 V V VCO 7.1 Oscillator frequency defined at TX output 7.2 Frequency control voltage range VVTUNE 7.3 VCO tuning input gain defined at TX output GVCO Notes: Over full temperature range(1) 2400 2483 MHz 0.5 VCC – 0.5 V 240 MHz/V 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Frequency (Smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. 4. Burst mode with 0.9% duty cycle 7 4779L–ISM–09/06 6. Electrical Characteristics (Continued) VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters 8 Synthesizer Test Conditions Symbol 8.1 External reference input frequency D7 = 0 D7 = 1 REF_CLK 8.2 Sinusoidal input signal level (peak-to-peak value) AC-coupled sine wave REF_CLK 8.3 Scaling factor prescaler SPSC 8.4 Scaling factor main counter SMC 8.5 Scaling factor swallow counter SSC 9 Min. Typ. 10.368 13.824 500 MHz MHz 1000 32/33 mVPP - 86/87/88/89 0 Unit 31 - Phase Detector 9.1 Phase detector comparison frequency 10 Charge-pump Output fPD 1728 kHz mA 10.1 Charge-pump output current VCP = 1/2 VCC ICP ±2 10.2 Leakage current VCP = 1/2 VCC IL ±100 11 Max. 1000 pA Timing Conditions(1)(2) 11.1 Transmit to receive time Reference clock stable TX → RX time 200 µs 11.2 Receive to transmit time Reference clock stable RX → TX time 200 µs 11.3 Channel switch time Reference clock stable CS time 200 µs 11.4 Power down to transmit Reference clock stable PD → TR time 250 µs 11.5 Power down to receive Reference clock stable PD → RX time 200 µs 11.6 Programming register Reference clock stable PRR time 3 µs 11.7 PLL settling time Reference clock stable PLL set time 200 µs 12 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE 12.1 HIGH-level input voltage Logic 1 VIH 1.4 3.1 V 12.2 LOW-level input voltage Logic 0 VIL –0.3 +0.4 V 3.1 V 12.3 HIGH-level output voltage Logic 1 VOH 12.4 LOW-level output voltage Logic 0 VOL 0 12.5 Input bias current Logic 1 or logic 0 Ibias –5 12.6 3-wire bus clock frequency Notes: fCLKmax V +5 µA 10 MHz 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Frequency (Smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. 4. Burst mode with 0.9% duty cycle 8 ATR2406 4779L–ISM–09/06 ATR2406 7. PLL Principle Figure 7-1. PLL Principle Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = 1728 kHz × (SMC × 32 + SSC) External loop filter PA driver Phase frequency detector PD fPD = 1728 kHz Charge pump VCO Divider by 2 Mixer Gaussian filter GF Reference counter RC REF_CLK D7 10.368 MHz 0 13.824 MHz 1 PLL reference Frequency REF_CLK TXDAT Baseband controller 9 4779L–ISM–09/06 Table 7-1 shows the LO frequencies for RX and TX in the 2.4-GHz ISM band. There are 95 channels available. Since the ATR2406 supports wideband modulation with 400-kHz deviation, every second channel can be used without overlap in the spectrum. Table 7-1. LO Frequencies Mode fIF / kHz Channel fANT / MHz fVCO / MHz divided by 2 SMC SSC N C0 2401.056 2401.056 86 27 2779 C1 2401.920 2401.920 86 28 2780 ... ... ... ... ... ... C93 2481.408 2481.408 89 24 2872 C94 2482.272 2482.272 89 25 2873 C0 2401.056 2401.920 86 28 2780 C1 2401.920 2402.784 86 29 2781 ... ... ... ... ... ... C93 2481.408 2482.272 89 25 2873 C94 2482.272 2483.136 89 26 2874 TX RX 7.1 864 TX Register Setting The following 16-bit word has to be programmed for TX. MSB LSB Data bits D15 D14 0 1 Note: D13 D12 D11 PA D10 GFCS D9 D8 D7 1 RC D6 D5 D4 MC D3 D2 D1 D0 SC D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0 or 1. Table 7-2. Output Power Settings with Bits D12 - D13 PA (Output Power Settings) D13 D12 RAMP_OUT (Pin 21) 0 0 1.3V 0 1 1.35V 1 0 1.4V 1 1 1.75V The VRAMP voltage is used to control the output power of an external power amplifier. The voltage ramp is started with the TX_ON signal. These bits are only relevant in TX mode. 10 ATR2406 4779L–ISM–09/06 ATR2406 7.2 RX Register Setting There are two RX settings possible. For a data rate of 1152 kBits/s, an internal clock recovery function is implemented. 7.3 Register Setting Without Clock Recovery Must be used for data rates below 1.152 Mbits/s. MSB LSB Data bits D15 D14 D13 D12 D11 D10 D9 D8 D7 0 1 X X X X X 0 RC D6 D5 D4 D3 MC Note: X values are not relevant and can be set to 0 or 1. 7.4 RX Register Setting with Internal Clock Recovery D2 D1 D0 SC Recommended for 1.152-Mbit/s data rate. The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal samples the data signal. MSB Data bits D24 D23 D22 D21 D20 D19 D18 D17 D16 1 0 1 0 0 0 0 0 0 LSB Data bits D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 X X X X X 0 RC Note: X values are not relevant and can be set to 0 or 1. 7.5 PLL Settings D6 D5 MC D4 D3 D2 D1 D0 SC RC, MC and SC bits control the synthesizer frequency as shown in Table 7-3, Table 7-4 on page 12 and Table 7-5 on page 12. Formula for calculating the frequency: TX frequency: fANT = 864 kHz × (32 × SMC + SSC) RX frequency: fANT = 864 kHz × (32 × SMC + SSC – 1) Table 7-3. PLL Settings of the Reference Counter Bit D7 RC (Reference Counter) D7 CLK Reference 0 10.368 MHz 1 13.824 MHz 11 4779L–ISM–09/06 Table 7-4. PLL Settings of the Main Counter Bits D5 to D6 MC (Main Counter) Table 7-5. D6 D5 SMC 0 0 86 0 1 87 1 0 88 1 1 89 PLL Settings of the Swallow Counter Bits D0 to D4 SC (Swallow Counter) 7.6 D4 D3 D2 D1 D0 SSC 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 ... ... ... ... ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 GFCS Adjustment The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. These bits are only relevant in TX mode. Table 7-6. GFCS Adjustment of Bits D9 - D11 GFCS 12 D11 D10 D9 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% ATR2406 4779L–ISM–09/06 ATR2406 7.7 Control Signals The various transceiver functions are activated by the following control signals. A timing proposal is shown in Figure 7-3 on page 14 Table 7-7. Control Signals and Functions Signal PU_REG Activates AUX voltage regulator and the VCO voltage regulator supplying the complete transceiver PU_TRX Activates RX/TX blocks RX_ON Activates RX circuits: DEMOD, IF AMP, IR MIXER TX_ON Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT nOLE 7.8 Functions Disables open loop mode of the PLL Serial Programming Bus The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE). After setting the enable signal to low, the data is transferred bit by bit into the shift register on the rising edge of the clock signal, starting with the MSBit. When the enable signal has returned to high, the programmed information is active. Additional leading bits are ignored and there is no check made of how many clock pulses arrived during enable low. The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock recovery mode). 7.9 3-wire Bus Timing Figure 7-2. 3-wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TC TPER TL TS Table 7-8. TEC TT TH 3-wire Bus Protocol Table Description Symbol Minimum Value Unit Clock period TPER 100 ns Set time data to clock TS 20 ns Hold time data to clock TH 20 ns Clock pulse width TC 60 ns Set time enable to clock TL 100 ns Hold time enable to data TEC 0 ns TT 250 ns Time between two protocols 13 4779L–ISM–09/06 RAMP_OUT Pin 21 connected to RAMP_IN of optional PA RSSI Pin 3 RX_DATA Pin 28 TX_ON Pin 25 RX_ON Pin 24 REF_CLK Pin 2 nOLE Pin 26 3W_ENA Pin 32 3W_DATA Pin 31 3W_CLK Pin 30 TX_DATA Pin 29 PU_TRX Pin 27 PU_REG Pin 1 Pin Name MODE Signals to TRX (Input) 14 Signals from TRX (Output) Note: > 40 µs Power-up C2 16/25 bits > 200 µs Programming C3 > 50 µs valid signal Data REF_CLK Active RX-slot C4 1. Keep input signals on low level during power-down state of TRX Power-down C1 Power-up optional Power-down optional > 40 µs C2 C1 16 bits > 200 µs Preamble (1-0-1-0) Programming C3 REF_CLK Data > 50 µs Active TX-slot C5 Power-down C1 VS 0V VS 0V Figure 7-3. Example TX and RX Timing Diagram ATR2406 4779L–ISM–09/06 ATR2406 Table 7-9. Description of the Conditions/States Condition 7.10 Description C1 Power down ATR2406 is switched off and the supply current is lower than 1 µA. C2 Power up ATR2406 is powered up by toggling PU_REG and PU_TRX to high. PU_REG enables the external AUX regulator transistor including VCO regulator. PU_TRX enables internal blocks like the PLL and the VCO. Depending on the value of the external capacitors (for example, at the AUX regulator, if one is used), it is necessary to wait at least 40 µs until the different supply voltages have settled. C3 Programming The internal register of the ATR2406 is programmed via the three-wire interface. At TX, this is just the PLL (transmit channel) and the deviation (Gaussian filter). At RX, this is just the PLL (receive channel) and, if the clock recovery is used, also the bits to enable this option. At the start of the three-wire programming, the enable signal is toggled from high to low to enable clocking the data into the internal register. When the enable signal rises again to high, the programmed data is latched. This is the time point at which the settling of the PLL starts. It is necessary to wait the settling time of 200 µs so that the VCO frequency is stable. The reference clock needs to be applied to ATR2406 for at least the time when the PLL is in operation, which is the programming state (C3) and the active slot (C4, C5). Out of the reference clock, several internal signals are also derived, for example, the Gaussian filter circuitry and TX_DATA sampling. C4 This is the receive slot where the transmit burst is received and data as well as recovered clock are available. C5 This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the signal nOLE toggles to low which enables modulation in open-loop mode. The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON. Received Signal Strength Indication (RSSI) The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is shown in Figure 7-4. Figure 7-4. Typical RSSI Value versus Input Power 2.5 RSSI Level (V) 2.0 1.5 1.0 0.5 0.0 -130 -110 -90 -70 -50 -30 -10 10 RF Level (dBm) 15 4779L–ISM–09/06 8. Application Circuit The ATR2406 requires only a few low-cost external components for operation. A typical application is shown in Figure 8-3 on page 17. 8.1 Typical Application Circuit Figure 8-1. Microcontroller Interfacing with General Purpose MCU, Pin Connections between Microcontroller and ATR2406 ATR2406 RF-DATA Interface Microcontroller TX_DATA RX_DATA RX-CLOCK Configuration and control ENABLE CLOCK DATA XTAL(1) Figure 8-2. Ctrl_Lines REF_CLK XTAL_OUT Example with AVR MCU AVR_MCU ATR2406 USART RF_DATA TXD TX_DATA RXD RX_DATA XCK GPIO GPIO2 GPIO3 GPIO4 GPIO5 13.824 MHz XTAL 16 RX-CLOCK RF_CTRL GPIO1 Note: R ENABLE CLOCK DATA nOLE TX_ON RX_ON PU_REG PU_TRX RSSI REF_CLK 1. XTAL: for example, XRFBCC-NANL; 13.824 MHz, 10 ppm Order at: Taitien Electronic, Taitien Specific No.: A009-x-B26-3, SMD ATR2406 4779L–ISM–09/06 4µ7 C13 100n C12 100n C15 4µ7 C16 C24 J2 RSSI VS T1 BC808 8 7 6 5 4 ENABLE IREF IC RX-CLOCK VS_IFA VS_IFD RSSI REF_CLK DATA 32 9 RX_DATA 27 30 ATR2406 VS_TRX RX_IN2 RX_IN1 TX_OUT RAMP C20, C21, COG dielectric 2n2 C21 TX_ON RAMP_OUT IC IC RX_ON 17 18 19 20 21 22 23 24 22n C20 RAMP_OUT RX_ON NC J26 TP2 TP1 µStrip C11 REF_CLK C23 VBATT µStrip-balun IC2P GND Slug REF_CLK 1p8 C10 1p5 C9 J8 J9 J10 CLOCK RX_ON RSSI J3 J4 J5 J6 J7 C6 VBATT TX_ON TX_DATA PU_TRX 2p2 18p 4p7 R3 µStrip Lowpassfilter 1k5 PU_REG 62k 4n7 CLOCK VS_REG 11 CLOCK 31 ENABLE REG_CTRL PU_TRX nOLE CP 15 5p6 1k5 R5 C3 TX_DATA 29 REG_DEC 12 C17 C18 DATA VREG 10 C19 28 TX_DATA 26 PU_TRX VTUNE 14 68p 25 TX_ON VS_SYN 16 nOLE GND G PU_REG C4 3 390p 2 R4 1 C14 IC2 1k0 RX_DATA VREG_VCO 13 NC 470n 2p2 C1 GND2 µStrip GND7 GND8 GND9 GND4 GND5 GND6 GND1 GND3 C7 R6 J24 J1 1p8 4779L–ISM–09/06 2 4 6 8 10 12 14 16 18 20 22 24 26 28 VLSI Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 27 J2 RX_DATA J17 J18 J19 J20 J21 ENABLE DATA nOLE PU_REG RX-CLOCK J12 J13 J14 J15 J16 GND ANT F-antenna VBATT ANT ANT2 J11 GND SMASI NC R2 Select integrated F-antenna or SMA connector by setting the 0R resistor R1 Figure 8-3. NC RFOUT (Ant) ATR2406 Application Circuit for ATR2406-DEV-BOARD 17 RX-CLOCK 9. PCB Layout Design Figure 9-1. 18 PCB Layout ATR2406-DEV-BOARD ATR2406 4779L–ISM–09/06 ATR2406 Table 9-1. Bill of Materials Part Value Part Number Vendor Package C1 5.6 pF GJM1555C1H5R6CB01 or GRM1555C1H5R6DZ01 Murata® 0402 C3, C10 1.8 pF GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata 0402 C4 390 pF GRM1555C1H391JA01 Murata 0402 C5 4.7 pF GJM1555C1H4R7CB01 or GRM1555C1H4R7CZ01 Murata 0402 C6, C7 2.2 pF GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata 0402 C9 1.5 pF GJM1555C1H1R5CB01 or GRM1555C1H1R5CZ01 Murata 0402 C11 18 pF GRM1555C1H180JZ01B Murata 0402 C12, C15 100 nF GRM155R71C104KA88B Murata 0402 C13, C16 4.7 µF B45196H2475M109 Epcos® 3216 Comment NC Optional(2) C14 1 nF GRM15R71H102KB01 Murata 0402 NC C17 3.3 nF GRM15R71H332KB01 Murata 0402 NC C18 68 pF GRM1555C1H680JZ01B Murata 0402 470 nF GRM18F51H474ZB01 (0402) or GRM188R61A474KA61B (0603) Murata 0402/0603 C19 C20 22 nF, COG GRM21B5C1H223JA01 Murata 0805 COG, important for good RF performance C21 2.2 nF, COG GRM1885C1H222JA01 Murata 0603 COG, important for good RF performance Murata 0402 C23 4.7 nF GRM155R71H472KA01B C24 4.7 pF GRM1555C1H4R7CZ01B Murata 0402 L6 8.2 nH WE-MK0402 744784082 Würth® Electronic 0402 NC, microstrip used R3 62 kΩ 62k, ≤ 5% Vishay 0402 R4 1.0 kΩ 1k0, ≤ 5% Vishay 0402 R5 1.5 kΩ 1k5, ≤ 5% Vishay 0402 Ref_Clk level, optional(1) R6 1.5 kΩ 1k5, ≤ 5% Vishay 0402 Ref_Clk level, optional(1) Atmel MLF32 Vishay, Philips®, etc. SOT-23 ® IC2 ATR2406 ATR2406 T1 BC808-40, any standard type can be used, but it is BC808-40 important that be “–40”! MSUB Notes: FR4 Optional(2) FR4, e_r = 4.4 at 2.45 GHz, H = 500 µm, T = 35 µm, tand = 0.02, surface, that is, chem. tin or chem. gold 1. Not necessary if supplied RefClk level is within specification range 2. If no AUX regulator is used, then T1 and C16 can be removed and a jumper is needed from the collector to the emitter pad. Additionally, pin 7 of the ATR2406 has to be connected to pin 4 or pin 5 to use the integrated F antenna, set jumper R2 (0R resistor 0603) Table 9-2. Parts Count Bill of Materials Parts Count Capacitors 0402 Required (Minimal BOM) Optional (Depending on Application) 14 14 Capacitors >0402 2 4 Resistors 0402 2 2 Inductors 0402 – – Semiconductors 1 2 19 4779L–ISM–09/06 10. Appendix: Current Calculations for a Remote Control Assumptions: Protocol A data packet consists of 24 bytes. 24 bytes = 240 bits (USART connection) Tpacket_length = 210 µs at 1.152 Mbits/s Channel The system will use five predefined channels for frequency hopping spread spectrum (FHSS) which gives improved immunity against interferers Loop filter Loop filter settling time will be 110 µs Handheld device If not in use, the handheld device will be in power-down mode with the AVR’s watchdog timer disabled. The AVR power-down current is typically 1.25 µA. If an external voltage regulator is used, additional power-down current has to be taken into account Base station device The base station will periodically scan all the channels of the used subset. The base station will stay on one channel for 2 seconds. If the base station receives a correct packet, an acknowledge will be returned to the handheld device. The power consumption of the base station device is not power-sensitive, as this part of the application is normally mains powered Basic Numbers: Peak current ATR2406 in TX at 1.152 Kbits/s 42 mA Peak current ATR2406 in RX at 1.152 Kbits/s 57 mA Peak current ATR2406 with synthesizer running 26 mA Current ATmega88 active 5 mA Current ATmega88 power down (no WDT) 1.25 µA Current ATmega88 power down (+ WDT) 5 µA Loop settling time of ATR2406 110 µs Configuration of ATR2406 30 µs Time needed for exchanging a packet at 1.152 Kbits/s 210 µs Amount of Current Needed to Transmit One Packet: Q1 = (0.005A + 0.026A) × 5030 µs = 155 µAs (charge up time ATR2406 + AVR internal calculations) Q2 = (0.005A + 0.026A) × 30 µs = 0.93 µAs (charge for configuring the ATR2406) Q3 = (0.005A + 0.026A) × 110 µs = 3.41 µAs (charge for settling the loop filter) Q4 = (0.005A + 0.042A) × 210 µs = 9.87 µAs (charge for transmitting the packet) Q5 = (0.005A) × 250 µs = 1.25 µAs (charge for turn around (TX to RX, RX to TX, etc.)) Q6 = (0.005A + 0.026A) × 30 µs = 0.93 µAs (charge for configuring the ATR2406) Q7 = (0.005A + 0.026A) × 60 µs = 1.86 µAs (charge for settling the loop filter) Q8 = (0.005A + 0.057A) × 50 µs = 3.10 µAs (charge until valid data can be received) Q9 = (0.005A + 0.057A) × 210 µs = 13.02 µAs (charge for receiving the packet) Q10 = (0.005A + 0.057A) × 50 µs = 3.1 µAs (charge for latency before receiving) 20 ATR2406 4779L–ISM–09/06 ATR2406 A successful packet exchange needs the following charge Q = Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 = 192.47 µAs As the described system is a FHSS system with 5 different channels, the system has to do this up to five times before the packet is acknowledged by the base station. The average will be 2.5 times. In the case of an interfered environment, some more retries may be required; therefore, it is assumed the factor will be 3. The power-up time is included only once, as the cycle will be completed without powering up and down the handheld in order to be as power efficient as possible. Average current needed for a packet exchange: 155 µAs + (37.5 µAs × 3) = 267.5 µAs If the device will be used 1000 times a day → 3.1 µA Average current in active mode: → System Power Down current: Current ATmega88: Current ATR2406: Current VREG (+ ShutDown): 1.25 µA 1.0 µA 2.75 µA Assumed average power-down current is 5 µA. → Overall power consumption is 8.1 µA It is assumed the system uses a small battery with a capacity of 100 mAh. This is 100.000 µAh. → Battery lifetime will be around: 12345 hours = 514 days = 1.4 years. The most important factor is to get the power-down current as low as possible! Example: Assume a system where the handheld is used just 10 times per day. → Iactive = 0.031 µA and assuming the power-down current of this device is just 4 µA. → I = 0.031 µA + 4 µA = 4.03 µA → Battery lifetime will be around 24807 hours = 1033 days = 2.83 years. → Power-down current is the main factor influencing the battery lifetime. 21 4779L–ISM–09/06 11. Ordering Information Extended Type Number ATR2406-PNQG ATR2406-DEV-BOARD ATR2406-DEV-KIT2 Package Remarks MOQ Taped and reeled, Pb-free 4000 – RF module 1 – Complete evaluation kit and reference design ATR2406 + ATmega88 1 QFN32 - 5x5 12. Package Information 22 ATR2406 4779L–ISM–09/06 ATR2406 13. Recommended Footprint/Landing Pattern Figure 13-1. Recommenced Footprint/Landing Pattern Table 13-1. Recommended Footprint/Landing Pattern Signs Sign Size A 3.2 mm B 1.2 mm C 0.3 mm a 1.1 mm b 0.3 mm c 0.2 mm d 0.55 mm e 0.5 mm 23 4779L–ISM–09/06 14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 24 Revision No. History 4779L-ISM-08/06 • Table “Electrical Characteristics” on pages 6 to 8 changed • Section 10 “Appendix: Current Calculations for a Remote Control” on pages 20 to 21 changed • Table “Ordering Information” on page 22 changed • Minor corrections to grammar and style throughout document 4779K-ISM-06/06 • Put datasheet in a new template • Table “Electrical Characteristics” on pages 6 to 8 changed • Section 10 “Appendix: Current Calculations for a Remote Control” on pages 20 to 21 added • Ordering Information on page 22 changed ATR2406 4779L–ISM–09/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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