MP7541B 15 V CMOS Multiplying 12-Bit Digital-to-Analog Converter FEATURES APPLICATIONS • • • • • • • • • • • • • • • ESD Protection: 2000 V Minimum Full Four Quadrant Multiplication Low Glitch Energy 12-Bit Linearity (End-Point) Guaranteed Monotonic. All Grades. All Temperatures. TTL/5 V CMOS Compatible Stable, More Accurate Segmented Architecture – 2.0 ppm/°C Typ. Gain Error Tempco – 0.2 ppm/°C Max. Linearity Tempco – Lowest Sensitivity to Output Amplifier Offset • Latch-Up Free Industrial Automation Automatic Test Equipment Disk Drive Servo Systems Digital/Synchro Conversion Programmable Gain Amplifiers Ratiometric A/D Conversion Function Generation Digitally Controlled Filters speed and excellent accuracy over temperature and time. The MP7541B’s outstanding features are: GENERAL DESCRIPTION Stability: Both Integral Non-Linearity (INL) and DifferentialNon-Linearity (DNL) are rated at 0.2 ppm/°C maximum. Monotonicity is guaranteed over the entire temperature range. Gain Temperature Coefficient (TCGE) is 2.0 ppm/°C typical. The MP7541B is a pin-compatible replacement which offers superior performance in latch-up and ESD protection versus the comparable 7541 and 7541A. The high ESD protection will reduce failures caused by mishandling. These devices are manufactured using patented advanced thin film resistors on a double metal CMOS process which result in ultra stable thin film and superior long life reliability and stability. The MP7541B incorporates a bit decoding technique yielding lower glitch, higher Lower Sensitivity to Output Amplifier Offset: Multiplying DACs provide an output current into a virtual ground of the output op amp. Additional linearity error caused by the op amp is reduced by a factor of 3 in the MP7541B versus conventional R-2R DACs. SIMPLIFIED BLOCK DIAGRAM VDD 40k 40k 40k 80k 80k RFB “1” “1” “1” “1” “1” “1” 10k IOUT1 VREF IOUT2 Switch Drivers 3-7 Decoder GND BIT 1 BIT 2 (MSB) BIT 3 BIT 4 Rev. 2.00 1 BIT 12 (LSB) MP7541B ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (LSB) Plastic Dip –40 to +85°C MP7541BKN –40 to +85°C 1/2 1/2 5 Plastic Dip MP7541BJN 1 8 SOIC –40 to +85°C 1 MP7541BKS –40 to +85°C 1/2 1/2 5 SOIC MP7541BJS 1 1 8 Ceramic Dip –55 to +125°C MP7541BTD* –55 to +125°C 1/2 1/2 5 Ceramic Dip MP7541BSD* 1 1 8 *Contact factory for non-compliant military processing PIN CONFIGURATIONS IOUT1 IOUT2 GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 See Packaging Section for Package Dimensions 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 IOUT1 IOUT2 GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 RFB VREF VDD BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 18 Pin PDIP, CDIP (0.300”) N18, D18 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 RFB VREF VDD BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 18 Pin SOIC (Jedec, 0.300”) S18 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 IOUT1 Current Output 1 10 BIT 7 Data Input Bit 7 2 IOUT2 Current Output 2 11 BIT 8 Data Input Bit 8 3 GND Ground 12 BIT 9 Data Input Bit 9 4 BIT 1 Data Input Bit 1 (MSB) 13 BIT 10 Data Input Bit 10 5 BIT 2 Data Input Bit 2 14 BIT 11 Data Input Bit 11 6 BIT 3 Data Input Bit 3 15 BIT 12 Data Input Bit 12 (LSB) 7 BIT 4 Data Input Bit 4 16 VDD Positive Power Supply 8 BIT 5 Data Input Bit 5 17 VREF Reference Input Voltage 9 BIT 6 Data Input Bit 6 18 RFB Internal Feedback Resistor Rev. 2.00 2 MP7541B ELECTRICAL CHARACTERISTICS VDD = + 15 V, VREF = +10 V, IOUT1 = IOUT2 = GND = 0 V Unless Otherwise Noted. Parameter Symbol Min N 12 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K, T J, S Differential Non-Linearity K, T J, S Gain Error K, T J, S 12 Bits INL LSB End Point Linearity LSB All grades monotonic over full temperature range. LSB Using Internal RFB +2 ppm/°C ∆Gain/∆Temperature +1/2 +1 +1/2 +1 +1/2 +1 +1/2 +1 +3 +6 +5 +8 DNL GE Gain Temperature Coefficient2 TCGE Power Supply Rejection Ratio PSRR 5 +50 +100 ppm/% |∆Gain/∆VDD| ∆VDD = + 5% ILKG 5 +10 +200 nA Digital Inputs = 0 or 5 V Output Leakage Current DYNAMIC PERFORMANCE2 RL=100Ω, CEXT=13pF µs Current Settling Time tS 0.65 1.0 AC Feedthrough at IOUT1 FT 1.0 mV p-p Glitch Energy Egl 500 nVs Propagation Delay tPD 60 ns Full scale change to 1/2 LSB VREF = 20 V p-p 10kHz, Sinewave 00--0 to 11--1 Input Change From 50% of digital input to 10% of final analog output current REFERENCE INPUT Input Resistance RIN 5 10 VIH VIL IINH, IINL 3.0 2.4 20 5 20 kΩ 0.8 +1.0 0.8 +1.0 V V µA 8.0 8.0 pF DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Input Leakage Current Input Capacitance2 Data CIN 3.0 ANALOG OUTPUTS2 Output Capacitance 100 50 50 100 COUT1 COUT1 COUT2 COUT2 pF pF pF pF DAC all 1’s DAC all 0’s DAC all 1’s DAC all 0’s V mA All Digital Inputs = 0 or 5 V POWER SUPPLY3 Functional Voltage Range2 Supply Current VDD IDD 4.5 16 1.0 Rev. 2.00 3 4.5 16 1.0 MP7541B ELECTRICAL CHARACTERISTICS (CONT’D) NOTES: 1 2 3 Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 850mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 11mW/°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V Digital Input Voltage to GND . . . . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 20mA for less than 100µs. APPLICATION NOTES Refer to Section 8 for Applications Information PERFORMANCE CHARACTERISTICS Graph 1. Linearity Error vs. Digital Input Code Rev. 2.00 4 MP7541B 18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S18 D 18 10 E H 9 h x 45° C A Seating Plane B e α A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.451 0.461 11.46 11.71 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.641 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 5 MP7541B 18 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N18 S 18 10 1 9 Q1 E1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN –– 0.200 –– MAX 5.08 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.845 0.925 21.46 23.50 E 0.295 0.325 7.49 8.26 E1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.040 0.098 1.02 2.49 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 6 C MP7541B 18 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D18 S S1 See Note 1 18 10 1 9 E1 E D Q Base Plane Seating Plane A L c e b INCHES SYMBOL A L1 b1 NOTES MILLIMETERS MIN MAX MIN MAX –– 0.200 –– 5.08 NOTES –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 0.960 –– 24.38 4 E 0.220 0.310 5.59 7.87 4 E1 0.290 0.320 7.37 8.13 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.070 0.381 1.78 3 S –– 0.098 –– 2.49 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α α Rev. 2.00 7 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7541B NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 8