PRELIMINARY • • PERFORMANCE (1.8 GHz) ♦ 36.5 dBm Linear Output Power ♦ 11 dB Power Gain ♦ Useable Gain to 9 GHz ♦ 47 dBm Output IP3 ♦ 19 dB Maximum Stable Gain ♦ 45% Power-Added Efficiency ♦ 10V Operation / Plated Source Thru-Vias FPD4000V 4W POWER PHEMT DRAIN BOND PAD (4X) GATE BOND PAD (4X) DESCRIPTION AND APPLICATIONS DIE SIZE (µm): 650 x 1300 DIE THICKNESS: 100 µm BONDING PADS (µm): >70 x 65 The FPD4000V is a discrete depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), optimized for power applications in L- and C-Bands. The FPD4000V includes Source plated thru-vias, and does not require wire bonds to the Source. Typical applications include drivers or output stages in PCS/Cellular base station transmitter amplifiers, as well as other power applications in WLL/WLAN amplifiers. • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1.8 GHz USING CW SIGNAL Power at 1dB Gain Compression P1dB VDS = 10V; IDS = 720 mA 35.5 36.5 10.0 11.0 dBm ΓS and ΓL tuned for Optimum IP3 Power Gain at dB Gain Compression G1dB VDS = 10V; IDS = 720 mA ΓS and ΓL tuned for Optimum IP3 Maximum Stable Gain MSG S21/S12 Power-Added Efficiency 3 -Order Intermodulation Distortion 19 dB 45 % -46 dBc PIN = 0dBm, 50Ω system PAE VDS = 10V; IDS = 750 mA ΓS and ΓL tuned for Optimum IP3 at 1dB Gain Compression rd VDS = 10 V; IDS = 720 mA IM3 ΓS and ΓL tuned for Optimum IP3 VDS = 10V; IDS = 720 mA POUT = 25.5 dBm (single-tone level) Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 3.6 A Transconductance GM VDS = 1.3 V; VGS = 0 V 2.4 S Gate-Source Leakage Current IGSO VGS = -3 V 70 170 µA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 8 mA 0.7 0.9 1.4 V Gate-Source Breakdown Voltage |VBDGS| IGS = 8 mA 6 8 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 8 mA 20 22 V Thermal Resistivity ΘCC See Note on following page 10 °C/W Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis 1.9 2.3 2.65 A Revised: 6/22/05 Email: [email protected] PRELIMINARY • RECOMMENDED OPERATING BIAS CONDITIONS Drain-Source Voltage: From 5V to 10V Quiescent Current: From 25% IDSS to 55% IDSS • ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Drain-Source Voltage VDS Gate-Source Voltage 4W POWER PHEMT Max Units -3V < VGS < +0V 12 V VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward or reverse current +25/-4 mA RF Input Power 2 Min PIN Under any acceptable bias state 1.5 W Channel Operating Temperature TCH Under any acceptable bias state 175 ºC Storage Temperature TSTG Non-Operating Storage 150 ºC Total Power Dissipation PTOT See De-Rating Note below 15.0 W Comp. Under any bias conditions 5 dB 2 or more Max. Limits 80 % Gain Compression 3 Simultaneous Combination of Limits 1 3 FPD4000V TAmbient = 22°C unless otherwise noted -40 2 Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes: • Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. • Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. • Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power • Absolute Maximum Power Dissipation to be de-rated as follows above 22°C: PTOT= 15.0W – (0.10W/°C) x THS where THS = heatsink or ambient temperature above 22°C Example: For a 85°C heatsink temperature: PTOT = 15.0W – (0.10 x (85 – 22)) = 8.7W • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. This product has be tested to Class 1A (> 250V but < 500V) using JESD22 A114, Human Body Model, and to Class A, (< 200V) using JESD22 A115, Machine Model.. • ASSEMBLY INSTRUCTIONS The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290°C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 1.0 mil (0.025 mm) gold wire. Stage temperature should be 250-260°C. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 6/22/05 Email: [email protected] PRELIMINARY FPD4000V 4W POWER PHEMT • APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. • BONDING DIAGRAM Note: 25 µm (0.001 in.) gold wire is recommended. No Source wire bonds are needed, device features Source thru-vias. All information and specifications are subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 6/22/05 Email: [email protected]