TI SN75HVD08DRG4

SN75HVD08, SN65HVD08
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
WIDE SUPPLY RANGE RS-485 TRANSCEIVER
FEATURES
•
•
•
•
•
•
•
Operates With a 3-V to 5.5-V Supply
Consumes Less Than 90 mW Quiescent
Power
Open-Circuit, Short Circuit, and Idle-Bus
Failsafe Receiver
1/8th Unit-Load (up to 256 nodes on the bus)
Bus-Pin ESD Protection Exceeds 16 kV HBM
Driver Output Voltage Slew-Rate Limited for
Optimum Signal Quality at 10 Mbps
Electrically Compatible With ANSI
TIA/EIA-485 Standard
The driver differential outputs and receiver
differential inputs connect internally to form a
differential input/output (I/O) bus port that is designed
to offer minimum loading to the bus whenever the
driver is disabled or not powered. The drivers and
receivers have active-high and active-low enables
respectively, which can be externally connected
together to function as a direction control.
D or P PACKAGE
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
APPLICATIONS
•
•
•
•
•
Data Transmission With Remote Stations
Powered From the Host
Isolated Multipoint Data Buses
Industrial Process Control Networks
Point-of-Sale Networks
Electric Utility Metering
DESCRIPTION
LOGIC DIAGRAM (Positive Logic)
A
D
B
DE
RE
R
The SN65HVD08 combines a 3-state differential line
driver and differential line receiver designed for
balanced data transmission and interoperation with
ANSI
TIA/EIA-485-A
and
ISO-8482E
standard-compliant devices.
The wide supply voltage range and low quiescent
current requirements allow the SN65HVD08s to
operate from a 5-V power bus in the cable with as
much as a 2-V line voltage drop. Busing power in the
cable can alleviate the need for isolated power to be
generated at each connection of a ground-isolated
bus.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
SN75HVD08, SN65HVD08
www.ti.com
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
Remote
(One of n Shown)
Host
5 V Power
Isolation
Barrier
Direct
Connection
to Host
SN65HVD08
5 V Return
Power Bus and Return Resistance
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
SPECIFIED TEMPERATURE
RANGE
PACKAGE
SN65HVD08D
–40°C to 85°C
SOIC
VP08
SN65HVD08P
–40°C to 85°C
PDIP
65HVD08
SN75HVD08D
0°C to 70°C
SOIC
VN08
SN75HVD08P
0°C to 70°C
PDIP
75HVD08
PART NUMBER
PACKAGE MARKING
PACKAGE DISSIPATION RATINGS
TA≤ 25°C POWER RATING
DERATING FACTOR ABOVE TA = 25°C
TA = 85°C POWER RATING
SOIC (D)
710 mW
5.7 mW/°C
369 mW
PDIP (P)
1000 mW
8 mW/°C
520 mW
PACKAGE
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1) (2)
UNIT
Supply voltage, VCC
-0.3 V to 6 V
Voltage range at A or B
-9 V to 14 V
Input voltage range at D, DE, R or RE
-0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω
-25 V to 25 V
Receiver ouput current, IO
Electrostatic discharge
–11 mA to 11 mA
Human Body Model
(3)
Charged-Device Model (4)
A, B, and GND
16 kV
All pins
4 kV
All pins
Continuous total power dissipation
(1)
(2)
(3)
(4)
2
1 kV
See Dissipation Rating Table
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VCC
Low-level input voltage, VIL
Driver, driver enable, and receiver enable inputs
Low-level output current, IOL
Operating free-air temperature, TA
(1)
UNIT
3
5.5
V
12
V
2.25
VCC
0
0.8
–12
12
Differential input voltage, VID
High-level output current, IOH
MAX
–7
Input voltage at any bus terminal (separately or common mode), VI (1)
High-level input voltage, VIH
NOM
Driver
–60
Receiver
V
mA
–8
Driver
60
Receiver
8
SN75HVD08
0
70
SN65HVD08
–40
85
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
|VOD|
Driver differential output voltage magnitude
RL= 60 Ω, 375 Ω on each output to
-7 V to 12 V, See Figure 1
∆|VOD|
Change in magnitude of driver differential
output voltage
RL= 54 Ω
VOC(PP)
Peak-to-peak driver common-mode output
voltage
Center of two 27-Ω load
resistors, See Figure 2
VIT+
Positive-going receiver differential input
voltage threshold
VIT-
Negative-going receiver differential input
voltage threshold
Vhys
Receiver differential input voltage threshold
hysteresis(VIT+ - VIT-)
VOH
Receiver high-level output voltage
IOH = -8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
IIH
Driver input, driver enable, and receiver
enable high-level input current
IIL
Driver input, driver enable, and receiver
enable low-level input current
IOS
Driver short-circuit output current
MIN
MAX
UNIT
1.5
VCC
V
–0.2
0.2
V
0.5
Bus input current (disabled driver)
–200
7 V < VO < 12 V
VI = -7 V
Supply current
mV
2.4
V
0.4
V
–100
100
µA
–100
100
µA
–265
265
mA
130
–100
VI = 12 V, VCC = 0 V
130
10
Driver enabled, receiver
disabled, no load
16
Both enabled, no load
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µA
–100
Receiver enabled, driver
disabled, no load
Both disabled
mV
mV
35
VI = -7 V. VCC = 0 V
ICC
V
–10
VI = 12 V
II
TYP
mA
5
µA
16
mA
3
SN75HVD08, SN65HVD08
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPHL
Driver high-to-low propagation delay time
18
40
tPLH
Driver low-to-high propagation delay time
18
40
tr
Driver 10%-to-90% differential output rise time
10
55
tf
Driver 90%-to-10% differential output fall time
10
55
tSK(P)
Driver differential output pulse skew, |tPHL - tPLH|
ten
Driver enable time
tdis
Driver disable time
RL = 54 Ω, CL = 50 pF,See Figure 3
UNIT
ns
2.5
Receiver enabled, See Figures 4 and 5
55
ns
Receiver disabled, See Figures 4 and 5
6
µs
Receiver enabled, See Figures 4 and 5
90
ns
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPHL
Receiver high-to-low propagation delay time
70
tPLH
Receiver low-to-high propagation delay time
70
tr
Receiver 10%-to-90% differential output rise time
tf
Receiver 90%-to-10% differential output fall time
tSK(P)
Receiver differential output pulse skew, |tPHL - tPLH|
ten
Receiver enable time
tdis
Receiver disable time
CL = 15 pF, See Figure 6
5
UNIT
ns
5
4.5
Driver enabled, See Figure 7
15
ns
Driver disabled, See Figure 8
6
µs
Driver enabled, See Figure 7
20
ns
PARAMETER MEASUREMENT INFORMATION
375 Ω ±1%
VCC
DE
D
A
VOD
0 or 3 V
60 Ω ±1%
+
_
B
–7 V < V(test) < 12 V
375 Ω ±1%
Figure 1. Driver VOD With Common-Mode Loading Test Circuit
VCC
DE
Input
D
27 Ω ± 1%
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
A
CL = 50 pF ±20%
VOC
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
Figure 2. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
4
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
3V
VCC
DE
D
Input
Generator
VI
VOD
tPLH
CL Includes Fixture
and Instrumentation
Capacitance
RL = 54 Ω
± 1%
B
50 Ω
1.5 V
VI
CL = 50 pF ±20%
A
1.5 V
tPHL
90%
VOD
≈2V
90%
0V
10%
0V
10%
≈ –2 V
tr
tf
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 3. Driver Switching Test Circuit and Voltage Waveforms
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
50 Ω
RL = 110 Ω
± 1%
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
0V
0.5 V
tPZH
VOH
VO
2.3 V
≈0V
tPHZ
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 4. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
3V
A
3V
D
VI
≈3V
1.5 V
VI
S1
1.5 V
VO
DE
Input
Generator
RL = 110 Ω
± 1%
50 Ω
0V
B
tPZL
tPLZ
≈3V
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
0.5 V
VO
2.3 V
VOL
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 5. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A
R
Input
Generator
50 Ω
VI
VO
B
1.5 V
CL = 15 pF ±20%
RE
0V
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
1.5 V
VI
1.5 V
0V
tPLH
tPHL
VOH
90% 90%
VO
1.5 V
10%
1.5 V
10% V
OL
tr
tf
Figure 6. Receiver Switching Test Circuit and Voltage Waveforms
3V
VCC
A
DE
0 V or 3 V
R
D
B
RE
Input
Generator
VI
A
1 kΩ ± 1%
VO
S1
CL = 15 pF ±20%
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
VI
1.5 V
1.5 V
0V
tPZH
tPHZ
VOH –0.5 V
VOH
D at 3 V
S1 to B
1.5 V
VO
≈0V
tPZL
tPLZ
≈ VCC
VO
1.5 V
VOL +0.5 V
D at 0 V
S1 to A
VOL
Figure 7. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
6
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
A
0 V or 1.5 V
R
B
1.5 V or 0 V
VI
S1
CL = 15 pF ±20%
RE
Input
Generator
A
1 kΩ ± 1%
VO
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
VI
1.5 V
0V
tPZH
VOH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
VO
GND
tPZL
≈ VCC
VO
1.5 V
A at 0 V
B at 1.5 V
S1 to A
VOL
Figure 8. Receiver Enable Time From Standby (Driver Disabled)
DEVICE INFORMATION
Function Tables
DRIVER
INPUT
ENABLE
OUTPUTS
D
DE
A
H
L
X
Open
H
H
L
H
H
L
Z
H
B
L
H
Z
L
RECEIVER
(1)
DIFFERENTIAL INPUTS
ENABLE (1)
OUTPUT (1)
VID = VA - VB
RE
R
VID≤ -0.2 V
-0.2 V < VID < -0.01 V
-0.01 V ≤ VID
X
Open Circuit
Short Circuit
L
L
L
H
L
L
L
?
H
Z
H
H
H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
16 V
100 kΩ
16 V
36 kΩ
180 kΩ
180 kΩ
Input
Input
16 V
36 kΩ
36 kΩ
100 kΩ
16 V
A and B Outputs
36 kΩ
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
8
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
4
70
D and DE at VCC
RL = 54 Ω
60
I O – Driver Output Current – mA
3.5
Differential Output Voltage – V
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
TA = –40°C
TA = 25°C
3
TA = 85°C
2.5
2
1.5
50
40
30
20
10
1
2.5
3
3.5
4
4.5
5
VCC – Supply Voltage – V
5.5
0
6
0
Figure 9.
Logic Input Threshold Voltage – V
I CC – RMS Supply Current – mA
TA = 25°C
D, DE or RE input
80
60
40
2.5
5
5.4
2.5
100
0
4.8
LOGIC INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
RL = 54 Ω
CL = 50 pF
VCC = 5 V
TA = 25°C
RE at VCC
DE at VCC
1.2 1.8 2.4
3
3.6 4.2
VCC – Supply Voltage – V
Figure 10.
RMS SUPPLY CURRENT
vs
SIGNALING RATE
120
0.6
7.5
10
2
Positive Going
1.5
Negative Going
1
0.5
0
2.5
Signaling Rate – Mbps
Figure 11.
3.5
4.5
5.5
VCC – Supply Voltage – V
6.5
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
ENABLE TIME
vs
COMMON-MODE VOLTAGE (SEE Figure 14)
500
450
400
Enable Time − ns
350
3.3 V
300
250
5V
200
150
100
50
0
-7
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 13.
375 W ± 1%
Y
D
0 or 3 V
-7 V < V(TEST) < 12 V
VOD
60 W
± 1%
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Figure 14. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
10
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SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
APPLICATION INFORMATION
As electrical loads are physically distanced from their
power source, the effects of supply and return line
impedance and the resultant voltage drop must be
accounted. If the supply regulation at the load cannot
be maintained to the circuit requirements, it forces
the use of remote sensing, additional regulation at
the load, bigger or shorter cables, or a combination
of these. The SN65HVD08 eases this problem by
relaxing the supply requirements to allow for more
variation in the supply voltage over typical RS-485
transceivers.
SUPPLY SOURCE IMPEDANCE
In the steady state, the voltage drop from the source
to the load is simply the wire resistance times the
load current as modeled in Figure 15.
RS
IL
+
+
RL
VL = VS – 2RSIL
VS
–
RS
–
Figure 15. Steady-State Circuit Model
For example, if you were to provide 5-V ±5% supply
power to a remote circuit with a maximum load
requirement of 0.1 A (one SN65HVD08), the voltage
at the load would fall below the 4.5-V minimum of
most 5-V circuits with as little as 5.8 m of 28-GA
conductors. Table 1 summarizes wire resistance and
the length for 4.5 V and 3 V at the load with 0.1 A of
load current. The maximum lengths would scale
linearly for higher or lower load currents.
not be ignored and decoupling capacitance at the
load is required. The amount depends upon the
magnitude and frequency of the load current change
but, if only powering the SN65HVD08, a 0.1 µF
ceramic capacitor is usually sufficient.
OPTO-ISOLATED DATA BUSES
Long RS-485 circuits can create large ground loops
and pick up common-mode noise voltages in excess
of the range tolerated by standard RS-485 circuits. A
common remedy is to provide galvanic isolation of
the data circuit from earth or local grounds.
Transformers, capacitors, or phototransistors most
often provide isolation of the bus and the local node.
Transformers and capacitors require changing
signals to transfer the information over the isolation
barrier and phototransistors (opto-isolators) can pass
steady-state signals. Each of these methods incurs
additional costs and complexity, the former in clock
encoding and decoding of the data stream and the
latter in requiring an isolated power supply.
Quite often, the cost of isolated power is repeated at
each node connected to the bus as shown in
Figure 16. The possibly lower-cost solution is to
generate this supply once within the system and then
distribute it along with the data line(s) as shown in
Figure 17.
DC-to-DC
Converter
Opto
Isolators
Local Power
Source
Rest of
Board
Table 1. Maximum Cable Lengths for Minimum
Load Voltages at 0.1 A Load
WIRE
SIZE
RESISTANCE
4.5 V LENGTH
AT 0.1 A
3-v LENGTH
AT 0.1 A
28 Gage
0.213 Ω/m
5.8 m
41.1 m
24 Gage
0.079 Ω/m
15.8 m
110.7 m
22 Gage
0.054 Ω/m
23.1 m
162.0 m
20 Gage
0.034 Ω/m
36.8 m
257.3 m
18 Gage
0.021 Ω/m
59.5 m
416.7 m
Under dynamic load requirements, the distributed
inductance and capacitance of the power lines may
DC-to-DC
Converter
Opto
Isolators
Local Power
Source
Rest of
Board
Figure 16. Isolated Power at Each Node
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The features of the SN65HVD08 are particularly
good for the application of Figure 17. Due to added
supply source impedance, the low quiescent current
requirements and wide supply voltage tolerance
allow for the poorer load regulation.
Local Power
Source
Opto
Isolators
Rest of
Board
AN OPTO ALTERNATIVE
The ISO150 is a two-channel, galvanically isolated
data coupler capable of data rates of 80 Mbps. Each
channel can be individually programmed to transmit
data in either direction.
SN65HVD08
Data is transmitted across the isolation barrier by
coupling complementary pulses through high-voltage
0.4-pF capacitors. Receiver circuitry restores the
pulses to standard logic levels. Differential signal
transmission
rejects
isolation-mode
voltage
transients up to 1.6 kV/ms.
Local Power
Source
Opto
Isolators
Rest of
Board
ISO150 avoids the problems commonly associated
with opto-couplers. Optically-isolated couplers
require high current pulses and allowance must be
made for LED aging. The ISO150's Bi-CMOS
circuitry operates at 25 mW per channel with supply
voltage range matching that of the SN65HVD08 of 3
V to 5.5 V.
Figure 17. Distribution of Isolated Power
Figure 18 shows a typical circuit.
–5 V
+5 V
Data
(I/O)
SN65HVD08
D
D2A
R/T2A
GA
ISO150
VSB
R/T2B
D2B
DE
Channel 1
RE
R
Side A
Side B
Channel 2
D1A
R/T1A
VSA
GA
R/T1B
D1B
DE/RE
+5 V
“1”
+5 V
Figure 18. Isolated RS-485 Interface
12
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A
B
Bus
PACKAGE OPTION ADDENDUM
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8-Jan-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD08D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD08DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD08DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD08DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD08P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65HVD08PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75HVD08D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD08DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD08DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD08DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD08P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75HVD08PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD08DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75HVD08DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD08DR
SOIC
D
8
2500
340.5
338.1
20.6
SN75HVD08DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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