www.fairchildsemi.com TMB22153AMS100 Demonstration Board for the TMC22x5yA Multistandard Digital Video Decoder Description • • • • • The TMB22153AMS100 Demonstration Board showcases the TMC22x5yA Digital Video Decoder. The onboard MMC FE-100 dual 10-bit A/D modules generate digitized composite or YC for the decoder. The decoder outputs D1, digital RGB, or YCBCR. Clocks and synchronization pulses are generated by Fairchild’s TMC2072 Genlocking Video Digitizer. Accepts analog composite or YC Outputs 10-bit digital RGB, D1, or YCBCR Locks to studio reference R-bus serial interface compatibility Raytheon demo board compatibility Applications • • • • Evaluation of TMC22x5yA Digital Video Decoder Input for Genesis 10-bit Line Doubler board Input for DAC and encoder demo boards System Breadboarding Related Products • • • • • TMC2069P7C DAC demonstration board TMC2074P7C Encoder demonstration board TMB2193MS100 Encoder demonstration board TMC2070P7C R-bus interface board Raydemo software Block Diagram Analog signals D.C. supply Digital signals RBUS FE-100x-1 TMC2072 96 way Edge Connector (male) Composite/Luma video input Micro (top) FPGA (bottom) Y/C video input FE-100x-2 Chroma video input Framestore Connector TMC22153A SW1 10 bit G/Y 10 bit B/U 10 bit R/V or D1 PXCK clock HSYNC VSYNC SYNC\ (D/A signals) BLANK\ (D/A signals) TMB22153AMS100 Rev. 001 PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information. Preliminary Information Features Preliminary Information TMB22153AMS100 PRELIMINARY INFORMATION Functional Description TMC2072 Genlocking Video Digitizer The TMB22153AMS100 is designed to demonstrate the performance of the TMC22x5yA Digital Video Decoder. For complete descriptions of the TMC22x5yA, TMC2072, TMC1185, and TMC2242 please refer to part datasheets. The TMB22153AMS100 is designed to be used in conjunction with other Fairchild demo boards, namely the TMC2069P7C DAC, and TMB2193MS100 encoder boards. The 96 pin edge connectors plug easily into each other. When used together, the boards demonstrate a high performance 10-bit digital video decoding system. The TMC2072 Genlocking Video Digitizer accepts analog composite data through the composite input BNC on the left side of the board. A 20MHz clock crystal provides the Genlock with an input clock. The TMC2072 outputs horizontal and vertical syncs, and a 27MHz clock. The clock is used to drive the Decoder and EPLD. Like the TMC22x5yA, the Genlock part must be programmed at startup. Instructions on how to do this are in the “Microcontroller” section of this documentation. TMC22x5yA Digital Video Decoder An Altera EPF10K10TC144-4 EPLD executes several essential board functions. The EPLD serves as a buffer and multiplexer for data buses and a register for several important control signals. These signals may be cross-referenced to the included schematics. The EPLD control registers may be modified using the Raydemo software. The Raydemo EPLD R-bus address is 0000001. For a more complete description or specification of signals going to or coming from the TMC22x5yA and TMC2072, please refer to the Fairchild Semiconductor Data Book (also available on CDROM) or the website at www.fairchildsemi.com. The TMC22x5yA accepts digitized video input on two 10-bit buses, “YOVER[9:0]” and “COVER[9:0]”. Based on the status of its control registers, it then outputs the data to the output edge connector of the board in a variety of formats. Please see Table 1 for a listing of board default video standards and output formats that are loadable to the control registers. After the TMC22x5yA control registers have been initially loaded by the microcontroller, subsequent changes to the control registers may be made through the R-bus interface and Raydemo software. It is important that the control registers be loaded correctly in order to obtain the desired output. Once the control registers have been set to output the correct data from the TMC22x5yA, then several board switches must also be correctly configured in order to obtain the desired output. EPLD Microcontroller An Atmel 89C55 microcontroller is used to program the TMC22x5yA and TMC2072 registers. The microcontroller programs the parts through the R-bus at power up and reprograms them each time the “Reset” button is pushed. Please see Table 1 on the next page for a description of available microcontroller-programmed board configurations. Table 1. TMB22153AMS100 Demonstration Board Video Standard Selection P3-0 Input Format Video Standard Output Format 0000 composite NTSC YUV 0001 Y/C NTSC YUV 0010 composite NTSC D1 0011 Y/C NTSC D1 0100 composite NTSC RGB 0101 composite, field-based NTSC YUV 0110 composite, field-based NTSC D1 0111 composite, frame-based NTSC YUV 1000 composite PAL YUV 1001 Y/C PAL YUV 1010 composite PAL D1 1011 Y/C PAL D1 1100 composite PAL RGB 1101 composite, field-based PAL YUV 1110 composite, field-based PAL D1 1111 reserved 2 PRELIMINARY INFORMATION TMB22153AMS100 4. Ensure BNC J1 (VIN1) is connected to composite NTSC signal. 1. Configure jumpers: 5. If using R-Bus interface, JP2 must be closed (connected) Ensure piano-key switches P3-0, Y are in the “LOW” (down) position. 6. Plug in power-supply connector and apply power. LED’s corresponding to applied voltages should lightup. 7. Press and release the MRST button (S2). The TMC2072 and TMC22x5yA should both be programmed. To verify the TMC2072 is functioning correctly, check for presence of a clock (TP sync pulses, VS (TP18) and HS (TP17). Likewise, to verify the TMC22x5yA is functioning, check for presence of DHSYNC (TP5) and DVSYNC (TP6). Leave JP1 open (unconnected) Verify that JP4 is linked to the odd-numbered pins of JP6 2. 3. Configure slider-switches (push red slider TOWARD specified marking on board) : E1 “FPGA” E2 “FPGA” E3 “VS” E4 “PXCK4\” Power Supply Requirements E5 “GP” E6 “GH” E7 “GV” The TMB22153AMS100 power supply connector is on the top edge of the board toward the left side. The TMB22153AMS100 board requires DC power supply voltages of +5V and -5V. E8 “XP” The +5V supply provides power and voltage references to the TMC22x5yA and /TMC2072, as well as driving TTL logic devices. It is for this reason that a bench power supply with short cable lengths is recommended. If you have reason to believe the bottom cover has been removed, remove it and configure S4 as follows: 1-7 ON (low) 8 OFF (high) 3 Preliminary Information Quick Setup/Verification for Composite NTSC Input, YUV Output 4 RESET\ 135MHZ COE10 YOE10 CLAMP ADCLK1 ADCLK2 MCU RESET 135MHZ MCU YOVER[0..9] SDA SCL DRST GRST AN COMP/LUMA COVER[0..9] YOVER[0..9] SDA SCL DRST\ GRST\ PGM_OUT PGM_START AN COMP/LUMA COVER[0..9] PGM_OUT PGM_START SMA MODULES COE10 YOE10 CLAMP ADCLK1 ADCLK2 SMA MODULES GRST\ SA0 SA1 SA2 SDA SCL FPGA PGM_START CVBS[0..7] 675MHZ DECCLK AVOUT HS VS DHSYNC DVSYNC SWW SDA SCL FPGA CVBS[0..7] CLAMP PGM_OUT D1ENFS FSOE FSER DCSB DA1 DA0 DRW YOE10 COE10 BUFFER MASTER0 MASTER1 OHS OVS MPU[0..7] COVER[0..9] YOVER[0..9] SDA SCL VALID GPXCK GHSYNC GVSYNC CVBS[0..7] FSET HREF CREF VREF RGB BLANK(DAC) NTSC/PAL D1 AN COMP/LUMA GRST GENLOCK PGM_START 675MHZ DECCLK AVOUT HS VS DHSYNC DVSYNC SWW SA0 SA1 SA2 SDA SCL AN COMP/LUMA GENLOCK CKDRIVE IXPXCK IXHSYNC IXVSYNC GPXCK GHSYNC GVSYNC CKDRIVE FSET HREF CREF VREF RGB BLANK\(DAC) NTSC/PAL D1 CLAMP PGM_OUT D1ENFS FSOE FSER DCSB DA1 DA0 DRW YOE10 COE10 BUFFER MASTER0 MASTER1 OHS OVS MPU[0..7] COVER[0..9] YOVER[0..9] VALID GPXCK GHSYNC GVSYNC IXPXCK IXHSYNC\ IXVSYNC\ GPXCK GHSYNC GVSYNC FSIN_CLK ADCLK1 ADCLK2 DICECLK DECCLK HS VS POWER POWER FSIN_CLK ADCLK1 ADCLK2 DICECLK SDA SCL FSOE FSER FSIN_CLK RESET\ SCL SDA HS VS SA2 SA1 SA0 SWW FID_0 AVOUT DVSYNC DHSYNC RV[0..9] BU[0..9] GY[0..9] FRAMESTORE CONNECTOR D1ENFS FSOE FSER IXPXCK IXHSYNC IXVSYNC COVER[0..9] FSIN_CLK RESET SCL SDA HS VS YOVER[0..9] FRAMESTORE CONNECTOR DECODER SDA SCL DRW MPU[0..7] DA0 DA1 DCSB DRST FSET BUFFER MASTER0 MASTER1 DECCLK HS VS YOVER[0..9] DRW MPU[0..7] DA0 DA1 DCSB DRST\ FSET BUFFER MASTER0 MASTER1 DECCLK HS VS COVER[0..9] YOVER[0..9] DECODER Preliminary Information IXPXCK IXHSYNC\ IXVSYNC\ COVER[0..9] SA2 SA1 SA0 SWW FID_0 AVOUT DVSYNC DHSYNC RV[0..9] BU[0..9] GY[0..9] FID_0 HREF CREF VALID VREF NTSC/PAL PGM_OUT RGB D1 BLANK\(DAC) RESET\ SCL SDA OHS OVS GY[0..9] BU[0..9] RV[0..9] IXHSYNC\ IXVSYNC\ NTSC/PAL PGM_OUT RGB D1 VALID VREF HREF CREF BLANK\(DAC) RESET\ DICECLK SCL SDA OHS OVS Y[0..9] OP-CONN FID_0 HREF CREF VALID VREF NTSC/PAL PGM_OUT RGB D1 BLANK(DAC) RESET SCL SDA OHS OVS MPU[0..4] GY[0..9] BU[0..9] RV[0..9] OP-CONN SIGNAL HEADER IXHSYNC IXVSYNC NTSC/PAL PGM_OUT RGB D1 VALID VREF HREF CREF FID_0 BLANK(DAC) RESET DICECLK SCL SDA OHS OVS Y[0..9] RV[0..9] BU[0..9] Y[0..9] 135MHZ 675MHZ IXPXCK EDGE CONNECTOR Y[0..9] 135MHZ 675MHZ IXPXCK TMB22153AMS100 PRELIMINARY INFORMATION 5 SA0 SA1 SA2 SDA SCL 0.1uF C21 VCC GRST\ AN COMP/LUMA R2 75 20MHz Y1 SA0 SA1 SA2 SDA SCL OUT GRST\ R3 75 R1 75 5 20MCLK 22uF/6.3v C11 VCC R5 4.75K VCC R6 4.75K 22uF/6.3v + H3 1 C2 0.1uF C1 0.1uF 0.1uF C5 AGND TMC2072KHC NC NC NC NC NC NC NC NC NC PXCK SEL EXT PXCK CLK IN CLK OUT SA0 SA1 SA2 SDA SCL RESET VIN1 VIN2 VIN3 NC NC NC NC NC NC NC NC NC NC NC U1 0.1uF C4 DGND 53 54 56 59 62 66 71 76 78 86 94 91 93 1 2 3 4 5 7 65 61 58 9 10 11 12 13 14 15 19 20 43 47 0.1uF C3 0.1uF C6 GND 0.1uF C7 TP2 TP 0.1uF C8 NC NC NC NC NC NC 21 22 23 24 25 28 29 30 99 85 84 83 80 79 TP3 TP 31 82 75 77 45 TP4 TP TP5 TP 35 FID0 36 FID1 37 FID2 BURL DDS OUT CBYP PFD IN PXCK 88 COMP 70 VREF 68 RT 57 RB 17 INT 34 VALID 40 LDV 32 GHSYNC 33 GVSYNC CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 0.1uF C9 1 1 CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 GPXCK H2 H1 GHSYNC GVSYNC 0.1uF C17 C18 0.1uF CVBS[0..7] C19 150pF INDUCTOR L1 6.8pF C13 C20 390pF C14 0.1uF VCC GHSYNC GVSYNC GPXCK C16 0.1uF R4 3.3K C8 NOT INSTALLED IF CR10 IS INSTALLED C15 0.1uF C12 0.1uF GPXCK CVBS[0..7] CR1 1.235V VALID GHSYNC GVSYNC 1 C10 TP1 TP Preliminary Information + 2 VCC PRELIMINARY INFORMATION TMB22153AMS100 6 C23 0.1uF C22 0.1uF VCC CVBS[0..7] DECCLK SDA SCL AVOUT PGM_OUT PGM_START SWW DHSYNC DVSYNC HS VS 675MHZ 0.1uF C24 0.1uF C25 0.1uF C26 0.1uF C27 CVBS[0..7] DECCLK SDA SCL AVOUT PGM_OUT PGM_START SWW DHSYNC DVSYNC HS VS 3 4 0.1uF C28 2 1K 1K DATA 1K R38 0.1uF C29 EPC1PC8 6 0.1uF C64 0.1uF C65 1K 1K 1 R40 R39 0.1uF C30 DCLK nCASC OE nCS U9 R37 R36 VCC H15 H9 H11 1 1 1 FSER HS VS BUFFER CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 DECCLK CREF D1ENFS 8 9 10 12 13 17 18 19 20 21 22 23 26 27 28 29 30 31 32 125 55 122 128 54 56 124 126 105 4 1 34 116 114 113 112 111 110 109 108 106 3 142 141 144 143 11 7 107 2 14 77 76 35 74 EPF10K10TC144 8 9 10 12 13 17 18 19 20 21 22 23 26 27 28 29 30 31 32 GCLK0 GCLK1 DEV_CLRn DEV_OE DEDIN DEDIN DEDIN DEDIN TDI TDO TCLK TMS DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 nCE nCEO nW S nRS nCS CS RDYnBSY CLKUSR DCLK CONF_DONE INIT_DONE MSEL0 MSEL1 nSTATUS nCONFIG U2 140 138 137 136 135 133 132 131 130 121 120 119 118 117 102 101 100 99 98 97 96 95 92 91 90 89 88 87 86 83 82 81 80 79 78 73 72 70 69 68 67 65 64 63 62 60 59 51 49 48 47 46 44 43 42 41 39 38 37 36 33 140 138 137 136 135 133 132 131 130 121 120 119 118 117 102 101 100 99 98 97 96 95 92 91 90 89 88 87 86 83 82 81 80 79 78 73 72 70 69 68 67 65 64 63 62 60 59 51 49 48 47 46 44 43 42 41 39 38 37 36 33 FSOE COE10 YOE10 CLAMP DCSB DA1 DA0 1 1 GRAB PIXEL_GRAB LINE_GRAB PGM_OUT BLANK\(DAC) SDA SCL D1 RGB 1 NTSC/PAL VREF HREF OHS OVS MPU7 MPU6 MPU5 MPU4 MPU3 MPU2 MPU1 MPU0 AVOUT DHSYNC DVSYNC MASTER1 MASTER0 PGM_START YOVER9 YOVER8 YOVER7 YOVER6 YOVER5 YOVER4 YOVER3 YOVER2 YOVER1 YOVER0 COVER9 COVER8 COVER7 COVER6 COVER5 COVER4 COVER3 COVER2 COVER1 COVER0 DRW SWW FSET H10 H5 H12 TP6 TP TP TP7 TP TP TP8 TP TP TP9 TP TP D1ENFS HREF CREF VREF TP TP D1ENFS HREF CREF VREF TP TP31 TP TP TP30 TP TP26 TP27 TP28 TP29 TP TP21 TP22 TP23 TP24 TP25 Preliminary Information MPU[0..7] H4 H6 H7 CLAMP DRW FSOE YOE10 COE10 FSER OHS OVS FSET 1 1 1 MPU[0..7] BLANK\(DAC) NTSC/PAL RGB D1 BUFFER MASTER0 MASTER1 COVER[0..9] YOVER[0..9] CLAMP DRW FSOE YOE10 COE10 FSER OHS OVS FSET DCSB DA1 DA0 DECODER PARALLEL INTERFACE BLANK\(DAC) NTSC/PAL RGB D1 BUFFER MASTER0 MASTER1 COVER[0..9] YOVER[0..9] TMB22153AMS100 PRELIMINARY INFORMATION VS HS FSIN_CLK D1ENFS YOVER[0..9] FSER SCL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SDA GND 2 3 4 5 6 7 8 9 VDD 11 12 13 14 15 16 17 18 GND 20 21 22 23 24 25 26 27 28 29 VDD 31 32 33 34 35 36 37 38 GND 40 41 42 43 44 45 46 47 VDD 49 50 51 52 53 54 55 56 57 58 VDD 60 61 62 63 64 65 66 67 68 69 70 71 FSOE 1 19 39 72 RESET\ Preliminary Information 7 YOVER1 YOVER0 YOVER9 YOVER8 YOVER7 YOVER6 YOVER5 YOVER4 YOVER3 YOVER2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 COVER1 COVER0 COVER9 COVER8 COVER7 COVER6 COVER5 COVER4 COVER3 COVER2 GND P1 SIMM72 VCC IXPXCK IXVSYNC\ IXHSYNC\ COVER[0..9] PRELIMINARY INFORMATION TMB22153AMS100 8 BLANK\(DAC) RGB PGM_OUT D1 NTSC/PAL VREF VALID CREF HREF FID_0 RESET\ SCL SDA OVS OHS BU[0..9] GY[0..9] MPU[0..4] RV[0..9] BLANK\(DAC) RGB PGM_OUT D1 NTSC/PAL VREF LOCK CREF HREF ODD IN RESET\ SCL SDA OVS OHS BU[0..9] GY[0..9] RV[0..9] MPU[0..4] GY6 GY7 GY8 GY9 GY1 GY2 GY3 GY4 GY5 GY0 HEADER 10 7 8 9 10 2 3 4 5 6 1 JP4 BLANK\(DAC) ODD IN NTSC/PAL RGB D1 RESET\ SCL OVS OHS HREF VREF Y6 Y7 Y8 Y9 CREF Y1 Y2 Y3 Y4 Y5 Y0 LOCK 39 41 43 45 47 31 33 35 37 21 23 25 27 29 11 13 15 17 19 3 5 7 9 1 HEADER 24X2 23 24 18 19 20 21 22 13 14 15 16 17 9 10 11 12 4 5 6 7 8 1 2 3 JP6A 32 34 36 38 40 42 44 46 48 BU3 BU4 BU5 BU6 BU7 BU8 BU9 PGM_OUT SDA 22 24 26 28 30 12 14 16 18 20 RV3 RV4 RV5 RV6 RV7 RV8 RV9 BU0 BU1 BU2 4 6 8 10 RV0 RV1 RV2 2 HEADER 24X2 23 24 18 19 20 21 22 13 14 15 16 17 9 10 11 12 4 5 6 7 8 1 2 3 JP6B Preliminary Information MPU1 MPU2 MPU3 MPU4 MPU0 HEADER 10 7 8 9 10 2 3 4 5 6 1 JP7 Y[0..9] Y[0..9] TMB22153AMS100 PRELIMINARY INFORMATION C61 1 SDA SCL 135MHZ P0 P1 P2 P3 1 2 3 4 2 1 SW DIP-4 S2 MRST S1 74F14 10K U4A R43 10.0uF/16V VCC 8 7 6 5 MRESET\ VCC 74F14 135MHZ SDA SCL 3 U4B VCC 0.1uF C62 4 4K7 R42 R11 10K R10 10K 10K R12 PGM_START VCC 135MHZ H32 PROG0 PROG1 PROG2 PROG3 10K R13 H28 1 135MHZ MRESET JP11 H27 1 H26 RESET\ 1 1 10 20 21 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 EA/VPP ALE/PROG PSEN P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 VCC AT89C55 44 PIN PLCC U13 RST XTAL2 XTAL1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 CAS_PROGEN CASCADE INIT SJ2 4K7 R44 MRESET\ PROG0 PROG1 PROG2 PROG3 H25 SCL SDA VCC 1 12 23 34 NC NC NC NC 35 33 32 11 13 14 15 16 17 18 19 24 25 26 27 28 29 30 31 0.1uF C63 1 1 1 VCC 4 3 2 1 H19 PGM_IN PGM_OUT CAS_PROGEN DRST\ GRST\ H17 H18 SCL +5V SDA GND 15-83-0064 P2 VCC 1 1 1 1 H30 H29 H20 1 1 H31 H21 10K R16 F BEAD FB1 Preliminary Information 9 1 H22 1 H23 10K R17 1 H24 1OHM, 1/4W C R15 PGM_OUT GRST\ DRST\ RESET\ PGM_START RBUSEN JP2 PGM_OUT GRST\ DRST\ RESET\ PGM_START SDA SCL PRELIMINARY INFORMATION TMB22153AMS100 10 COE10 YOE10 ADCLK2 CLAMP 2 COE10 YOE10 J2 CROMA 1 2 J1 LUMA 1 4 3 1 2 DIS FPGA DIS FPGA S-VIDEO J3 CEN E2 YEN E1 CLAMP R23 75 0.1uF R24 10K 10K C40 R20 75 100uF/6.3V R19 100uF/6.3V C38 + C37 + 220 R22 220 R18 R21 4.75K VCC 4.75K R25 ADCLK VCC 18 19 20 23 17 1 18 19 20 23 17 1 FE-100H DEC_N SYNC CLK BP_PULSE OE_N VIDEO_IN U6 FE-100H DEC_N SYNC CLK BP_PULSE OE_N VIDEO_IN U5 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VID_BUF D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VID_BUF 16 15 14 13 12 11 10 9 8 7 6 5 24 16 15 14 13 12 11 10 9 8 7 6 5 24 0.1uF C41 VCC TP34 C39 TP 0.1uF VCC 0.01uF C70 VCC 0.01uF C66 VCC 0.1uF C71 VCC 0.01uF C72 VCC 0.01uF C68 COVER9 COVER8 COVER7 COVER6 COVER5 COVER4 COVER3 COVER2 COVER1 COVER0 VCC 0.1uF C67 VCC YOVER9 YOVER8 YOVER7 YOVER6 YOVER5 YOVER4 YOVER3 YOVER2 YOVER1 YOVER0 R45 75 Preliminary Information ADCLK1 0.1uF C59 VEE 0.1uF C58 VEE 0.01uF C73 VEE 0.01uF C69 VEE COVER[0..9] YOVER[0..9] COVER[0..9] YOVER[0..9] AN COMP/LUMA PRELIMINARY INFORMATION TMB22153AMS100 11 SCL SDA MPU[0..7] COVER[0..9] YOVER[0..9] DCSB DA1 DA0 DRST\ DRW BUFFER MASTER0 MASTER1 HS VS DECCLK FSET GA0 GA1 GA2 DA0 DA1 DA2 SER HILO 1 2 3 4 5 6 7 8 1 16 15 14 13 12 11 10 9 DCSB DA1 DA0 DRST\ SMT SW-8 S4 R28 4.7K BUFFER MASTER0 MASTER1 FSET R29 4.7K R30 4.7K R31 4.7K R32 4.7K R33 4.7K R34 4.7K VS HILO SET E3 SELECT MPU[0..7] COVER[0..9] YOVER[0..9] SWQ SWR SWS SWT SWU SWV SWW SWX R35 4.7K 54 55 56 59 58 SWT SWU SWV SCL SDA C42 0.1uF 52 51 53 SET DRST\ SWW VCC 62 63 36 37 38 41 42 43 44 45 60 61 DA0 DA1 MPU0 MPU1 MPU2 MPU3 MPU4 MPU5 MPU6 MPU7 DCSB 89 3 48 49 66 67 68 69 70 71 72 73 74 75 COVER0 COVER1 COVER2 COVER3 COVER4 COVER5 COVER6 COVER7 COVER8 COVER9 1 77 78 79 80 81 82 83 84 85 86 YOVER0 YOVER1 YOVER2 YOVER3 YOVER4 YOVER5 YOVER6 YOVER7 YOVER8 YOVER9 H16 50 87 88 BUFFER MASTER0 MASTER1 C43 0.1uF TMC22153KHC SA_0 SA_1 SA_2 SCL SDA SET RESET SER A_0 A_1 D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 CS R/W CLOCK LDV HSYNC VSYNC VIDEOB_0 VIDEOB_1 VIDEOB_2 VIDEOB_3 VIDEOB_4 VIDEOB_5 VIDEOB_6 VIDEOB_7 VIDEOB_8 VIDEOB_9 VIDEOA_0 VIDEOA_1 VIDEOA_2 VIDEOA_3 VIDEOA_4 VIDEOA_5 VIDEOA_6 VIDEOA_7 VIDEOA_8 VIDEOA_9 BUFFER MASTER0 MASTER1 U7 C44 0.1uF C45 0.1uF FID_0 FID_1 FID_2 AVOUT DHSYNC DVSYNC R/CR_0 R/CR_1 R/CR_2 R/CR_3 R/CR_4 R/CR_5 R/CR_6 R/CR_7 R/CR_8 R/CR_9 B/CB_0 B/CB_1 B/CB_2 B/CB_3 B/CB_4 B/CB_5 B/CB_6 B/CB_7 B/CB_8 B/CB_9 G/Y_0 G/Y_1 G/Y_2 G/Y_3 G/Y_4 G/Y_5 G/Y_6 G/Y_7 G/Y_8 G/Y_9 RV0 RV1 RV2 RV3 RV4 RV5 RV6 RV7 RV8 RV9 27 26 25 24 23 22 21 20 19 18 C46 0.1uF BU0 BU1 BU2 BU3 BU4 BU5 BU6 BU7 BU8 BU9 15 14 13 12 11 10 9 8 7 6 31 32 33 30 34 35 GY0 GY1 GY2 GY3 GY4 GY5 GY6 GY7 GY8 GY9 2 1 100 99 98 97 96 95 94 93 Preliminary Information VCC C47 0.1uF C48 0.1uF SWQ SWR SWS SWW TP10 TP11 TP12 TP13 TP14 TP15 TP TP TP TP TP TP RV[0..9] BU[0..9] GY[0..9] SA0 SA1 SA2 SWW AVOUT DHSYNC DVSYNC FID_0 RV[0..9] BU[0..9] GY[0..9] PRELIMINARY INFORMATION TMB22153AMS100 IXVSYNC\ IXHSYNC\ BLANK\(DAC) RGB PGM_OUT D1 NTSC/PAL VREF VALID CREF HREF FID_0 RESET\ SCL SDA OVS OHS BU[0..9] Y[0..9] RV[0..9] DICECLK XPXCK OUT VCC 74F14 27MHz Y2 BLANK\(DAC) RGB PGM_OUT D1 NTSC/PAL VREF LOCK CREF HREF ODD IN RESET\ SCL SDA OVS OHS VDD 0.1uF C31 BU[0..9] Y[0..9] RV[0..9] 11 U4E 5 R27 10K 10 E8 SELECT JP9 JP8 XVE XHE E4 SELECT VCC JP3 D1EN XVSYNC\ XHSYNC\ R26 4.75K PXCK4 RV0 RV1 RV2 RV3 RV4 RV5 RV6 RV7 RV8 RV9 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 BU0 BU1 BU2 BU3 BU4 BU5 BU6 BU7 BU8 BU9 VCC 3 2 EURO96M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P3A VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK D Q Q PGM_OUT XHSYNC\ XVSYNC\ XPXCK 0.01uF C60 74F74 6 5 U11A -5V VCC 11 12 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CLK D EURO96M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P3B Q Q 74F74 8 9 U11B BLANK\(DAC) SDA LOCK D1 RESET\ SCL RGB NTSC/PAL OVS OHS HREF VREF ODD IN CREF PXCK4 96 WAY EDGE CONNECTIONS FROM THE DECODER BOARD Preliminary Information 4 PR CL 1 10 PR CL 12 13 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 EURO96M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P3C 675MHZ 135MHZ IXPXCK TMB22153AMS100 PRELIMINARY INFORMATION PRELIMINARY INFORMATION TMB22153AMS100 VCC C49 0.1uF IXPXCK IXPXCK E5 SELECT U8A 1 2 ADCLK1 4 ADCLK2 ADCLK1 74F04 GPXCK GPXCK U8B 3 ADCLK2 74F04 5 TP16 DECCLK 6 SJ1 74F04 U8D SELECT 9 8 DECCLK 10 DICECLK DECCLK 74F04 U8E 11 DICECLK 74F04 U8F 13 GHSYNC FSIN_CLK 74F04 GH E6 SELECT TP17 HS IXH IXHSYNC\ GVSYNC FSIN_CLK 12 TP18 VS GV E7 HS SELECT VS IXVSYNC\ IXV 13 Preliminary Information U8C TMB22153AMS100 PRELIMINARY INFORMATION TP19 VDD VDDA VCC +5V +5V + C52 0.1uF 50V + C51 0.47uF 35V D1 1N4004 C53 0.01uF 50V D2 RED LED 1 2 C50 22uF 35V 2 1 P5V JP5 1 HEADER 3 C56 0.1uF 50V C54 22uF 35V + C55 0.47uF 35V D3 1N4004 C57 0.01uF 50V 2 FB2 TP20 D4 ORANGE LED -5V 1 + N5V 2 GND 1 2 3 Preliminary Information F BEAD UNUSED GATES U4C 5 6 74F14 U4D 9 8 74F14 U4F 13 12 74F14 14 Ground Test Points G1 G2 G3 G4 G5 GND GND GND GND GND VEE -5V PRELIMINARY INFORMATION TMB22153AMS100 OUTPUT 96 way connector (male) description and notes row A row B row C +5v 1 GND 1 +5v 2 D1 or R/V [bit 0] 2 +5V 2 GND 3 D1 or R/V [bit 1] 3 +5V 3 PXCK 4 D1 or R/V [bit 2] 4 +5V 4 GND 5 D1 or R/V [bit 3] 5 GND 5 PCK 6 D1 or R/V [bit 4] 6 Analog Composite/luma 6 GND 7 D1 or R/V [bit 5] 7 GND 7 CREF 8 D1 or R/V [bit 6] 8 Analog chroma 8 GND 9 D1 or R/V [bit 7] 9 XEN 9 VSYNC\ 10 D1 or R/V [bit 8] 10 GND 10 HSYNC\ 11 D1 or R/V [bit 9] 11 XDIR 11 HREF 12 Comp, G/Y, or Luma [bit 0] 12 XHSYNC\ 12 VREF 13 Comp, G/Y, or Luma [bit 1] 13 XVSYNC\ 13 ODD IN 14 Comp, G/Y, or Luma [bit 2] 14 XPXCK 14 GND 15 Comp, G/Y, or Luma [bit 3] 15 XRS [bit 3] 15 NTSC/PAL 16 Comp, G/Y, or Luma [bit 4] 16 XRS [bit 2] 16 CLAMP pulse 17 Comp, G/Y, or Luma [bit 5] 17 XRS [bit 1] 17 RGB 18 Comp, G/Y, or Luma [bit 6] 18 XRS [bit 0] 18 19 Comp, G/Y, or Luma [bit 7] 19 GND 19 20 Comp, G/Y, or Luma [bit 8] 20 -5V 20 21 Comp, G/Y, or Luma [bit 9] 21 -5V 21 LOCK 22 Chroma or B/U [bit 0] 22 -5V 22 D1 23 Chroma or B/U [bit 1] 23 GND 23 RESET\ 24 Chroma or B/U [bit 2] 24 PGM_OUT 24 SCL 25 Chroma or B/U [bit 3] 25 -12V 25 GND 26 Chroma or B/U [bit 4] 26 -12V 26 SDA 27 Chroma or B/U [bit 5] 27 IE (input enable) 27 OE (output enable) 28 Chroma or B/U [bit 6] 28 GND 28 BLANK\ (DAC) 29 Chroma or B/U [bit 7] 29 29 30 Chroma or B/U [bit 8] 30 30 31 Chroma or B/U [bit 9] 31 +12V 31 +12V 32 GND 32 GND 32 GND 15 Preliminary Information 1 TMB22153AMS100 PRELIMINARY INFORMATION Output Edge Connector Design notes: Signal Flow FORWARD FPGA TMC2072 TMC3003 Decoder Input Logic TMC22153 32 32 Preliminary Information SW1 SW2 High Quality LPF TMC2242 Chrominance BPF and Clamp Circuit EPROM 1 High Quality LPF Digital LPFs 1 High Quality LPF 10 bit ADCs 1 2:1 MUX TMC1185 TMC2242 TMC1185 1 Y/Composite LPF and Clamp Circuit 32 32 DC Supply SW1 +5V 0V -5V Low Quality LPF Low Quality LPF Low Quality LPF 65-B2193-14 Signal Flow BACKWARD 1. Boards with different revision letters may not be compatible; damage may occur if they are connected together. 2. XPXCK is a two times pixel clock fed BACKWARD 3. XHSYNC and XVSYNC are timing reference signals fed BACKWARD 4. The MASTER/SLAVE signal states if a board is a MASTER or a SLAVE board. This signal is fed FORWARD. A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLAVE board expects to receive XPXCK, XHSYNC, XVSYNC, etc. 5. XDIR is fed FORWARD and controls in which direction the XRS[3:0] data flows. 6. PGM_OUT negative going signal pulse for initiating programming of down stream boards, generated once the devices on the board have been programmed. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any given time. The Minimum width of PGM_OUT is 1µS. 7. The RESET pin on the output edge connector should be connected directly to the RESET pin on the input connector. A link should be used to connect any pulse to the RESET line. 8. The MASTER/SLAVE, XDIR, PGM_OUT and RESET pins on the output edge connector should be connected to +5V through a 10k pull up resistor. 9. The CLAMP signal is fed BACKWARD from a MASTER to a SLAVE board. The CLAMP signal should not be fed FORWARD. 16 PRELIMINARY INFORMATION TMB22153AMS100 Table 4. TMB22153AMS100 Parts List Item Qty. Reference Designator Description 1 1 CR1 1.235 V 2 47 C1, C2, C3, C4, C5, C6, C7, C8, C9, C12, C14, C15, C16, C17, C18, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C52, C56, C58, C59, C62, C63, C64, C65, C67, C71 0.1 µF 3 2 C10, C11 0.01 µF 4 1 C13 6.8 pF 5 1 C19 150 pF 6 1 C20 390 pF 2 C37, C38 100 uF / 6.3 V 2 C50, C54 22 µF 9 2 C51, C55 0.47 µF 10 9 C53, C57, C60, C66, C68, C69, C70, C72, C73 0.01 µF 11 1 C61 10.0 µF / 16V 12 2 D1, D3 1N4004 13 1 D2 LED RED 14 1 D4 LED ORANGE 16 9 SJ1, E1, E2, E3, E4, E5, E6, E7, E8 SELECT 17 2 FB1, FB2 F BEAD 18 5 G1, G2, G3, G4, G5 GND LOOP 19 29 H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, H18, H19, H20, H21, H22, H23, H24, H25, H26, H27, H28, H32 PTH 20 5 JP2, JP3, JP8, JP9, JP11 HEADER2 21 2 JP4, JP7 HEADER10 22 1 JP6 HEADER24X2 23 1 J1 BNC LUMA 24 1 J2 BNC CHROMA 25 1 J3 CON S-VIDEO 26 1 L1 INDUCTOR 27 1 P1 HEADER72X2 SIMM72 28 1 P2 15-83-0064 29 1 P3 EURO96M 30 5 R1, R2, R3, R19, R23 75 OHM 31 1 R4 3.3 KOHM 32 5 R5, R6, R21, R25, R26 4.75 KOHM 33 10 R10, R11, R12, R13, R16, R17, R20, R24, R27, R43 10 KOHM 34 1 R15 1 OHM / 1/4W C 35 3 R18, R22, R45 220 OHM 36 10 R28, R29, R30, R31, R32, R33, R34, R35, R42, R44 4.7 KOHM 37 5 R36, R37, R38, R39, R40 1 KOHM 38 1 SJ2 CASCADE INIT 39 1 S1 PUSHBUTTON MRST 17 Preliminary Information 7 8 TMB22153AMS100 Item Preliminary Information 40 Qty. 1 PRELIMINARY INFORMATION Reference Designator Description S2 SW DIP-4 41 1 S4 SW DIP-8 42 32 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14, TP15, TP16, TP17, TP18, TP19, TP20, TP21, TP22, TP23, TP24, TP25, TP26, TP27, TP28, TP29, TP30, TP31, TP34 TP 43 1 U1 TMC2072KHC 44 1 U2 EPF10K10TC144 45 1 U4 74F14 46 2 U5, U6 FE-100H 47 1 U7 TMC22153AKHC 48 1 U8 74F04 49 1 U9 EPC1PC8 50 1 U11 74F74 51 1 U13 AT89C55 44 PIN PLCC 52 1 Y1 20MHz CRYSTAL 53 1 Y2 27MHz CRYSTAL 18 PRELIMINARY INFORMATION TMB22153AMS100 Notes: Preliminary Information 19 TMB22153AMS100 PRELIMINARY INFORMATION Ordering Information Product Number TMB22153AMS100 Temperature Range 25°C Speed Grade 27 MHz Screening Package Commercial 4" by 5" Printed Circuit Board Package Marking TMB22153AMS100 The TMC2070P7C parallel port to R-bus board, interface cable, Raydemo software, and all relevant documentation are included in the TMB22153AMS100 purchase price. Preliminary Information A schematic database is available in OrCAD format, along with EPROM maps. More information on the EPLD/FPGA design is also available. Contact the factory. The TMB22153AMS100 Demonstration Board, design documentation, and software are provided as a design example for the customers of Fairchild. Fairchild makes no warranties, express, statutory, or implied regarding merchantability or fitness for a particular purpose. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/20/99 0.0m 002 Stock#DS70022153AMS100 1998 Fairchild Semiconductor Corporation