SBAS271 − MARCH 2004 FEATURES D Low Glitch: 1nV-s (typ) D Low Power: 18mW D Unipolar or Bipolar Operation D Settling Time: 12µs to 0.003% D 16-Bit Linearity and Monotonicity: D D D D D D DESCRIPTION The DAC7664 is a 16-bit, quad voltage output digital-to-analog converter (DAC) with 16-bit monotonic performance over the specified temperature range. It accepts 16-bit parallel input data, has double-buffered DAC input logic (allowing simultaneous update of all DACs), and provides a readback mode of the internal input registers. Programmable asynchronous reset clears all registers to a mid-scale code of 8000h or to a zero-scale of 0000h. The DAC7664 can operate from a single +5V supply or from +5V and −5V supplies. –40°C to +85°C Programmable Reset to Mid-Scale or Zero-Scale Data Readback Double-Buffered Data Inputs Internal Bandgap Voltage Reference Power-On Reset 3V to 5V Logic Interface APPLICATIONS D Process Control D Closed-Loop Servo Control D Motor Control D Data Acquisition Systems D DAC-per-Pin Programmers Low power and small size per DAC make the DAC7664 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo control. The DAC7664 is available in an LQFP-64 package and is specified for operation over the −40°C to +85°C temperature range. VD D VS S VC C VR E F H A and B DAC7664 VR E F L A and B Bandgap Voltage Reference DB0−DB15 Data Latch Input Register A DAC Register A VO U T A Sense 2 VO U T A Sense 1 VO U T A DAC A VR E F Input Register B DAC Register B VO U T B Sense 2 VO U T B Sense 1 VO U T B DAC B VR E F Input Register C A0 DAC Register C RST VR E F Control Logic RSTSEL LDAC Input Register D DAC Register D OFSR2C OFSR1C VO U T D Sense 2 VO U T D Sense 1 VO U T D DAC D R/W VR E F VR E F L C and D OFSR2B OFSR1B VO U T C Sense 2 VO U T C Sense 1 VO U T C DAC C A1 CS OFSR2A OFSR1A OFSR2D OFSR1D VRE F H C and D A G ND D GND This device has ESD-CDM sensitivity and special handling precautions must be taken. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2004, Texas Instruments Incorporated !" #$ % & % # '& ( &% &#$ %&#& % ) $% # * % !%$% % + ,( & &%% % &%% , & % # $%( www.ti.com www.ti.com SBAS271 − MARCH 2004 ORDERING INFORMATION(1) PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC7664Y LQFP−64 PM −40°C to +85°C DAC7664Y DAC7664YB LQFP−64 PM −40°C to +85°C DAC7664YB DAC7664YC LQFP−64 PM −40°C to +85°C DAC7664YC ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC7664YT Tape and Reel, 250 DAC7664YR Tape and Reel, 1500 DAC7664YBT Tape and Reel, 250 DAC7664YBR Tape and Reel, 1500 DAC7664YCT Tape and Reel, 250 DAC7664YCR Tape and Reel, 1500 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) DAC7664 UNIT −0.3 to 11 V −0.3 to 5.5 V Digital Input Voltage to GND −0.3 to VDD + 0.3 V Digital Output Voltage to GND −0.3 to VDD + 0.3 V IOVDD, VCC and VDD to VSS IOVDD, VCC and VDD to GND ESD-CDM 200 V Maximum Junction Temperature +150 °C Operating Temperature Range −40 to +85 °C Storage Temperature Range −65 to +125 °C Lead Temperature (soldering, 10s) +300 °C (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. www.ti.com SBAS271 − MARCH 2004 ELECTRICAL CHARACTERISTICS: VSS = 0V All specifications at TA = TMIN to TMAX, IOVDD = VDD = VCC = +5V, and VSS = 0V, unless otherwise noted. DAC7664Y PARAMETER TEST CONDITIONS MIN TYP DAC7664YB MAX MIN DAC7664YC TYP MAX ±2 ±3 MIN TYP MAX UNIT [ [ LSB Accuracy Linearity error ±3 Linearity match ±4 Differential linearity error ±2 Monotonicity, TMIN to TMAX ±4 ±2 ±3 14 ±1 [ ±2 15 −1 LSB +2 16 LSB Bit Unipolar zero error ±1 ±5 [ [ [ [ mV Unipolar zero error drift 5 10 [ [ [ [ ppm/°C Full-scale error ±6 ±20 ±4 ±12.5 [ [ mV Full-scale error drift 7 15 [ [ [ [ ppm/°C mV Unipolar zero matching Channel-to-channel matching ±3 ±7 ±2 ±5 [ [ Full-scale matching Channel-to-channel matching ±4 ±10 ±2 ±8 [ [ mV Power-supply rejection ratio (PSRR) At full-scale 10 100 [ [ [ [ ppm/V Analog Output Voltage output RL = 10kΩ Output current Maximum load capacitance 0 2.5 [ [ [ [ V −1.25 +1.25 [ [ [ [ mA 500 [ [ pF ±20 [ [ mA Indefinite [ [ No oscillation Short-circuit current Short-circuit duration GND or VCC Dynamic Performance Settling time To ±0.003%, 2.5V output step 12 Channel-to-channel crosstalk Digital feedthrough Output noise voltage f = 10kHz DAC glitch 7FFFh to 8000h or 8000h to 7FFFh [ 15 [ [ [ µs 0.5 [ [ 2 [ [ nV-s 130 [ [ nV/√Hz 1 [ 5 [ [ LSB [ nV-s Digital Input [ 0.7 × IOVDD VIH [ 0.3 × IOVDD VIL V [ [ V IIH ±10 [ [ µA IIL ±10 [ [ µA Digital Output VOH IOH = −0.8mA, IOVDD = 5V VOL IOL = 1.6mA, IOVDD = 5V VOH IOH = −0.4mA, IOVDD = 3V VOL IOL = 0.8mA, IOVDD = 3V 3.6 0.3 2.4 [ 4.5 [ 2.6 0.3 0.4 [ [ 0.4 [ [ [ [ [ [ [ [ V [ [ V V [ [ V Power Supply VDD +4.75 +5.0 +5.25 [ [ [ [ [ [ V IOVDD +2.7 +5.0 +5.25 [ [ [ [ [ [ V VCC +4.75 +5.0 +5.25 [ [ [ [ [ [ V VSS 0 0 0 [ [ [ [ [ [ V ICC 3.5 5 [ [ [ [ mA IDD 50 [ [ I(IOVDD) 50 [ [ µA Power 18 [ mW [ 25 [ µA Temperature Range Specified performance −40 +85 [ [ [ [ °C [ specifications same as the grade to the left 3 www.ti.com SBAS271 − MARCH 2004 ELECTRICAL CHARACTERISTICS: VSS = −5V All specifications at TA = TMIN to TMAX, IOVDD = VDD = VCC = +5V, and VSS = −5V, unless otherwise noted. DAC7664Y PARAMETER TEST CONDITIONS MIN TYP DAC7664YB MAX MIN DAC7664YC TYP MAX ±2 ±3 MIN TYP MAX UNIT [ [ LSB Accuracy Linearity error ±3 Linearity match ±4 Differential linearity error ±2 ±3 ±1 ±5 Monotonicity, TMIN to TMAX ±4 ±2 14 [ ±1 ±2 [ [ 15 Bipolar zero error −1 LSB +2 LSB [ [ mV ppm/°C 16 Bit Bipolar zero error drift 5 10 [ [ [ [ Full-scale error ±6 ±20 ±4 ±12.5 [ [ mV Full-scale error drift 7 15 [ [ [ [ ppm/°C mV Bipolar zero matching Channel-to-channel matching ±3 ±7 ±2 ±5 [ [ Full-scale matching Channel-to-channel matching ±4 ±10 ±2 ±8 [ [ mV Power-supply rejection ratio (PSRR) At full-scale 10 100 [ [ [ [ ppm/V Analog Output Voltage output RL = 10kΩ Output current Maximum load capacitance −2.5 +2.5 [ [ [ [ V −1.25 +1.25 [ [ [ [ mA Short-circuit duration 500 [ [ pF −15, +30 [ [ mA Indefinite [ [ No oscillation Short-circuit current GND or VCC or VSS Dynamic Performance Settling time To ±0.003%, 5V output step 12 Channel-to-channel crosstalk Digital feedthrough Output noise voltage f = 10kHz DAC glitch 7FFFh to 8000h or 8000h to 7FFFh [ 15 [ [ [ µs 0.5 [ [ 2 [ [ nV-s 200 [ [ nV/√Hz 2 [ 7 [ [ LSB [ nV-s Digital Input [ 0.7 × IOVDD VIH [ V [ [ V IIH ±10 [ [ µA IIL ±10 [ [ µA 0.3 × IOVDD VIL Digital Output VOH IOH = −0.8mA, IOVDD = 5V VOL IOL = 1.6mA, IOVDD = 5V VOH IOH = −0.4mA, IOVDD = 3V VOL IOL = 0.8mA, IOVDD = 3V 3.6 0.3 2.4 [ 4.5 [ 0.4 [ 2.6 0.3 0.4 [ [ [ [ [ [ [ [ [ V [ [ V V [ [ V Power Supply VDD IOVDD +4.75 +5.0 +5.25 [ [ [ [ [ [ V +2.7 +5.0 +5.25 [ [ [ [ [ [ V VCC VSS +4.75 +5.0 +5.25 [ [ [ [ [ [ V −5.25 −5.0 −4.75 [ [ [ [ [ [ V 4 5.5 [ [ [ [ mA ICC IDD I(IOVDD) ISS −3.5 Power 50 [ [ 50 [ [ µA [ mA [ mW [ −2.0 30 [ [ 45 [ [ µA Temperature Range Specified performance [ specifications same as the grade to the left 4 −40 +85 [ [ [ [ °C www.ti.com SBAS271 − MARCH 2004 PIN ASSIGNMENTS NC NC NC RSTSEL RST A0 A1 NC NC 44 NC 45 NC 46 VOUTD Sense 2 47 VOUTD Sense 1 NC 48 VOUTD NC LQFP PACKAGE (TOP VIEW) 43 42 41 40 39 38 37 36 35 34 33 Offset D Range 1 49 32 LDAC Offset D Range 2 50 31 R/W Offset C Range 2 51 30 CS Offset C Range 1 52 29 DB0 VOUTC Sense 2 53 28 DB1 VOUTC Sense 1 54 27 DB2 VOUTC 55 26 DB3 REF GND 56 25 DB4 DAC7664 REF GND 57 24 DB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DB13 NC NC 17 DB12 DB14 Offset A Range 1 64 DB15 18 DB11 IOVDD Offset A Range 2 63 VDD 19 DB10 DGND Offset B Range 2 62 AGND 20 DB9 VOUTA Sense 2 Offset B Range 1 61 VOUTA Sense 1 21 DB8 VOUTA VOUTB Sense 2 60 VCC 22 DB7 VSS VOUTB Sense 1 59 NC 23 DB6 NC VOUTB 58 5 www.ti.com SBAS271 − MARCH 2004 Terminal Functions PIN NAME 1 NC No Connection 2 NC No Connection 3 VSS VCC VOUTA Analog –5V power supply or 0V single supply VOUTA Sense 1 VOUTA Sense 2 Connect to VOUTA for bipolar mode 4 5 6 7 PIN NAME DESCRIPTION 38 RSTSEL Reset select. Determines the action of RST. If high, an RST command sets the DAC registers to mid-scale (8000h). If low, an RST command sets the DAC registers to zero (0000h). DAC A output voltage 39 NC No connection Connect to VOUTA for unipolar mode 40 NC No connection 41 NC No connection 42 NC No connection 43 NC No connection 44 VOUTD Sense 2 Connect to VOUTD for bipolar mode 45 VOUTD Sense 1 Connect to VOUTD for unipolar mode DAC D output No connection Analog +5V power supply 8 AGND Analog ground 9 DGND Digital ground 10 Digital +5V power supply 12 VDD IOVDD DB15 Data bit 15 (MSB) 46 13 DB14 Data bit 14 47 VOUTD NC 14 DB13 Data bit 13 48 NC 15 NC No connection 49 16 NC No connection Offset D Range 1 Connect to Offset D Range 2 for unipolar mode 17 DB12 Data bit 12 50 18 DB11 Data bit 11 Offset D Range 2 Connect to Offset D Range 1 for unipolar mode 19 DB10 Data bit 10 51 20 DB9 Data bit 9 Offset C Range 2 Connect to Offset C Range 1 for unipolar mode 21 DB8 Data bit 8 52 22 DB7 Data bit 7 Offset C Range 1 Connect to Offset C Range 2 for unipolar mode 23 DB6 Data bit 6 53 VOUTC Sense 2 Connect to VOUTC for bipolar mode 24 DB5 Data bit 5 54 25 DB4 Data bit 4 VOUTC Sense 1 Connect to VOUTC for unipolar mode 26 DB3 Data bit 3 55 DB2 Data bit 2 56 VOUTC REF GND DAC C output 27 28 DB1 Data bit 1 57 REF GND Reference ground 29 DB0 Data bit 0 58 DAC B output 30 CS Chip select, active low 59 31 R/W Enabled by CS; controls the data read and data write. VOUTB VOUTB Sense 1 60 LDAC DAC register load control, rising edge triggered. VOUTB Sense 2 Connect to VOUTB for bipolar mode 32 61 33 NC No connection Offset B Range 1 Connect to Offset B Range 2 for unipolar mode 34 NC No connection 62 35 A1 Enabled by CS; in combination with A0, selects the individual DAC input registers. Offset B Range 2 Connect to Offset B Range 1 for unipolar mode 63 36 A0 Enabled by CS; in combination with A1, selects the individual DAC input registers. Offset A Range 2 Connect to Offset A Range 1 for unipolar mode 64 37 RST Offset A Range 1 Connect to Offset A Range 2 for unipolar mode 11 6 DESCRIPTION Interface power supply Reset, rising edge triggered. Depending on the state of RSTSEL, the DAC registers are set to either mid-scale or zero. No connection Reference ground Connect to VOUTB for unipolar mode www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = 0V (+25°C) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted. DLE (LSB) 8000h A000h C000h E000h FFFFh 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 1 Figure 2 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25_ C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25_ C) 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 6000h 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25_ C) LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25_ C) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 3 Figure 4 7 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = 0V (+85°C) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted. DLE (LSB) Figure 5 Figure 6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85_ C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +85_ C) 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh 8 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 A000h C000h E000h FFFFh 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 Digital Input Code DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85_ C) LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85_ C) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 7 Figure 8 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = 0V (−40°C) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted. 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, −40_C) 8000h A000h C000h E000h FFFFh 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 9 Figure 10 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, −40_C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, −40_ C) LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, −40_C) 8000h A000h C000h E000h FFFFh Digital Input Code Figure 11 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Figure 12 9 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = 0V All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs DIGITAL INPUT CODE 5.0 5.0 All DACs at Midscale No Load 4.5 4.0 4.0 ICC 3.5 3.5 3.0 ICC (mA) ICC (mA) All DACs No Load 4.5 2.5 2.0 2.5 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 ICC 3.0 0 −40 −15 10 35 60 0000h 85 8000h A000h C000h E000h FFFFh Digital Input Code Figure 13 Figure 14 ZERO−SCALE ERROR vs TEMPERATURE POSITIVE FULL−SCALE ERROR vs TEMPERATURE 10 10 (Code 0000h) 8 Positive Full−Scale Error (mV) 8 6 Zero−Scale Error (mV) 2000h 4000h 6000h Temperature (_C) 4 DAC B DAC C 2 0 −2 DAC A −4 DAC D −6 −8 −10 −40 (Code FFFFh) 6 DAC D 4 DAC B 2 0 −2 DAC C −4 DAC A −6 −8 −10 −15 10 35 60 −40 85 −15 10 35 Temperature (_C) Temperature (_ C) Figure 15 Figure 16 BROADBAND NOISE (Code = 8000h, BW = 10kHz) 60 85 OUTPUT NOISE VOLTAGE vs FREQUENCY Noise (nV√Hz) Noise Voltage (100µV/div) 1000 100 10 Time (10ms/div) 10 100 1k 10k Frequency (Hz) Figure 17 10 Figure 18 100k 1M www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = 0V (continued) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted. SETTLING TIME (0V to +2.5V) SETTLING TIME (+2.5V to 39mV) Small Signal: 100µV/div Output Voltage Output Voltage Large Signal: 1.0V/div Large Signal: 1.0V/div Small Signal: 100µV/div Figure 19 Figure 20 MIDSCALE GLITCH PERFORMANCE CODE 7FFFh to 8000h MIDSCALE GLITCH PERFORMANCE CODE 8000h to 7FFFh Unfiltered DAC Output DAC Output after 2K, 470pF Low−Pass Filter Output Voltage (10mV/div) Time (5µs/div) Output Voltage (10mV/div) Time (5µs/div) Unfiltered DAC Output DAC Output After 2K, 470pF Low−Pass Filter Time (0.5µs/div) Time (0.5µs/div) Figure 21 Figure 22 OVERSHOOT FOR TRANSITION OF 100 CODES CODE 32750 to 32850 OVERSHOOT FOR TRANSITION OF 100 CODES CODE 32850 to 32750 DAC Output After 2K, 470pF Low−Pass Filter 100 Codes Output Voltage (20mV/div) Output Voltage (20mV/div) Unfiltered DAC Output DAC Output After 2K, 470pF Low−Pass Filter Unfiltered DAC Output Time (1.0µs/div) Time (1.0µs/div) Figure 23 Figure 24 11 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = 0V (continued) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted. IOVDD SUPPLY CURRENT vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS VOUT vs RLOAD 5.0 0.8 4.5 Logic Supply Current (mA) 4.0 VOUT (V) 3.5 3.0 Source 2.5 2.0 1.5 1.0 Sink 0 0.1 1 RLOAD (kΩ ) Figure 25 12 0.6 0.5 0.4 0.3 0.2 0.1 0.5 0.01 Typical of One Digital Input IOVDD = 5V 0.7 10 0 100 0 1 2 3 4 Logic Input Level for Digital Inputs (V) Figure 26 5 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = −5V (+25°C) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted. LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25_ C) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 8000h A000h C000h E000h FFFFh 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Figure 27 Figure 28 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25_ C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25_ C) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh LE (LSB) Digital Input Code 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25_ C) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 29 Figure 30 13 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = −5V (+85°C) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted. 14 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85_ C) 8000h A000h C000h E000h FFFFh 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 31 Figure 32 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85_ C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +85_ C) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h LE (LSB) 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85_ C) 6000h 8000h A000h C000h E000h FFFFh 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 33 Figure 34 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = −5V (−40°C) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted. 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 0000h 2000h 4000h DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, −40_ C) 6000h 8000h A000h C000h E000h FFFFh 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 35 Figure 36 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, −40_C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, −40_C) LE (LSB) 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 0000h 2000h 4000h 6000h DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, −40_ C) 8000h A000h C000h E000h FFFFh 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 2.0 1.5 1.0 0.5 0 − 0.5 − 1.0 − 1.5 − 2.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Digital Input Code Digital Input Code Figure 37 Figure 38 15 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = −5V All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs DIGITAL INPUT CODE 5 ICC 4 3 3 2 2 1 1 0 −1 ISS −2 −5 0 −1 ISS −2 −3 −4 ICC 4 ICC (mA) ICC (mA) 5 −3 All DACs at Midscale No Load All DACs No Load −4 −5 −40 −15 10 35 60 85 0000h A000h C000h E000h FFFFh Figure 39 Figure 40 BIPO LAR ZERO ERROR vs TEMPERATURE POSITIVE FULL− SCALE ERROR vs TEMPERATURE 10 Positive Full− Scale Error (mV) (Code 8000h) 8 6 4 DAC C DAC D 2 0 −2 −4 DAC A −6 DAC B −8 −10 −40 (Code FFFFh) 8 6 DAC C 4 DAC D 2 0 −2 DAC B −4 DAC A −6 −8 −10 −15 10 35 60 −40 85 −15 10 35 Temperature (_C) Temperature (_C) Figure 41 Figure 42 NEGATIVE FULL− SCALE ERROR vs TEMPERATURE Negative Full−Scale Error (mV) 10 8 (Code 0000h) 6 DAC B 4 2 DAC A 0 −2 DAC C −4 −6 DAC D −8 −10 −40 −15 10 35 Temperature (_C) Figure 43 16 8000h Digital Input Code 10 Bipolar Zero Error (mV) 2000h 4000h 6000h Temperature (_C) 60 85 60 85 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = −5V (continued) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted. OUTPUT NOISE VOLTAGE vs FREQUENCY 1000 Noise (nV√Hz) Noise Voltage (100µV/div) BROADBAND NOISE (Code = 8000h, BW = 10kHz) 100 10 10 Time (10ms/div) 100 1k 10k 100k 1M Frequency (Hz) Figure 44 Figure 45 SETTLING TIME (−2.5V to +2.5V) SETTLING TIME (+2.5V to −2.5V) Small Signal: 100µV/div Output Voltage Output Voltage Large Signal: 1.0V/div Small Signal: 100µV/div Time (5µs/div) Time (5µs/div) Figure 46 Figure 47 MIDSCALE GLITCH PERFORMANCE CODE 7FFFh to 8000h MIDSCALE GLITCH PERFORMANCE CODE 8000h to 7FFFh Unfiltered DAC Output DAC Output after 2K, 470pF Low−Pass Filter Output Voltage (10mV/div) Output Voltage (10mV/div) Large Signal: 1.0V/div Unfiltered DAC Output DAC Output After 2K, 470pF Low−Pass Filter Time (0.5µs/div) Time (0.5µs/div) Figure 48 Figure 49 17 www.ti.com SBAS271 − MARCH 2004 TYPICAL CHARACTERISTICS: VSS = −5V (continued) All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted. OVERSHOOT FOR TRANSITION OF 100 CODES CODE 32750 to 32850 OVERSHOOT FOR TRANSITION OF 100 CODES CODE 32850 to 32750 Output Voltage (20mV/div) Output Voltage (20mV/div) Unfiltered DAC Output DAC Output After 2K, 470pF Low−Pass Filter 100 Codes DAC Output After 2K, 470pF Low−Pass Filter Unfiltered DAC Output Time (1.0µs/div) Time (1.0µs/div) Figure 50 Figure 51 VOUT vs RLOAD 5 4 Source 3 VOUT (V) 2 1 0 −1 Sink −2 −3 −4 −5 0.01 0.1 1 RLOAD (kΩ) Figure 52 18 10 100 www.ti.com SBAS271 − MARCH 2004 THEORY OF OPERATION The DAC7664 is a quad voltage output 16-bit DAC. The architecture is an R−2R ladder configuration with the three most significant bits (MSBs) segmented, followed by an operational amplifier that serves as a buffer. Each DAC has its own R−2R ladder network, segmented MSBs, and output op amp, as shown in Figure 53. The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the internal voltage references and the resistors associated with the output operational amplifier. The digital input is a 16-bit parallel word and the DAC input registers offer readback capability. The converters can be powered from either a single +5V supply or a dual ±5V supply. The device offers a reset function that immediately sets all DAC output voltages and DAC registers to mid-scale (code 8000h) or to zero-scale, code 0000h. See Figure 54 and Figure 55 for the basic operation of the DAC7664. VOUTS1 13KΩ 13KΩ VOUTS2 100Ω R VOUT 2R 2R 2R 2R 2R 2R 2R 2R 2R OFSR2 13KΩ 11KΩ OFSR1 12KΩ VREFH VREFL Figure 53. DAC7664 Architecture 19 www.ti.com 0V to +2.5V 50 Offset D Range 2 43 42 41 40 39 38 37 36 35 34 33 NC NC NC NC NC RSTSEL RST A0 A1 NC NC 44 VOUTD Sense 2 NC 45 49 Offset D Range 1 0V to +2.5V NC NC NC NC NC NC NC NC 46 VOUTD Sense 1 47 VOUTD 48 NC NC NC DAC Select RESET SBAS271 − MARCH 2004 LDAC 32 R/W 31 Read/Write 51 Offset C Range 2 CS 30 Chip Select 52 Offset C Range 1 (LSB) DB0 29 NC 53 VOUTC Sense 2 DB1 28 54 VOUTC Sense 1 DB2 27 55 VOUTC DB3 26 DAC7664 Single Supply 56 Reference GND 57 Reference GND DB4 25 DB5 24 NC = No Connection 58 VOUTB DB6 23 59 VOUTB Sense 1 DB7 22 NC 60 VOUTB Sense 2 DB8 21 10 11 12 13 14 NC 0V to +2.5V NC 9 DB12 17 NC 8 DB13 7 DB14 6 DB11 18 DB15 (MSB) 5 IOVDD 4 VDD 3 NC NC DGND 2 64 Offset A Range 1 AGND VOUTA Sense 1 1 63 Offset A Range 2 VOUTA Sense 2 VOUTA DB10 19 VCC 62 Offset B Range 2 VSS DB9 20 NC 61 Offset B Range 1 NC 0V to +2.5V 15 16 NC NC DAC Input Data +5V +3V to +5V + 1µF 0.1µF 0.1µF + 1µF Figure 54. Basic Single-Supply Operation of the DAC7664 20 Load DAC Registers DAC Input Data www.ti.com −2.5V to +2.5V 43 42 41 40 39 38 37 36 35 34 33 NC NC NC NC RSTSEL RST A0 A1 NC NC NC 50 Offset D Range 2 NC NC 44 NC NC 49 Offset D Range 1 NC NC NC NC NC 45 VOUTD Sense 2 NC NC 46 VOUTD Sense 1 47 VOUTD 48 NC NC NC +5V DAC Select −2.5V to +2.5V RESET SBAS271 − MARCH 2004 LDAC 32 R/W 31 Read/Write NC 51 Offset C Range 2 CS 30 Chip Select NC 52 Offset C Range 1 (LSB) DB0 29 53 VOUTC Sense 2 DB1 28 NC 54 VOUTC Sense 1 DB2 27 55 VOUTC DB3 26 DAC7664 Dual Supply 56 Reference GND 57 Reference GND DB4 25 DB5 24 NC = No Connection 58 VOUTB DB6 23 NC 59 VOUTB Sense 1 DB7 22 60 VOUTB Sense 2 DB8 21 6 7 8 9 10 11 12 13 14 DB12 17 NC NC 5 DAC Input Data DB11 18 NC 4 DB13 VOUTA 3 DB14 VCC 2 DB15 (MSB) VSS 1 NC NC IOVDD NC NC 64 Offset A Range 1 VDD NC 63 Offset A Range 2 DGND DB10 19 AGND NC 62 Offset B Range 2 VOUTA Sense 2 DB9 20 VOUTA Sense 1 NC 61 Offset B Range 1 NC −2.5V to +2.5V Load DAC Registers 15 16 NC NC −5V + 1µF 0.1µF −2.5V to +2.5V DAC Input Data +5V +3V to +5V + 1µF 0.1µF 0.1µF + 1µF Figure 55. Basic Dual-Supply Operation of the DAC7664 21 www.ti.com SBAS271 − MARCH 2004 ANALOG OUTPUTS The DAC7664 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 56), thus ensuring an accurate output voltage. When VSS = –5V (dual-supply operation), the output amplifier can swing to within 2.25V of the supply rails over a range of –40°C to +85°C. When VSS = 0V (single-supply operation), and with RLOAD also connected to ground, the output can swing to within 5mV of ground. Care must be taken when measuring the zero-scale error when VSS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (0000h, 0001h, 0002h, etc.) if the output amplifier has a negative offset. DIGITAL INTERFACE Table 1 shows the basic control logic for the DAC7664. Note that each internal register is edge-triggered and not level-triggered. When the LDAC signal is transitioned to high, the digital word currently in the register is latched. The first set of registers (the input registers) are triggered via the A0, A1, R/W, and CS inputs. Only one of these registers is transparent at any given time. Due to the high accuracy of these DACs, system design problems such as grounding and contact resistance are very important. A 16-bit converter with a 2.5V full-scale range has a 1LSB value of 38µV. With a load current of 1mA, series wiring and connector resistance of only 40mΩ (RW2) will cause a voltage drop of 40µV, as shown in Figure 56. To understand what this means in terms of system layout, the resistivity of a typical 1-ounce copper-clad printed circuit board is 1/2 mΩ per square. For a 1mA load, a 0.01-inch-wide printed circuit conductor 0.6 inches long will result in a voltage drop of 30µV. The double-buffered architecture is designed mainly so each DAC input register can be written to at any time and then all DAC voltages updated simultaneously by the rising edge of LDAC. It also allows a DAC input register to be written to at any point and the DAC voltages to be synchronously changed via a trigger signal connected to LDAC. RW1 VOUTA Sense1 6 VOUTA 5 AGND 8 DAC7664 RW2 VOUT RW1 VOUTB Sense1 59 VOUTB 58 RW2 VOUT Figure 56. Analog Output Closed-Loop Configuration (1/2 DAC7664). RW represents wiring resistances. Table 1. DAC7664 Logic Truth Table 22 A1 A0 R/W CS RST RSTSEL LDAC INPUT REGISTER DAC REGISTER MODE DAC L L L L H X X Write Hold Write input A L H L L H X X Write Hold Write input B H L L L H X X Write Hold Write input C H H L L H X X Write Hold Write input D L L H L H X X Read Hold Read input A L H H L H X X Read Hold Read input B H L H L H X X Read Hold Read input C H H H L H X X Read Hold Read input D X X X H H X ↑ Hold Write Update All X X X H H X H Hold Hold Hold All X X X X ↑ L X Reset to zero Reset to zero Reset to zero All X X X X ↑ H X Reset to mid-scale Reset to mid-scale Reset to mid-scale All www.ti.com SBAS271 − MARCH 2004 3V TO 5V LOGIC INTERFACE DIGITAL TIMING All of the digital input and output pins are compatible with any logic supply voltage between 3V and 5V. Connect the interface logic supply voltage to the IOVDD pin. Note that the internal digital logic operates from 5V, so the VDD pin must connect to a 5V supply. Figure 57 and Table 2 provide detailed timing information for the digital interface of the DAC7664. GLITCH SUPPRESSION CIRCUIT Figure 21, Figure 22, Figure 48, and Figure 49 show the typical DAC output when switching between codes 7FFFh and 8000h. For R-2R ladder DACs, this is potentially the worst-case glitch condition, since every switch in the DAC changes state. To minimize the glitch energy at this and other code pairs with possible high-glitch outputs, an internal track-and-hold circuit is used to maintain the DAC ouput voltage at a nearly constant level during the internal switching interval. This track-and-hold circuit is activated only when the transition is at, or close to, one of the code pairs with the high-glitch possibility. It is advisable to avoid digital transitions within 1µs of the rising edge of the LDAC signal. These signals can affect the charge on the track-and-hold capacitor, thus increasing the glitch energy. DIGITAL INPUT CODING The DAC7664 input data is in straight binary format. The output voltage for single-supply operation is given by Equation 1: V OUT + 2.5 N 65, 536 (1) where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. The output for the dual supply operation is given by Equation 2: V OUT + 5 N * 2.5 65, 536 (2) 23 www.ti.com SBAS271 − MARCH 2004 CS tWCS tWS t WH R/W CS tRCS A0/A1 tLH R/W t LS tLX tLWD tAH tAS ±0.003% of FSR Error Band LDAC A0/A1 tDS tDZ Data Out t AH t AS tRDH tRDS tDH Data In tS Data Valid tCSD VOUT Data Read Timing Data Write Timing tSS ±0.003% of FSR Error Band tSH RESET SEL t RSH tRSS RST +FS VOUT, RESET SEL LOW −FS +FS MS VOUT, RESET SEL HIGH −FS DAC7664 Reset Timing Figure 57. Digital Input and Output Timing 24 www.ti.com SBAS271 − MARCH 2004 Table 2. Timing Specifications for Figure 57 SYMBOL DESCRIPTION MIN tRCS CS low for read 150 TYP MAX UNITS ns tRDS R/W high to CS low 10 ns tRDH R/W high after CS high 10 ns tDZ CS high to data bus in high impedance 10 tCSD CS low to data bus valid tWCS CS low for write 100 100 ns 150 ns 40 ns tWS R/W low to CS low 0 ns tWH R/W low after CS high 10 ns tAS Address valid to CS low 0 ns tAH Address valid after CS high 10 ns tLS CS low to LDAC high 30 ns tLH CS low after LDAC high 100 ns tLX LDAC high 100 ns tDS Data valid to CS low 0 ns tDH Data valid after CS low 10 ns tLWD LDAC low 100 ns tSS RSTSEL valid before RST high 0 ns tSH RSTSEL valid after RST high 200 ns tRSS RSTSEL low before RST high 10 ns tRSH RSTSEL low after RST high 10 ns tS Settling time 12 µs 25 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY DAC7664YBR ACTIVE LQFP PM 64 1500 DAC7664YBT ACTIVE LQFP PM 64 250 DAC7664YCR ACTIVE LQFP PM 64 1500 DAC7664YCT ACTIVE LQFP PM 64 250 DAC7664YR ACTIVE LQFP PM 64 1500 DAC7664YT ACTIVE LQFP PM 64 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. 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